CN107369713B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN107369713B CN107369713B CN201710249273.3A CN201710249273A CN107369713B CN 107369713 B CN107369713 B CN 107369713B CN 201710249273 A CN201710249273 A CN 201710249273A CN 107369713 B CN107369713 B CN 107369713B
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Abstract
本发明提供一种半导体装置及其制造方法。该半导体装置包括:基板,其包括第1面及相向于第1面的第2面;外延层,其形成在基板的第1面的上方,且具有第1导电型;基极区,其形成在外延层内,且具有与第1导电型不同的第2导电型;源极区,其形成在基极区内,且具有第1导电型;沟道区,其在基极区内,与源极区间隔而成,且具有第1导电型;及阻挡区,其形成在源极区和沟道区之间,且具有第2导电型。根据本发明能够通过阻挡区(Barrier region)来确保半导体装置的运行稳定性。
Description
技术领域
本发明涉及一种半导体装置及其制造方法。
背景技术
近年来,半导体装置变得小型化且高性能化。由此,半导体装置要求低发热性和高耐久性,尤其是金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)要求低导通电阻(ON resistance:Ron)、阈值电压变动的最小化、泄漏电流量变动的最小化等。
在MOSFET,为了防止沟道区(Channel region)内的穿通(punch-through)现象,需要长沟道耗尽区(long channel depletion region),这能引起导通电阻(Ron)的增大。
发明内容
本发明要解决的技术问题
本发明所要解决的技术问题为提供通过阻挡区(Barrier region)可以确保半导体装置的运行稳定性的半导体装置及其制造方法。
本发明的技术问题不会被上述的技术问题所限制,且技术人员可以通过以下的记载明确理解没有提及的其他技术问题。
技术方案
根据为了达到上述技术问题的本发明几个实施例的半导体装置,其包括:基板,其包括第1面及相向于第1面的第2面;外延层,其形成在基板的第1面的上方,且具有第1导电型;基极区,其形成在外延层内,且具有与第1导电型不同的第2导电型;源极区,其形成在基极区内,且具有第1导电型;沟道区,其在基极区内,与源极区间隔而成,且具有第1导电型;及阻挡区,其形成在源极区和沟道区之间,且具有第2导电型。
几个实施例中,上述阻挡区,其在上述源极区和上述沟道区之间,能够以与上述源极区及沟道区相接的方式形成。
几个实施例中,上述阻挡区,其可以具有与上述基极区相同的杂质浓度。
几个实施例中,还可以包括栅极沟槽,其形成在上述外延层内,与上述基极区间隔而成;及栅极。所述栅极包括:第1栅极部分,其在上述外延层上表面的上方,以与上述阻挡区及上述沟道区重叠的方式形成;和第2栅极部分,其以充满上述栅极沟槽的方式形成。
几个实施例中,还可以包括沟槽底部掺杂区,其在上述外延层内,形成于上述栅极沟槽的底面,且具有上述第2导电型。
几个实施例中,从上述第2栅极部分到上述阻挡区的间距,其可以大于从上述第2栅极部分到上述沟道区的间距。
几个实施例中,从上述第2栅极部分到上述源极区的间距,其可以大于从上述第2栅极部分到上述阻挡区的间距。
几个实施例中,上述源极区,上述沟道区及上述阻挡区可以形成在上述外延层的表面。
几个实施例中,还可以包括漏极,其形成在上述基板的第2面下方。
其他实施例的具体事项包括在详细的说明及附图中。
有益效果
根据本发明的半导体装置及其制造方法,可通过阻挡区确保半导体装置的运行稳定性。
附图说明
图1为根据本发明几个实施例的半导体装置的剖视图。
图2为放大图1中K区的放大图。
图3至图9为用于说明根据本发明几个实施例的半导体装置的制造方法的中间阶段的图。
图10为包括根据本发明实施例的半导体装置的芯片级系统(SoC)的框图。
附图标记的说明:
100:基板 121:源极区
123:沟道区 125:阻挡区
具体实施方式
本发明的优点和特征及其实现方法将通过结合附图详细说明的后述实施例得到进一步明确。但是本发明并不限定于下面所公开的实施例,能够以多种不同的形态实现,本说明书中的实施例仅用于更加完整地公开本发明,以便于具有本发明所属领域之一般知识的人员能够更加完整地理解本发明的范畴,本发明应由权利要求书的范畴做出定义。在整个说明书中,相同的附图标记代表相同的构成要素。
一个元件(elements)与其他元件“相接(connected to)”或者“耦联(coupledto)”指的是包括与其他元件直接相接或者耦联的情况,或者包括在中间设置其他元件的全部情况。相反,一个元件与其他元件“直接相接(directly connected to)”或者“直接耦联(directly coupled to)”指的是中间没有设置其他元件的情况。
在整个说明书中,相同的附图标记指代相同的构成要素。“及/或者”包括所提到的器件的每个以及一个以上的所有的组合。
元件(elements)或层位于其他元件或层的“上侧(on)”或“上方(on)”不仅包括直接位于其他元件或层的上侧的情况,还包括在两者之间设置其他层或其他元件的情况。与此相反,元件“直接位于上侧(directly on)”或“直接位于上方”表示两者之间不包括其他元件或层。
虽然在对各种元件、构成要素和/或部分进行说明时使用了如第1、第2等术语,但上述元件、构成要素和/或部分并不受到上述术语的限制。这些术语仅用于将一个元件、构成要素或部分与其他元件、构成要素或部分进行区分。因此,下面所提及的第1元件、第1构成要素或第1部分在本发明的技术思想范围内也可能是第2元件、第2构成要素或第2部分。
在本说明书中所使用的术语仅用于对实施例进行说明,并不是对本发明做出的限制。在本说明书中,除非另有说明,否则单数型语句包括复数型含义。在说明书中所使用的“包括(comprises)”和/或“包括...的(comprising)”不排除所提及的构成要素、步骤、动作和/或元件中还包括一个以上的其他构成要素、步骤、动作和/或元件的存在或追加的可能性。
除非另有定义,否则本说明书中所使用的所有术语(包括技术及科学术语)能够作为具有本发明所属技术领域的技术人员所普遍理解的含义使用。而且除非另有定义,已在通常所使用的词典中做出定义的术语不应被解释为理想化或过度化的含义。
以下,参照图1及图2说明关于根据本发明的几个实施例的半导体装置。
图1为根据本发明几个实施例的半导体装置的剖视图。图2为放大图1中K区的放大图。
参照图1,根据本发明的技术思想的半导体装置包括:基板100、外延层(EPIlayer)110、基极区120、栅极(gate electrode)130、源极(source electrode)150、漏极(drain electrode)160等。
基板100可以包括第1面100U和第2面100L。基板100的第1面100U可以相向于第2面100L。
基板100,例如,其可以是体硅(bulk silicon)或者绝缘体上硅(silicon-on-insulator,SOI)。与此不同,基板100也可以是硅基板,或者其他物质,例如,其可以包括碳化硅(silicon carbide)、硅锗(silicon germanium)、锑化铟(indium antimonide)、碲化铅(lead telluride)化合物、砷化铟、磷化铟、砷化镓或者锑化镓。根据本发明的技术思想的几个实施例中,基板100可以是碳化硅(SiC)基板。
基板100,例如,其可以具有n+型的导电型。n型杂质,例如其可以包括磷(P)或者氮(N)。
外延层110可以形成在基板100的第1面100U的上方。外延层110可以具有第1导电型。根据本发明技术思想的几个实施例中,第1导电型可以是n型的导电型。但是,本发明不会限制于此,第1导电型可以是p型导电型。
外延层110可以具有相比基板100的杂质浓度低的杂质浓度。例如,在基板100为n+型导电型的情况下,外延层110可以是n-型导电型。外延层110,例如,其可以包括碳化硅(SiC)。
外延层110的p型的杂质浓度,例如,实质上其可以为零。
外延层110的杂质浓度及厚度可以根据所需求的击穿电压(breakdown voltage)的大小来决定。
基极区120可以形成在外延层110内。基极区120,例如,其可以形成在外延层110的表面110s。附图中,基极区120被定义为梯形形状,但这只是为了便于说明,本发明不会限制于此。例如,根据工艺,基极区120和外延层110相接的界面可以具有曲率。
基极区120可以具有第2导电型。第二导电型可以不同于第1导电型。例如,在第1导电型为n型或者p型的情况下,第2导电型可以是p型或者n型。根据本发明技术思想的几个实施例中,基极区120可以具有p-型的导电型。p型杂质,例如,其可以包括铝(Al)或者硼(B)。
基极区120,其可以包括源极区121、p+区122、沟道区123、阻挡区125等。
源极区121可以形成在基极区120内。更具体地,源极区121,其在基极区120内,可以形成于外延层110的表面110s。源极区121的厚度,例如,其可以小于基极区120的厚度。
源极区121可以具有第1导电型。根据本发明技术思想的几个实施例中,源极区121可以具有n+型的导电型。
P+区122可以形成在基极区120内。更具体地,p+区122,其在基极区120内,可以形成于外延层110的表面110s。
附图中,p+区122以与源极区121间隔而成的方式被图示,但本发明不会限制于此。例如,p+区122还能以与源极区121直接相接的方式形成。
并且,附图中,p+区122以形成在与源极区121实际上相同的平面上的方式被图示,但本发明不会限制于此。例如,p+区122,其以基板100的第1面100U为基准,还可以形成在比源极区121高或者低的位置。
沟道区123,其可以形成在基极区120内。更具体地,沟道区123,其在基极区120内,可以形成于外延层110的表面110s。沟道区123的厚度,例如,其可以小于基极区120的厚度。
沟道区123,其可以与源极区121间隔而成。沟道区123的长度,例如,其可以长于源极区121的长度。
沟道区123,例如,其可以具有第1导电型。根据本发明技术思想的几个实施例中,沟道区121可以具有n-型的导电型。
附图中,p+区122、源极区121及沟道区123以矩形形状被图示,但这只是为了便于说明,而不会限制于此。例如,根据工艺,各区域和基极区120相接的界面也可以具有曲率。
阻挡区125可以形成在基极区120内。更具体地,阻挡区125,其在基极区120内,可以形成于外延层110的表面110s。
一同参照图2,阻挡区125可以形成在源极区121和沟道区123之间。根据本发明技术思想的几个实施例中,阻挡区125能够以与源极区121及沟道区123直接相接的方式形成。即,阻挡区125的一区域可以直接相接于源极区121。并且,阻挡区125的其他区域可以直接相接于沟道区123。
阻挡区125可被定义为由源极区121和沟道区123间隔而形成在两个区域之间的区域。例如,阻挡区125,其可以是基极区120的一部分。
阻挡区125可以包括与基极区120实质上相同的物质。阻挡区125可以具有第2导电型。根据本发明技术思想的几个实施例中,阻挡区125可以具有p-型的导电型。阻挡区125的杂质浓度,例如,其实质上可以与基极区120的杂质浓度相同。
根据本发明技术思想的半导体装置,其在沟道区123和源极区121之间包括阻挡区125,从而可以减少穿通(Punch-Through)现象。
换言之,根据本发明技术思想的半导体装置,其可以通过阻挡区125确保半导体装置的运行稳定性。
再来参照图1,栅极沟槽(Gate trench)130T可以形成在外延层110内。栅极沟槽130T的底面及两侧壁可以根据外延层110限定。附图中栅极沟槽130T的两侧壁以相对基板110的第1面100U具有梯度的方式被图示,但本发明不会限制于此。例如,栅极沟槽130T的两侧壁还可以垂直于基板100的第1面100U。
栅极沟槽130T可以与基极区120间隔而成。
栅极130可以包括第1栅极部分130a和第2栅极部分130b。
第1栅极部分130a,其在外延层110上表面的上方,以与源极区121的至少一部分、阻挡区125及沟道区123重叠的方式形成。第2栅极部分130b可以以充满栅极沟槽130T的方式形成。
栅极130可以包括导电型物质。虽然栅极130图示为单层,但本发明不会限制于此。例如,栅极130可以包括:功函数(work function)导电层,其可调节功函数;填充(filling)导电层,其填充由调节功函数的功函数导电层形成的空间。
栅极130,例如,其可以包括氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)、钌(Ru)、碳化钛(TiC)、碳化钽(TaC)、钛(Ti)、银(Ag)、铝(Al)、铝钛(TiAl)、氮化铝钛(TiAlN)、碳化钛铝(TiAlC)、氰化钽(TaCN)、氮化硅钽(TaSiN)、锰(Mn)、锆(Zr)、钨(W)、铝(Al)中的至少一个。或者,栅极130也可以分别由非金属的硅(Si)、硅锗(SiGe)等构成。
栅绝缘膜131可以形成在外延层110和栅极130之间。换言之,栅绝缘膜131可以沿着栅极沟槽130T的两侧壁及底面形成。并且,栅绝缘膜131,其可以在外延层110及基极区120与栅极130之间,以包裹栅极130的形态形成。
栅绝缘膜131的一部分可以在外延层110上表面的上方,以与基极区120的一部分重叠的方式形成。具体地,栅绝缘膜131的一部分可以在外延层110上表面的上方,以与源极区121的一部分、阻挡区125及沟道区123重叠的方式形成。
附图中,栅绝缘膜131以单一膜的方式被图示,但本发明不会限制于此。例如,栅绝缘膜131还可以包括界面膜及高介电率绝缘膜。
栅绝缘膜131可以包括高介电体物质,其具有比硅氧化膜高的介电常数。例如,高介电体物质可以包括氧化铪(hafnium oxide)、铪硅氧化物(hafnium silicon oxide)、氧化镧(lanthanum oxide)、氧化铝镧(lanthanum aluminum oxide)、氧化锆(zirconiumoxide)、锆硅氧化物(zirconium silicon oxide)、氧化钽(tantalum oxide)、氧化钛(titanium oxide)、钡锶钛氧化物(barium strontium titanium oxide)、钡钛氧化物(barium titanium oxide)、锶钛氧化物(strontium titanium oxide)、氧化钇(yttriumoxide)、氧化铝(Aluminum oxide)、铅钪钽氧化物(lead scandium tantalum oxide)或者铌锌酸铅(lead zinc niobate)中一个以上的物质,但不会限制于此。
栅绝缘膜131,其根据包括在外延层110的物质也可以不包括界面膜。在这种情况下,栅绝缘膜131不仅包括上述的高介电体物质,还可以包括氧化硅膜、氮氧化硅膜或者氮化硅膜等。
以第2栅极部分130b为基准,源极区121可以形成得比沟道区123及阻挡区125更远。从第2栅极部分130b到源极区121的间距Ds,其可以大于从第2栅极部分130b到阻挡区125的间距Db及从第2栅极部分130b到沟道区123的间距Dch。
以第2栅极部分130b为基准,阻挡区125可以形成得比沟道区123更远。以第2栅极部分130b为基准,阻挡区125可以形成得比源极区121更近。从第2栅极部分130b到阻挡区125的间距Db,其可以大于从第2栅极部分130b到沟道区123的间距Dch。从第2栅极部分130b到阻挡区125的间距Db,其可以小于从第2栅极部分130b到源极区121的间距Ds。
沟槽底部掺杂区140在外延层110内,可以形成于栅极沟槽130T的底面。例如,沟槽底部掺杂区140可以具有第2导电型。
根据本发明技术思想的几个实施例中,沟槽底部掺杂区140能以与栅绝缘膜131相接的方式形成。
附图中,沟槽底部掺杂区140以具有矩形形态的方式被图示,但是这只是为了便于说明,本发明不会限制于此。例如,根据工艺的不同,沟槽底部掺杂区140的界面可以具有曲率。
根据本发明技术思想的半导体装置,其形成沟槽底部掺杂区140,从而能够减缓栅极沟槽130T的底面部分的电场,而确保半导体装置的坚固性。
附图中,沟槽底部掺杂区140宽度以与栅极沟槽130T底面宽度相同的方式被图示,但本发明不会限制于此。例如,根据工艺的不同,沟槽底部掺杂区140宽度也可以与栅极沟槽130T的底面宽度相异。
源极150可以以盖住栅绝缘膜131的方式形成。源极150也可以以与源极区121的一部分相接的方式形成。
源极150可以包括钨,但本发明不会限制于此。例如,源极150可以包括导电型物质。
漏极160可以形成在基板100的第2面100L,且漏极160可以包括导电型物质。
以下,参照图1、图3至图9,说明关于根据本发明几个实施例的半导体装置的制造方法。为了使本发明清楚,将省略与前面说明的内容重复的事项。
图3至图9为用于说明根据本发明几个实施例的半导体装置制造方法的中间阶段的图。
参照图3,基板100的第1面100U上方可以形成外延层110。
参照图4,外延层110内可以形成源极区121。源极区121可以通过使用掩模图案(mask pattern)M1的掺杂工艺来形成。
具体地,可以将感光膜(photoresist,PR)盖在外延层110上方,并通过光蚀刻工艺形成掩模图案M1。
感光膜可以为单层,但本发明不会限制于此。
即感光膜可以包括在光蚀刻工艺(photolithography process)时用于防止通过下部膜质形成的光反射的抗反射层。抗反射层,例如,其可以包括底部抗反射涂层(BottomAnti-Reflective Coating,BARC)或者可显影的底部抗反射涂层(developable BottomAnti-Reflective Coating,dBARC),但不会限制于此。
形成感光膜后,通过光刻工艺可以形成用于形成掩模图案M1的感光膜图案。此时,感光膜图案可以不形成于将要形成源极区121的区域,但可以形成于不会形成源极区121的区域。
掩模图案M1,其可以通过将感光膜图案作为刻蚀掩模来使用,并去除掩模膜(maskfilm)而被图案化(patterning)。形成掩模图案M1后,可以去除感光膜图案。
通过仅露出将形成源极区121的区域的掩模图案M1进行掺杂工艺时,可以将杂质仅注入到将要形成源极区121的区域。根据本发明技术思想的几个实施例中,注入到源极区121的杂质可以为5价离子。
进行用于形成源极区121的掺杂工艺后,可以去除掩模图案M1。
参照图5,外延层110内可以形成p+区122。P+区122可以通过使用掩模图案M2的掺杂工艺来形成。进行掺杂工艺时注入到p+区122的杂质,例如,其可以为3价离子。掩模图案M2,其可以通过与M1实质上相同的工艺形成。
进行用于形成P+区122的掺杂工艺后,可以去除掩模图案M2。
参照图6,外延层110内可以形成基极区120。基极区120可以通过使用掩模的掺杂工艺来形成。
参照图7,基极区120内可以形成沟道区123及阻挡区125。
沟道区123可以通过使用掩模图案M3的掺杂工艺形成。掩模图案M3,其可以通过与M1及M2实质上相同的工艺形成。
随着以使得沟道区123与源极区121间隔的方式形成掩模图案M3,未注入杂质的源极区121和沟道区123之间的区域,其能够维持与基极区120相同的导电型及杂质浓度。即可以在不进行如掺杂工艺等额外的工艺的情况下,在沟道区123的掺杂工艺过程中形成阻挡区125。阻挡区125的宽度,换言之,源极区121与沟道区123间隔之间的宽度,其可以根据掩模图案来决定。
参照图8,外延层121内可以形成栅极沟槽130T。栅极沟槽130T可以通过光刻及刻蚀工艺来形成。
具体地,可以将感光膜盖在外延层110及基极区120上,并通过光蚀刻工艺形成掩模图案。掩模图案能够以露出将要形成栅极沟槽130T的区域、且不会露出不形成栅极沟槽130T的区域的方式形成。可以将掩模图案作为刻蚀掩模来进行刻蚀工艺而形成栅极沟槽130T。栅极沟槽130T形成后,可以去除掩模图案。
参照图9,可以形成沟槽底部掺杂区140。例如,无需额外的掩模,可通过对栅极沟槽130T的底部进行掺杂工艺来形成沟槽底部掺杂区140。
再次参照图1,进行至图9为止的工艺后,能够形成栅绝缘膜131、栅极130、源极150及漏极160。
以下,参照图10,说明关于根据本发明几个实施例的半导体装置。
图10为包括根据本发明几个实施例的半导体装置的SoC系统的框图。
参照图10,SoC系统1000包括应用处理器1001和动态随机存取存储器(dynamicrandom access memory,DRAM)1060。
应用处理器1001可包括中央处理器1010、多媒体系统1020、总线(BUS)1030、存储系统1040、外围电路1050。
中央处理器1010可以执行SoC系统1000的驱动所需的运算。本发明的几个实施例中,中央处理器1010可以由包括多个内核的多核环境构成。
多媒体系统1020,其可使用于SoC系统中执行各种媒体的功能上。这种多媒体系统1020可以包括3D引擎(3D engine)模块、视频编解码器(video codec)、显示系统(displaysystem)、摄像系统(camera system)、后置处理器(post-processor)等。
总线1030,其可以用于中央处理器1010、多媒体系统1020、存储系统1040及外围电路1050相互进行数据通信。本发明的几个实施例中,这种总线1030可以具有多层结构。具体地,作为这种总线1030例子,其可以使用多层高级高性能总线(multi-layer AdvancedHighperformance Bus,多层AHB)或者多层高级可扩展接口(multi-layer AdvancedeXtensible Interface,多层AXI),但本发明不会限制于此。
存储系统1040,其可以提供应用处理器1001连接于外部存储器(例如,DRAM 1060)而以高速运行所需的环境。本发明的几个实施例中,存储系统1040还可以包括用于控制外部存储器(例如,DRAM 1060)的额外的控制器(例如,DRAM控制器)。
外围电路1050,其可以提供SoC系统1000能够顺利相接于外部装置(例如,主板(mianboard))所需的环境。因此,外围电路1050可以具备各种接口,使得能够对接入至SoC系统1000的外部装置进行互换。
DRAM 1060能够起到使应用处理器1001运行所需的运行存储器的功能。本发明的几个实施例中,如图所示,DRAM 1060可以配置于应用处理器1001的外部。具体地,DRAM1060可以与应用处理器1001封装成堆叠封装(Package on Package,PoP)的形态。
这种SoC系统1000的结构要素中的至少一个,可以通过根据上述说明的本发明实施例的半导体装置的制造方法来制造。
上面参照附图说明了本发明的实施例,但本发明不会限制于上述实施例,而是能够制造成互不相同的各种形态。并且,本发明所属的技术领域的技术人员由此能理解在不对本发明技术思想或者必要技术特征进行变更的情况下能以其他具体形态来实施。因此,以上所述的实施例在所有方面仅仅是示例性的,而非限制性的。
Claims (9)
1.一种半导体装置,其包括:
基板,其包括第1面及相向于所述第1面的第2面;
外延层,其形成在所述基板的第1面的上方,且具有第1导电型;
基极区,其形成在所述外延层内,且具有与所述第1导电型不同的第2导电型;
栅极沟槽,其形成在所述外延层内,与所述基极区间隔而成;
源极区,其形成在所述基极区内,且具有第1导电型;
沟道区,其在所述基极区内,与所述源极区间隔而成,还与栅极沟槽间隔而成,且具有所述第1导电型;及
阻挡区,其形成在所述源极区和所述沟道区之间,且具有所述第2导电型。
2.根据权利要求1所述的半导体装置,其中,
所述阻挡区,其在所述源极区和所述沟道区之间,以与所述源极区及所述沟道区相接的方式形成。
3.根据权利要求1所述的半导体装置,其中,
所述阻挡区,其具有与所述基极区相同的杂质浓度。
4.根据权利要求1所述的半导体装置,
还包括栅极,
其中,所述栅极包括:
第1栅极部分,其在所述外延层的上表面的上方,以与所述阻挡区及所述沟道区重叠的方式形成;和
第2栅极部分,其以充满所述栅极沟槽的方式形成。
5.根据权利要求4的半导体装置,还包括:
沟槽底部掺杂区,其在所述外延层内,形成于所述栅极沟槽的底面,且具有所述第2导电型。
6.根据权利要求4的半导体装置,其中,
从所述第2栅极部分到所述阻挡区的间距,大于从所述第2栅极部分到所述沟道区的间距。
7.根据权利要求4的半导体装置,其中,
从所述第2栅极部分到所述源极区的间距,大于从所述第2栅极部分到所述阻挡区的间距。
8.根据权利要求1的半导体装置,其中,
所述源极区,所述沟道区及所述阻挡区形成在所述外延层的表面。
9.根据权利要求1的半导体装置,还包括:
漏极,其形成在所述基板的第2面的下方。
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