CN107291145A - A kind of current-mode maximum value circuit - Google Patents
A kind of current-mode maximum value circuit Download PDFInfo
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- CN107291145A CN107291145A CN201710677466.9A CN201710677466A CN107291145A CN 107291145 A CN107291145 A CN 107291145A CN 201710677466 A CN201710677466 A CN 201710677466A CN 107291145 A CN107291145 A CN 107291145A
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- Prior art keywords
- current
- nmos tube
- grid
- drain electrode
- input
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Abstract
The invention discloses a kind of current-mode current maxima circuit, including：Arithmetic element, for output current difference, the not output current when the first input current I1 is less than the second input current I2 when the first input current I1 is more than the second input current I2；First constant current source unit, for the second input current I2 to be converted into current sink；Second constant current source unit, connect the arithmetic element and the first constant current source unit, for the first input current I1 and the second input current I2 the greater outwards to be exported in the form of current source Iout, pass through the present invention, realize a kind of simple in construction, small current-mode current maxima circuit of low in energy consumption and chip occupying area.
Description
Technical field
The present invention relates to a kind of circuit, more particularly to a kind of current-mode maximum value circuit.
Background technology
At present, current maxima circuit is widely used in measurement and control field.Fig. 1 is traditional current maxima electricity
The circuit diagram on road.Wherein NMOS tube MN1 and MN2, PMOS MP1, MP2 and MP3 respectively constitute current sink current mirror and electricity
Ource electric current mirror is flowed, NMOS tube MN3, PMOS MP4 and MP5 both function as switch, and resistance R1 function is will to flow through electric current therein
Be converted to voltage.
NMOS tube MN4~MN6, PMOS MP6~MP10 and resistance R2 are constituted with above-mentioned identical circuit to defeated
Enter electric current I2 processing.
NMOS tube MN7 and MN8 constitute current sink current mirror, and PMOS MP11 and MP12 constitute current source current mirror.
Comparator CMP completes to be compared two input voltages and export the function of respective logic value.
Phase inverter INV is negated to the logic voltage that it is inputted.
The principle of the circuit is as follows：
Input current I1 by after two groups of current mirror MN1 and MN2, MP1~MP3 mirror images respectively from PMOS MP2 and MP3
Drain electrode output two-way equal currents, wherein pass through PMOS MP2 drain electrode output the R1 of current flowing resistance all the way after thereon
The electricity that generation pressure drop I1*R1, the control source comparator CMP in-phase input end are produced with input current I2 after same processing
Pressure is compared.The mirror that another road is produced by the electric current of PMOS MP3 drain electrode outputs with input current I2 after same processing
Image current is summed.Work as I1>During I2, comparator CMP two input value I1*R1>I2*R2, comparator CMP export logic
Height, and opened the partial circuit handled I1 by switching tube MN3, MP4 and MP5, so that the electricity for the output that drained from MP3
Flow for I1.And switching tube MN6, MP9 and MP10 can close the partial circuit handled I2, exported so as to be drained from MP8
Electric current be 0.The result summed at MP3 and MP8 drain electrode to two-way electric current is just I1.By two groups of current mirror MN7 and
The ultimate current of drain electrode output after MN8, MP11 and MP12 from MP12 is exactly I1.
Work as I1<During I2, it is therefore apparent that the ultimate current from MP12 drain electrode output is exactly I2.
However, above-mentioned current maxima circuit has as a drawback that：
1. it is complicated.
2. power consumption is big.
3. chip occupying area is big.
The content of the invention
To overcome the shortcomings of that above-mentioned prior art is present, the purpose of the present invention is to provide a kind of current-mode maximum electricity
Road, to reduce the power consumption of circuit, and it is simple in construction, chip occupying area is small.
In view of the above and other objects, the present invention proposes a kind of current-mode current maxima circuit, including：
Arithmetic element, for when the first input current I1 is more than the second input current I2 output current difference, first
Not output current when input current I1 is less than the second input current I2；
First constant current source unit, for the second input current I2 to be converted into current sink；
Second constant current source unit, connects the arithmetic element and the first constant current source unit, for by first input current I1
Outwards exported in the form of current source Iout with the second input current I2 the greater.
Further, the arithmetic element includes the first NMOS tube, the second NMOS tube and the 3rd NMOS tube.
Further, first NMOS tube, the second NMOS tube and the 3rd NMOS tube source ground, first input current
I1 connects second NMOS tube drain electrode, and the grid of second NMOS tube and drain electrode are connected to form diode-connected, and with this first
The grid of NMOS tube is connected to form mirror-image constant flow source, the first input current source I1 of drain electrode connection of the 3rd NMOS tube output with
And grid, the grid of second NMOS tube and the drain electrode of first NMOS tube, its grid connect the second input current I2 and
First constant current source unit, the drain electrode of first NMOS tube connects first constant current source unit and the second constant current source unit.
Further, first constant current source unit includes the 4th NMOS tube and the 5th NMOS tube.
Further, the 4th NMOS tube and the 5th NMOS tube source ground, second input current I2 connect the 4th
NMOS tube drains, and the grid of the 4th NMOS tube and drain electrode are connected to form diode-connected, and with the grid of the 5th NMOS tube
Mirror-image constant flow source is connected to form, meanwhile, the grid of the 4th NMOS tube and drain electrode are connected after being connected with the 3rd NMOS tube grid,
The drain electrode of 5th NMOS tube connects first NMOS tube drain electrode and second constant current source unit.
Further, second constant current source unit includes the first PMOS, the second PMOS.
Further, the grid of first PMOS and drain electrode is connected to form diode-connected, and with second PMOS
Grid be connected to form mirror-image constant flow source, the drain electrode of first NMOS tube, the drain electrode of the 5th NMOS tube are with second PMOS
Grid, the grid of the first PMOS are connected with drain electrode, and the drain electrode of second PMOS exports Iout for current source.
Further, first PMOS, the source electrode of the second PMOS connect power supply.
Further, the breadth length ratio of all PMOSs is equal or roughly equal.
Further, the breadth length ratio of all NMOS tubes is equal or roughly equal.
Compared with prior art, a kind of current-mode current maxima circuit of the invention by the first constant current source unit by second
Input current I2 is converted to current sink, and using arithmetic element, when the first input current I1 is more than the second input current I2, output is electric
Flow difference I1-I2, the not output current when the first input current I1 is less than the second input current I2, utilize the second constant current source unit
For the first input current I1 and the second input current I2 the greater outwards to be exported in the form of current source Iout, realize
A kind of current-Mode Circuits of current maxima, with simple in construction, small power consumption, without current waist and chip occupying area very little
Advantage.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram of current maxima circuit of prior art；
Fig. 2 is a kind of circuit structure diagram of current-mode current maxima circuit of the invention；
Fig. 3 is Simulation results schematic diagram of the invention.
Embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Instantiation implemented or applied, the various details in this specification also can based on different viewpoints with application, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
Fig. 2 is a kind of circuit structure diagram of current-mode current maxima circuit of the invention.As shown in Fig. 2 the present invention is a kind of
Current-mode maximum value circuit includes：Arithmetic element 10, the first constant current source unit 20 and the second constant current source unit 30.
Wherein, arithmetic element 10 is made up of NMOS tube MN1, MN2 and MN3, for being more than second in the first input current I1
Output current difference I1-I2 during input current I2, the not output current when the first input current I1 is less than the second input current I2；
First constant current source unit 20 is made up of NMOS tube MN4, MN5, for the second input current I2 to be converted into current sink；Second constant current
Source unit 30 is made up of PMOS MP1, MP2, for by the first input current I1 and the second input current I2 the greater with electricity
Stream source Iout form is outwards exported.
NMOS tube MN1, MN2, MN3, MN4, MN5 source ground, the source electrode of PMOS MP1, MP2 meet power supply VCC, first
Input current source I1 and the second input current source I2 are the current source generated by power supply VCC, NMOS tube MN2 grid and drain electrode
Diode-connected is connected to form, and mirror-image constant flow source, NMOS tube MN3 drain electrode connection are connected to form with NMOS tube MN1 grid
First input current source I1 output and NMOS tube MN1 grid, NMOS tube MN2 grid and drain electrode, NMOS tube MN4 grid
Pole and drain electrode are connected to form diode-connected, and are connected to form mirror-image constant flow source with NMOS tube MN5 grid, NMOS tube MN3's
Grid connects the second input current source I2 output and NMOS tube MN5 grid, NMOS tube MN4 grid and drain electrode, PMOS
Pipe MP1 grid and drain electrode are connected to form diode-connected, and are connected to form mirror-image constant flow source in PMOS MP2 grid,
NMOS tube MN1 drain electrode connection NMOS tube MN5 drain electrode, PMOS MP2 grid, PMOS MP1 grid are connected with drain electrode,
PMOS MP2 drain electrode is that current source exports Iout.
The principle of the current-mode current maxima circuit of the present invention is as follows：
Make that the breadth length ratio of all PMOSs is equal, all NMOS tubes breadth length ratio is equal, i.e.,
(W/L)MP1=(W/L)MP2=(W/L)MP
(W/L)MN1=(W/L)MN2=(W/L)MN3=(W/L)MN4=(W/L)MN5=(W/L)MN
As I1 >=I2, all MOS field-effect transistors are all operated in saturation region, flow through NMOS tube MN5 electric current I6 with
And flow through NMOS tube MN3 electric current I5 and the second input current source I2 formation mirror, flow through NMOS tube MN2 electric current I4 with
NMOS tube MN1 electric current I3 and the first input current source I1 formation mirror is flowed through, due to the breadth length ratio phase of all PMOSs
Breadth length ratio Deng, all NMOS tubes is equal, so I6=I5=I2, I4=I3=I1-I5, then I4=I3=I1-I5=I1-
I2；Known according to kirchhoff electric current theorem, flow through PMOS MP1 electric current I7 be equal to flow through NMOS tube MN1's and NMOS tube MN5
With, i.e. I7=I6+I3=I2+ (I1-I2)=I1, flow through PMOS MP1 electric current I7 and flow through PMOS MP2 electric current Iout
Form mirror,
So output current Iout is：
Iout=I7=I6+I3=I2+ (I1-I2)=I1；
It can be seen that its value is the maximum in I1 and I2.
Work as I1<During I2, because flowing through NMOS tube MN3 and NMOS tube MN2 electric current sum at most only the first current source I1
Output amplitude, and due to flowing through NMOS tube MN5 electric current I6 when script is operated in saturation region and flow through NMOS tube MN3 electricity
The mirror of I5 and the second input current source I2 formation is flowed, NMOS tube MN3 needs to flow through the output width with the second current source I2
The equal electric current of degree, so the conclusion I5=I2 set up originally at saturation region is now untenable, circuit can force MN3 leakage
Pole tension is greatly reduced, and causes MN3 to be operated in depth linear zone, can only flow through the smaller current that its value is the first current source I1,
And being greatly reduced for MN2 grids (i.e. MN3 drain electrode) voltage makes MN2 and MN1 be in cut-off state, so that I4=I3=0.And can
I6=I2 is remained as to be operated in the electric current flowed through in the MN5 of saturation region.
So output current Iout is：
Iout=I7=I6+I3=I2+0=I2
It can be seen that its value is also the maximum in I1 and I2.
Fig. 3 is Simulation results schematic diagram of the invention.It is the larger sinusoidal current of an amplitude, I2 that I1 is set during emulation
For the less sinusoidal current of an amplitude, after processing of circuit, output Iout is current value the greater in any moment I1 and I2,
Output two input currents I1, I2 maximum.
In summary, a kind of current-mode current maxima circuit of the invention is electric by the second input by the first constant current source unit
Stream I2 be converted to current sink, using arithmetic element the first input current I1 be more than the second input current I2 when output current difference
I1-I2, the not output current when the first input current I1 is less than the second input current I2, being used for using the second constant current source unit will
First input current I1 and the second input current I2 the greater are outwards exported in the form of current source Iout, realize a kind of electricity
The current-Mode Circuits of maximum are flowed, it is excellent without current waist and chip occupying area very little with simple in construction, small power consumption
Point.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.Any
Art personnel can be modified above-described embodiment and changed under the spirit and scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of current-mode current maxima circuit, including：
Arithmetic element, for when the first input current I1 is more than the second input current I2 output current difference, in the first input
Not output current when electric current I1 is less than the second input current I2；
First constant current source unit, for the second input current I2 to be converted into current sink；
Second constant current source unit, connects the arithmetic element and the first constant current source unit, for by the first input current I1 and
Two input current I2 the greater is outwards exported in the form of current source Iout.
2. a kind of current-mode current maxima circuit as claimed in claim 1, it is characterised in that：The arithmetic element includes first
NMOS tube, the second NMOS tube and the 3rd NMOS tube.
3. a kind of current-mode current maxima circuit as claimed in claim 2, it is characterised in that：First NMOS tube, second
NMOS tube and the 3rd NMOS tube source ground, first input current I1 connect second NMOS tube drain electrode, the 2nd NMOS
The grid of pipe and drain electrode are connected to form diode-connected, and are connected to form mirror-image constant flow source with the grid of first NMOS tube, should
The first input current source I1 of drain electrode connection of 3rd NMOS tube output and grid, second NMOS tube of first NMOS tube
Grid and drain electrode, its grid connects the second input current I2 and first constant current source unit, the leakage of first NMOS tube
Pole connects first constant current source unit and the second constant current source unit.
4. a kind of current-mode current maxima circuit as claimed in claim 3, it is characterised in that：The first constant current source unit bag
Include the 4th NMOS tube and the 5th NMOS tube.
5. a kind of current-mode current maxima circuit as claimed in claim 4, it is characterised in that：4th NMOS tube and the 5th
NMOS tube source ground, second input current I2 connects the drain electrode of the 4th NMOS tube, the grid and drain electrode phase of the 4th NMOS tube
Even composition diode-connected, and mirror-image constant flow source is connected to form with the grid of the 5th NMOS tube, meanwhile, the 4th NMOS tube
Grid and drain electrode be connected after be connected with the 3rd NMOS tube grid, the 5th NMOS tube drain connect first NMOS tube drain and
Second constant current source unit.
6. a kind of current-mode current maxima circuit as claimed in claim 5, it is characterised in that：The second constant current source unit bag
Include the first PMOS, the second PMOS.
7. a kind of current-mode current maxima circuit as claimed in claim 6, it is characterised in that：The grid of first PMOS
Diode-connected is connected to form with drain electrode, and mirror-image constant flow source, the first NMOS are connected to form with the grid of second PMOS
The drain electrode of pipe, the drain electrode of the 5th NMOS tube and the grid of second PMOS, the grid of the first PMOS and draining is connected, and this
The drain electrode of two PMOSs is that current source exports Iout.
8. a kind of current-mode current maxima circuit as claimed in claim 7, it is characterised in that：First PMOS, second
The source electrode of PMOS connects power supply.
9. a kind of current-mode current maxima circuit as claimed in claim 8, it is characterised in that：The breadth length ratio of all PMOSs
It is equal or roughly equal.
10. a kind of current-mode current maxima circuit as claimed in claim 8, it is characterised in that：The width of all NMOS tubes is long
Than equal or roughly equal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710677466.9A CN107291145B (en) | 2017-08-09 | 2017-08-09 | A kind of current-mode maximum value circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710677466.9A CN107291145B (en) | 2017-08-09 | 2017-08-09 | A kind of current-mode maximum value circuit |
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| Publication Number | Publication Date |
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| CN107291145A true CN107291145A (en) | 2017-10-24 |
| CN107291145B CN107291145B (en) | 2019-01-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710677466.9A Active CN107291145B (en) | 2017-08-09 | 2017-08-09 | A kind of current-mode maximum value circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN115016580A (en) * | 2022-05-16 | 2022-09-06 | 电子科技大学 | Current divider with wide input range |
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| US6154018A (en) * | 1999-09-01 | 2000-11-28 | Vlsi Technology, Inc. | High differential impedance load device |
| US20040189375A1 (en) * | 2003-03-28 | 2004-09-30 | Lee See Taur | Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA driver with built-in current steering VGA |
| CN103412608A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Band-gap reference circuit |
| CN106200755A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | A kind of current-Mode Circuits of current maxima |
| CN106774584A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
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2017
- 2017-08-09 CN CN201710677466.9A patent/CN107291145B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6154018A (en) * | 1999-09-01 | 2000-11-28 | Vlsi Technology, Inc. | High differential impedance load device |
| US20040189375A1 (en) * | 2003-03-28 | 2004-09-30 | Lee See Taur | Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA driver with built-in current steering VGA |
| CN103412608A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Band-gap reference circuit |
| CN106200755A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | A kind of current-Mode Circuits of current maxima |
| CN106774584A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN111897390B (en) * | 2020-08-13 | 2021-09-24 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN115016580A (en) * | 2022-05-16 | 2022-09-06 | 电子科技大学 | Current divider with wide input range |
| CN115016580B (en) * | 2022-05-16 | 2023-02-28 | 电子科技大学 | Current divider with wide input range |
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| Publication number | Publication date |
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| CN107291145B (en) | 2019-01-18 |
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