CN111897390A - Current selection circuit and method thereof - Google Patents

Abstract

A current selection circuit and method, utilize the first input current of mirror image of the current to obtain the first mirror image current and mirror image the second input current and obtain the second mirror image current, superpose the first mirror image current and second mirror image current to the heavy current and choose the output end together with the second mirror image current after subtracting, then the heavy current chooses the output end to choose the larger input current of current value and output the current proportional to input current chosen from first input current and second input current; and then the first mirror image current and the second mirror image current are superposed and subtracted from the output current of the large current selection output end, and the superposed first mirror image current and second mirror image current are output to the small current selection output end, and the small current selection output end can select the input current with a smaller current value from the first input current and the second input current and output the current proportional to the selected input current. The circuit of the invention has simple structure, and can simultaneously realize the functions of selecting large current and small current only by arranging the current mirror.

Description

Current selection circuit and method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to a current selection circuit and a current selection method.

Background

In integrated circuit designs, it is often desirable to select the magnitude of the two currents, such as selecting the larger of the two currents as the output current, or selecting the smaller of the two currents as the output current. In the conventional scheme, a current comparator is usually used, and the comparison result of the current comparator is used for controlling a selection switch to connect the required current to the output. However, this method has a complicated circuit structure and requires switching, resulting in discontinuity of output current or glitch. The existing current selection circuits generally select large current output, and the selection of small current is rarely involved.

Disclosure of Invention

Aiming at the problems of complex circuit structure, discontinuous current or burr caused by switching of a switch and the defect that the existing current selection scheme rarely relates to small current selection, the invention provides a current selection circuit and a method thereof, which do not need a current comparator and only utilize a simple current mirror circuit to simultaneously select the larger current and the smaller current to output in proportion.

The technical scheme of the invention is as follows:

a current selection circuit comprises a first current mirror, a second current mirror, a third current mirror and a fourth current mirror,

the first current mirror is used for mirroring a first input current I1 to obtain a first mirrored current kxI 1;

the second current mirror is used for mirroring a second input current I2, obtaining a second mirroring current k multiplied by I2 and outputting the second mirroring current k multiplied by I2 to the large-current selection output end;

the mirror image ratio of the first current mirror and the second current mirror is 1: k;

the third current mirror is used for obtaining a difference value between the first mirror image current k × I1 and the second mirror image current k × I2, then mirroring the difference value to the large-current selection output end according to a mirror image ratio of 1:1 to superpose the obtained difference value with the second mirror image current k × I2, wherein the large current output by the large-current selection output end is a current proportional to the input current with the larger current value in the first input current I1 and the second input current I2;

the fourth current mirror is used for obtaining the sum of the first mirror image current k × I1 and the second mirror image current k × I2 and the current subtracted from the large current, and mirroring the sum to a small current selection output end according to a mirror image ratio of 1:1, wherein the small current output by the small current selection output end is a current proportional to the input current with the smaller current value in the first input current I1 and the second input current I2;

when I1> I2, the large current is (k × I1-k × I2) + k × I2 ═ k × I1, and the small current is (k × I1+ k × I2) -k × I1 ═ k × I2;

when I1 ≦ I2, k × I1-k × I2 ═ 0, the large current is (k × I1-k × I2) + k × I2 ═ k × I2, and the small current is (k × I1+ k × I2) -k × I2 ═ k × I1.

Specifically, the first current mirror comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor, a gate drain of the first PMOS transistor is in short circuit and is connected with gates of the second PMOS transistor and the third PMOS transistor and the first input current I1, a source of the first PMOS transistor is connected with sources of the second PMOS transistor and the third PMOS transistor and is connected with a power supply voltage, and drains of the second PMOS transistor and the third PMOS transistor output the first mirror image current k × I1;

the second current mirror comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, the grid drain of the first NMOS transistor is in short circuit connection with the grids of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor and the second input current I2, and the source electrode of the first current mirror is connected with the source electrodes of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor and is grounded; the grid-drain short circuit of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube and is connected with power supply voltage; the drain electrodes of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor and the fifth PMOS transistor output the second mirror current kxI 2;

the third current mirror comprises a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor, the grid drain of the sixth NMOS transistor is in short circuit connection with the grids of the seventh NMOS transistor and the eighth NMOS transistor, the first mirror image current kxI 1 output by the drain electrode of the second PMOS transistor in the first current mirror and the second mirror image current kxI 2 output by the drain electrode of the third NMOS transistor in the second current mirror, and the source electrode of the third current mirror is connected with the source electrodes of the seventh NMOS transistor and the eighth NMOS transistor and grounded; the drains of the seventh NMOS transistor and the eighth NMOS transistor output a difference value between the first mirror current kXI 1 and the second mirror current kXI 2;

the large current selection output end is connected with the difference value of the first mirror image current k × I1 and the second mirror image current k × I2 output by the drain electrode of a seventh NMOS transistor in the third current mirror and the second mirror image current k × I2 output by the drain electrode of a fourth NMOS transistor in the second current mirror;

the fourth current mirror comprises a ninth NMOS transistor and a tenth NMOS transistor, the gate drain of the ninth NMOS transistor is in short circuit connection with the gate of the tenth NMOS transistor, the first mirror image current k × I1 output by the drain of the third PMOS transistor in the first current mirror, the second mirror image current k × I2 output by the drain of the fifth PMOS transistor in the second current mirror, the second mirror image current k × I2 output by the drain of the fifth NMOS transistor in the second current mirror, and the difference value between the first mirror image current k × I1 and the second mirror image current k × I2 output by the drain of the eighth NMOS transistor in the third current mirror, the sources of the ninth NMOS transistor and the tenth NMOS transistor are both grounded, and the drain of the tenth NMOS transistor is used as the small current selection output terminal.

Specifically, the k is 1, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor have the same size, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor have the same size.

A current selection method comprising the steps of:

step one, mirroring a first input current I1 by using a current mirror to obtain a first mirror current k multiplied by I1, wherein k is a mirror ratio;

step two, mirroring a second input current I2 by using a current mirror to obtain a second mirrored current kxI 2;

thirdly, subtracting the first mirror current kxI 1 from the second mirror current kxI 2 to obtain a first large-current selection current kxI 1-kxI 2;

step four, superimposing the first large-current selection current k × I1-k × I2 and the second mirror current k × I2 to a large-current selection output terminal, where the large-current selection output terminal is capable of selecting an input current with a larger current value from the first input current I1 and the second input current I2, and outputting a current proportional to the selected input current: when I1 is greater than I2, the output current of the large-current selection output end is (k × I1-k × I2) + k × I2 ═ k × I1, when I1 is less than or equal to I2, k × I1-k × I2 ═ 0, and the output current of the large-current selection output end is (k × I1-k × I2) + k × I2 ═ k × I2;

step five, superposing the first mirror current k × I1 and the second mirror current k × I2 to obtain a first small current selection current k × I1+ k × I2;

step six, subtracting the output current of the large current selection output end from the first small current selection current k × I1+ k × I2, and outputting the subtracted result to a small current selection output end, where the small current selection output end can select an input current with a smaller current value from the first input current I1 and the second input current I2, and output a current proportional to the selected input current: when I1> I2, the output current of the small-current selection output terminal is (k × I1+ k × I2) -k × I1 ═ k × I2, and when I1 ≦ I2, the output current of the small-current selection output terminal is (k × I1+ k × I2) -k × I2 ═ k × I1.

The invention has the beneficial effects that: the circuit of the invention has simple structure, can realize current selection only by setting the current mirror, can output current proportional to the selected current by setting the mirror ratio of the current mirror, and has more flexible application; the invention realizes the functions of selecting large current and small current at the same time, and solves the problem that the small current selection is rarely involved in the traditional current comparison scheme.

Drawings

Fig. 1 is a circuit diagram of a specific implementation of a current selection circuit according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

The invention provides a current selection method, which can realize the current selection function only by using a simple current mirror structure and can simultaneously select large current and small current. Firstly, a first mirror image is used for mirroring a first input current I1 to obtain a first mirror image current k multiplied by I1; as shown in fig. 1, an implementation structure of the first current mirror is provided, the first current mirror includes a first PMOS transistor MP0, a second PMOS transistor MP1, and a third PMOS transistor MP2, a gate-drain short circuit of the first PMOS transistor MP0 is connected to gates of the second PMOS transistor MP1 and the third PMOS transistor MP2 and a first input current I1, a source of the first input current I1 is connected to sources of the second PMOS transistor MP1 and the third PMOS transistor MP2 and is connected to a power supply voltage, and drains of the second PMOS transistor MP1 and the third PMOS transistor MP2 output a first mirror current k × I1.

Secondly, a second current mirror is used for mirroring a second input current I2 to obtain a second mirror current k × I2, and as shown in fig. 1, an implementation structure of the second current mirror is provided, wherein the second current mirror comprises a first NMOS tube MN7, a second NMOS tube MN6, a third NMOS tube MN5, a fourth NMOS tube MN4, a fifth NMOS tube MN3, a fourth PMOS tube MP4 and a fifth PMOS tube MP3, a gate-drain short circuit of the first NMOS tube MN7 is connected with gate electrodes of the second NMOS tube MN6, the third NMOS tube MN5, the fourth NMOS tube MN4 and the fifth NMOS tube MN3 and a second input current I2, and a source electrode of the first current mirror is connected with source electrodes of the second NMOS tube MN6, the third NMOS tube MN5, the fourth NMOS tube 4 and the fifth NMOS tube MN3 and grounded; the gate-drain short circuit of the fourth PMOS transistor MP4 connects the gate of the fifth PMOS transistor MP3 and the drain of the second NMOS transistor MN6, and the source thereof is connected to the source of the fifth PMOS transistor MP3 and to the supply voltage; drains of the second NMOS transistor MN6, the third NMOS transistor MN5, the fourth NMOS transistor MN4, the fifth NMOS transistor MN3, and the fifth PMOS transistor MP3 all output a second mirror current k × I2.

Then, a third current mirror is used for obtaining a difference value of the first mirror image current k × I1 and the second mirror image current k × I2 and then mirroring according to a mirror image ratio of 1:1, an implementation structure of the third current mirror is provided as shown in fig. 1, the third current mirror comprises a sixth NMOS tube MN0, a seventh NMOS tube MN1 and an eighth NMOS tube MN2, a gate-drain short circuit of the sixth NMOS tube MN0 is connected with gates of the seventh NMOS tube MN1 and the eighth NMOS tube MN2, a first mirror image current k × I1 output by a drain of a second PMOS tube MP1 in the first current mirror and a second mirror image current k × I2 output by a drain of a third NMOS tube MN5 in the second current mirror are connected, and a source of the third NMOS tube MN1 and an eighth NMOS tube MN2 is connected and grounded; the drains of the seventh NMOS transistor MN1 and the eighth NMOS transistor MN2 both output a difference between the first mirror current k × I1 and the second mirror current k × I2.

The branch current of the drain of the second PMOS transistor MP1 in the first current mirror is the first mirror current k × I1, the branch current respectively flows through the branch of the drain of the sixth NMOS transistor MN0 in the third current mirror and the branch of the drain of the third NMOS transistor MN5 in the second current mirror, and the branch current of the drain of the third NMOS transistor MN5 in the second current mirror is the second mirror current k × I2, so the branch current of the drain of the sixth NMOS transistor MN0 in the third current mirror is the difference between the first mirror current k × I1 and the second mirror current k × I2, that is, the first large current selection current k × I1-k × I2. The third current mirror mirrors the first large-current selection current k multiplied by I1-k multiplied by I2 to the branch where the drain of the seventh NMOS transistor MN1 is located and the branch where the drain of the eighth NMOS transistor MN2 is located according to the mirror ratio of 1: 1.

The large-current selection output end is connected with the drain of a seventh NMOS tube MN1 in the third current mirror and the drain of a fourth NMOS tube MN4 in the second current mirror, so that the current k × I1-k × I2 of a branch where the drain of the seventh NMOS tube MN1 in the third current mirror is located and the current k × I2 of a branch where the drain of the fourth NMOS tube MN4 in the second current mirror is located are superposed at the large-current selection output end, and the large current Iout _ max output by the large-current selection output end is (k × I1-k × I2) + k × I2, when I1> I2, (k × I1-k × I2) + k × I2 is k × I1, and when I9 ≦ I2, since k × I1-k × I2 is 0, therefore (k × I1-k × I2) + k × I2+ k × I2 is I × 2.

In order to realize the selection of the small current, the invention utilizes a fourth current mirror to obtain the sum of the first mirror current k × I1 and the second mirror current k × I2, and then the sum is subtracted from the large current Iout _ max, and the sum is mirrored to the small current selection output end according to the mirror image ratio of 1:1, as shown in fig. 1, an implementation structure of the fourth current mirror is provided, the fourth current mirror comprises a ninth NMOS transistor MN8 and a tenth NMOS transistor MN9, the gate-drain of the ninth NMOS transistor MN8 is in short circuit and is connected with the gate of the tenth NMOS transistor MN9, the drain of the third PMOS transistor MP2 in the first current mirror, the drain of the fifth PMOS transistor MP3 in the second current mirror, the drain of the fifth NMOS transistor MN3 in the second current mirror and the drain of the eighth NMOS transistor MN2 in the third current mirror, the sources of the ninth NMOS transistor MN8 and the tenth NMOS transistor MN9 are all grounded, and the drain of the tenth NMOS transistor MN9 is used as the small current selection output end.

The branch current of the drain of the third PMOS transistor MP2 in the first current mirror is the first mirror current k × I1, the branch current of the drain of the fifth PMOS transistor MP3 in the second current mirror is the second mirror current k × I2, the superposed current k × I1+ k × I2 of the two branch currents respectively flows into a branch where the drain of the ninth NMOS transistor MN8 in the fourth current mirror is located, a branch where the drain of the eighth NMOS transistor MN2 in the third current mirror is located, and a branch where the drain of the fifth NMOS transistor MN3 in the second current mirror is located, the branch current of the drain of the eighth NMOS transistor MN2 in the third current mirror and the branch current of the drain of the fifth NMOS transistor MN3 in the second current mirror are superposed to form a large current Iout _ max, therefore, the branch current of the drain of the ninth NMOS transistor MN8 in the fourth current mirror is (k × I1+ k × I2) -Iout _ max, when I1> I2, the large current Iout _ max is k × I1, and therefore the small current Iout _ min is (k × I1+ k × I2) -k × I1 is k × I2; when I1 ≦ I2, the large current Iout _ max is k × I2, and therefore the small current Iout _ min is (k × I1+ k × I2) -k × I2 is k × I1.

In addition to selecting a larger current and a smaller current from the first input current I1 and the second input current I2, the present invention can output the selected currents in a desired ratio by setting a mirror ratio 1: k of the first current mirror and the second current mirror, where k is 1 as an example.

The sizes of the first PMOS tube MP0, the second PMOS tube MP1, the third PMOS tube MP2, the fourth PMOS tube MP4 and the fifth PMOS tube MP3 are the same, and the sizes of the first NMOS tube MN7, the second NMOS tube MN6, the third NMOS tube MN5, the fourth NMOS tube MN4, the fifth NMOS tube MN3, the sixth NMOS tube MN0, the seventh NMOS tube MN1, the eighth NMOS tube MN2, the ninth NMOS tube MN8 and the tenth NMOS tube MN9 are the same. Then the first input current I1 passes through the mirror image of the first current mirror, the currents flowing through the first PMOS transistor MP0, the second PMOS transistor MP1 and the third PMOS transistor MP2 are all I1, the second input current I2 passes through the mirror image of the second current mirror, the currents flowing through the fourth PMOS transistor MP4, the fifth PMOS transistor MP3, the first NMOS transistor MN7, the second NMOS transistor MN6, the third NMOS transistor MN5, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN3 are all I2, the currents flowing through the second PMOS transistor MP1 respectively flow into the sixth NMOS transistor MN0 and the third NMOS transistor MN5, so that the current flowing through the sixth NMOS transistor MN0 is I1-I2, and the currents flowing through the sixth NMOS transistor MN0, the seventh NMOS transistor MN1 and the eighth NMOS transistor MN2 are all I1-I3687472.

When I1> I2, the larger one of I1 and I2, Iout _ max ═ max { I1, I2} is the sum of currents flowing through the seventh NMOS transistor MN1 and the fourth NMOS transistor MN4, so Iout _ max ═ max { I1, I2} -, I1-I2+ I2 ═ I1. When I1 ≦ I2, I1-I2 ≦ 0, so the current of the seventh NMOS transistor MN1 is 0, and Iout _ max ═ max { I1, I2} -, 0+ I2 ═ I2.

The current flowing through the ninth NMOS transistor MN8 is the sum of the currents of the third PMOS transistor MP2 and the fifth PMOS transistor MP3 (I1+ I2) minus the current of the eighth NMOS transistor MN2 and the current of the fifth NMOS transistor MN3(Iout _ max), and then the current flowing through the tenth NMOS transistor MN9 and the current flowing through the ninth NMOS transistor MN8 are equal through the fourth current mirror image, so that the smaller one of I1 and I2, I _ min { I1, I2}, I1+ I2-Iout _ max, when I1> I2, I _ min ═ I1+ I2-I1 ═ I2, and when I1 ≦ I2, I _ min ═ I1+ I2-I2 ═ I1.

The embodiment is described by taking k as 1 as an example, but the value of k and the specific structures of the first to fourth current mirrors should not be used to limit the protection scope of the present invention, and other ways of implementing current mirroring by setting the transistor size to change the value of k or using other current mirror structures should fall within the protection scope of the present invention, and those skilled in the art can make various other specific modifications and combinations according to the technical teaching disclosed by the present invention without departing from the spirit of the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (4)

1. A current selection circuit is characterized by comprising a first current mirror, a second current mirror, a third current mirror and a fourth current mirror,

the first current mirror is used for mirroring a first input current I1 to obtain a first mirrored current kxI 1;

the second current mirror is used for mirroring a second input current I2, obtaining a second mirroring current k multiplied by I2 and outputting the second mirroring current k multiplied by I2 to the large-current selection output end;

the mirror image ratio of the first current mirror and the second current mirror is 1: k;

the third current mirror is used for obtaining a difference value between the first mirror image current k × I1 and the second mirror image current k × I2, then mirroring the difference value to the large-current selection output end according to a mirror image ratio of 1:1 to superpose the obtained difference value with the second mirror image current k × I2, wherein the large current output by the large-current selection output end is a current proportional to the input current with the larger current value in the first input current I1 and the second input current I2;

the fourth current mirror is used for obtaining the sum of the first mirror image current k × I1 and the second mirror image current k × I2 and the current subtracted from the large current, and mirroring the sum to a small current selection output end according to a mirror image ratio of 1:1, wherein the small current output by the small current selection output end is a current proportional to the input current with the smaller current value in the first input current I1 and the second input current I2;

when I1> I2, the large current is (k × I1-k × I2) + k × I2 ═ k × I1, and the small current is (k × I1+ k × I2) -k × I1 ═ k × I2;

when I1 ≦ I2, k × I1-k × I2 ═ 0, the large current is (k × I1-k × I2) + k × I2 ═ k × I2, and the small current is (k × I1+ k × I2) -k × I2 ═ k × I1.

2. The current selection circuit of claim 1, wherein the first current mirror comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor, a gate-drain short circuit of the first PMOS transistor is connected with gates of the second PMOS transistor and the third PMOS transistor and the first input current I1, sources of the first PMOS transistor and the third PMOS transistor are connected with sources of the second PMOS transistor and the third PMOS transistor and a power voltage, and drains of the second PMOS transistor and the third PMOS transistor output the first mirror current kxI 1;

the second current mirror comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, the grid drain of the first NMOS transistor is in short circuit connection with the grids of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor and the second input current I2, and the source electrode of the first current mirror is connected with the source electrodes of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor and is grounded; the grid-drain short circuit of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube and the drain electrode of the second NMOS tube, and the source electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube and is connected with power supply voltage; the drain electrodes of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor and the fifth PMOS transistor output the second mirror current kxI 2;

the third current mirror comprises a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor, the grid drain of the sixth NMOS transistor is in short circuit connection with the grids of the seventh NMOS transistor and the eighth NMOS transistor, the first mirror image current kxI 1 output by the drain electrode of the second PMOS transistor in the first current mirror and the second mirror image current kxI 2 output by the drain electrode of the third NMOS transistor in the second current mirror, and the source electrode of the third current mirror is connected with the source electrodes of the seventh NMOS transistor and the eighth NMOS transistor and grounded; the drains of the seventh NMOS transistor and the eighth NMOS transistor output a difference value between the first mirror current kXI 1 and the second mirror current kXI 2;

the large current selection output end is connected with the difference value of the first mirror image current k × I1 and the second mirror image current k × I2 output by the drain electrode of a seventh NMOS transistor in the third current mirror and the second mirror image current k × I2 output by the drain electrode of a fourth NMOS transistor in the second current mirror;

the fourth current mirror comprises a ninth NMOS transistor and a tenth NMOS transistor, the gate drain of the ninth NMOS transistor is in short circuit connection with the gate of the tenth NMOS transistor, the first mirror image current k × I1 output by the drain of the third PMOS transistor in the first current mirror, the second mirror image current k × I2 output by the drain of the fifth PMOS transistor in the second current mirror, the second mirror image current k × I2 output by the drain of the fifth NMOS transistor in the second current mirror, and the difference value between the first mirror image current k × I1 and the second mirror image current k × I2 output by the drain of the eighth NMOS transistor in the third current mirror, the sources of the ninth NMOS transistor and the tenth NMOS transistor are both grounded, and the drain of the tenth NMOS transistor is used as the small current selection output terminal.

3. The current selection circuit according to claim 2, wherein k is 1, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor have the same size, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor have the same size.

4. A method of current selection, comprising the steps of:

step one, mirroring a first input current I1 by using a current mirror to obtain a first mirror current k multiplied by I1, wherein k is a mirror ratio;

step two, mirroring a second input current I2 by using a current mirror to obtain a second mirrored current kxI 2;

thirdly, subtracting the first mirror current kxI 1 from the second mirror current kxI 2 to obtain a first large-current selection current kxI 1-kxI 2;

step four, superimposing the first large-current selection current k × I1-k × I2 and the second mirror current k × I2 to a large-current selection output terminal, where the large-current selection output terminal is capable of selecting an input current with a larger current value from the first input current I1 and the second input current I2, and outputting a current proportional to the selected input current: when I1 is greater than I2, the output current of the large-current selection output end is (k × I1-k × I2) + k × I2 ═ k × I1, when I1 is less than or equal to I2, k × I1-k × I2 ═ 0, and the output current of the large-current selection output end is (k × I1-k × I2) + k × I2 ═ k × I2;

step five, superposing the first mirror current k × I1 and the second mirror current k × I2 to obtain a first small current selection current k × I1+ k × I2;

step six, subtracting the output current of the large current selection output end from the first small current selection current k × I1+ k × I2, and outputting the subtracted result to a small current selection output end, where the small current selection output end can select an input current with a smaller current value from the first input current I1 and the second input current I2, and output a current proportional to the selected input current: when I1> I2, the output current of the small-current selection output terminal is (k × I1+ k × I2) -k × I1 ═ k × I2, and when I1 ≦ I2, the output current of the small-current selection output terminal is (k × I1+ k × I2) -k × I2 ═ k × I1.

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