CN103412597A - Current reference circuit - Google Patents
Current reference circuit Download PDFInfo
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- CN103412597A CN103412597A CN2013103013884A CN201310301388A CN103412597A CN 103412597 A CN103412597 A CN 103412597A CN 2013103013884 A CN2013103013884 A CN 2013103013884A CN 201310301388 A CN201310301388 A CN 201310301388A CN 103412597 A CN103412597 A CN 103412597A
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Abstract
The invention relates to the technique of integrated circuits, in particular to a current reference circuit. The current reference circuit is characterized by comprising a first current reference unit, a second current reference unit and a maximum current selecting circuit, wherein the output end of the first current reference unit is connected with the first input end of the maximum current selecting circuit, the output end of the second current reference unit is connected with the second input end of the maximum current selecting circuit, and the output end of the maximum current selecting circuit is the output end of the current reference circuit. The current reference circuit has the advantages that by adopting a cascode current mirror, currents are copied more accurately, collector electrode voltage of an audion Q1 and collector electrode voltage of an audion Q2 are accurate and equal, the PSRR is improved, the current in the first current reference unit and the current in the second current reference unit are selected by adopting the maximum current selecting circuit, and therefore the temperature coefficient of the output currents is better. The current reference circuit is particularly suitable for current reference circuits.
Description
Technical field
The present invention relates to integrated circuit technique, relate to specifically a kind of current reference circuit.
Background technology
In integrated circuit, reference source is applied very extensively, comprising voltage-reference and current reference source.Along with the development of integrated circuit technique, more and more higher to the performance requirement of chip, need current reference circuit to provide the precision of electric current also more and more higher.
Can provide at present the circuit of precision current reference source to be divided into two kinds: the first is at a kind of high-precision voltage reference circuit of chip internal design, produce a reference voltage with temperature, technique, independent of power voltage, then by more additional circuit, convert reference voltage to reference current; The second is that compensation is done in the directly electric current by producing a kind of negative temperature coefficient and the direct addition of electric current of positive temperature coefficient (PTC), thereby obtains a kind of temperature independent current reference source.
Existing a kind of current reference circuit as shown in Figure 1, comprises PMOS current mirror M1, M2 and M5, NMOS current mirror M3, M4, triode Qa, Qb, resistance R a, Rb and Rc.The principle that this circuit produces reference current is as follows: utilize current mirror M1, M2 and current mirror M3, M4 that the collector voltage of triode Qa, Qb is equated, the voltage that is 2 of A, B equates, Qa, Qb and Ra have formed loop, and the pressure drop above Ra is base stage and the emitter voltage V of triode Qa, Qb
Be1, V
Be2Difference △ V
Be, I
Ra=△ V
Be/ Ra, △ V
BeThe voltage of a positive temperature coefficient (PTC), therefore I
RaFor the electric current of positive temperature coefficient (PTC), the electric current above resistance R b is I
Rb=V
Be2/ Rb, V
Be2For the voltage of negative temperature coefficient, therefore I
RbFor the electric current of negative temperature coefficient, I
RaAnd I
RbThe electric current sum is I
M2, the ratio of the size by adjusting resistance Ra, Rb, Ra and triode Qa, Qb emitter area, can make I
M2Size variation with temperature and changing not.M2 and M5 form current mirror, and the electric current above M5 current mirror M2, have Iref=I
M2So, obtained temperature-independent reference current Iref.Fig. 2 is the output waveform of this circuit, and the waveform that can see Iref is one section curve, due to the temperature coefficient of the electric current of the electric current of positive temperature coefficient (PTC) and negative temperature coefficient also along with temperature variation changes, so can not accurately offset.
The shortcoming of this circuit is: 1, mirror currents mismatch problems: due to the channel modulation effect, PMOS current mirror M1, M2, the drain-source voltage of NMOS current mirror M3, M4 also not exclusively equates, the collector voltage that causes triode Qa, Qb is deviation to some extent, and then to cause the output current benchmark be not very accurate.2, owing to having adopted basic two-tube current mirror, the PSRR(Power Supply Rejection Ratio of this current reference circuit) not fine.3, because this circuit is fairly simple, do not use high-order compensation, so the temperature coefficient of output current benchmark is not very high.
Summary of the invention
Technical matters to be solved by this invention, be exactly the problems referred to above for the conventional current reference circuit, proposes a kind of current reference circuit.
The present invention solves the problems of the technologies described above the technical scheme adopted: a kind of current reference circuit, it is characterized in that, comprise the first current reference unit, the second current reference unit and maximum current selecting circuit, the output terminal of described the first current reference unit is connected with described maximum current selecting circuit first input end, the output terminal of described the second current reference unit is connected with described maximum current selecting circuit the second input end, and the output terminal of described maximum current selecting circuit is the output terminal of current reference circuit; Wherein,
Described the first current reference unit, the second current reference unit are for producing respectively an independently reference current output, the reference current that the first current reference unit produces has preferably temperature characterisitic in the time of low temperature and current value is greater than the second current reference unit produces in the time of low temperature reference current, and the reference current that the second current reference unit produces has preferably temperature characterisitic in the time of high temperature and current value is greater than the first current reference unit produces in the time of high temperature reference current;
Described maximum current selecting circuit is for the output as current reference circuit of the electric current Da De mono-road electric current selecting the first current reference unit and the second current reference unit and produce, makes output current have simultaneously low-temperature zone and high temperature section temperature coefficient preferably.
Concrete, described the first current reference unit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5, the 6th NMOS pipe N6, the first triode Q1, the second triode Q2, the first resistance R 1, the second resistance R 2 and the 3rd resistance R 3
Described maximum current selecting circuit comprises the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15 and the 16 NMOS pipe N16
Described the second current reference unit comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 21 NMOS pipe N21, the 22 NMOS pipe N22 the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 3rd triode Q3 and the 4th triode Q4, wherein,
The grid of the one PMOS pipe P1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a NMOS pipe N1 with drain electrode, the drain and gate of the grid of the one NMOS pipe N1 and the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the source electrode of the 6th PMOS pipe P6 is connected with the grid of the 8th PMOS pipe P8, the grid of the 2nd PMOS pipe P2 is connected with the grid of the 3rd PMOS pipe P3 with the drain electrode of the 2nd NMOS pipe N2 with drain electrode, the source electrode of the 3rd PMOS pipe P3 drain electrode and the 4th NMOS pipe N4, the grid of the 5th NMOS pipe N5, the grid of the 6th NMOS pipe N6 is connected with drain electrode, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 7th PMOS pipe P7 with the grid of the 3rd NMOS pipe N3 with drain electrode, the drain and gate of the drain electrode of the 3rd NMOS pipe N3 and the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7 is connected with the grid of the 9th PMOS pipe P9, the drain electrode of the 5th NMOS pipe N5 is connected with the source electrode of the 3rd NMOS pipe N3, the collector of source electrode and the first triode Q1 and base stage, one end of the first resistance R 1 connects, the emitter of the first triode Q1 is connected with an end of the second resistance R 2, the source electrode of the 6th NMOS pipe N6 and collector and the base stage of the second triode Q2, one end of the 3rd resistance R 3 connects, the source ground of the source electrode of the one NMOS pipe N1 and the 2nd NMOS pipe N2,
The drain electrode of the 8th PMOS pipe P8 is connected with the source electrode of the 9th PMOS pipe P9, the drain and gate of the drain electrode of the 9th PMOS pipe P9 and the 7th NMOS pipe N7, the grid of the 9th NMOS pipe N9, the drain electrode of the 13 NMOS pipe N13 connects, grid and the drain electrode of the source electrode of the 7th NMOS pipe N7 and the 8th NMOS pipe N8, the grid of the tenth NMOS pipe N10 connects, the source electrode of the 9th NMOS pipe N9 is connected with the drain electrode of the tenth NMOS pipe N10, the grid of the 11 NMOS pipe N11, the grid of the 13 NMOS pipe N13, grid and the drain electrode of the 15 NMOS pipe N15, the drain electrode of the 11 PMOS pipe P11 connects, the 11 NMOS pipe N11 source electrode with the drain electrode of the 12 NMOS pipe N12, be connected, the grid of the 12 NMOS pipe N12, the grid of the 14 NMOS pipe N14, grid and the drain electrode of the 16 NMOS pipe N16, the source electrode of the 15 NMOS pipe N15 connects, the tenth PMOS pipe P10 is connected with the source electrode of drain electrode the 11 PMOS pipe P11,
The drain electrode of the 9th NMOS pipe N9 is connected the output terminal as current reference circuit with the drain electrode of the 11 NMOS pipe N11;
The grid of the grid of the tenth PMOS pipe P10 and the 12 PMOS pipe P12, grid and the drain electrode of the 13 PMOS pipe P13, the source electrode of the 15 PMOS pipe P15, the grid of the 22 NMOS pipe N22 connects, the grid of the grid of the 11 PMOS pipe P11 and the 14 PMOS pipe P14, grid and the drain electrode of the 15 PMOS pipe P15, the drain electrode of the 18 NMOS pipe N18 connects, the drain electrode of the 12 PMOS pipe P12 is connected with the source electrode of the 14 PMOS pipe P14, the drain and gate of the drain electrode of the 14 PMOS pipe P14 and the 17 NMOS pipe N17, the grid of the 18 NMOS pipe N18 connects, the drain and gate of the source electrode of the 17 NMOS pipe N17 and the 19 NMOS pipe N19, the drain electrode of the 20 NMOS pipe N20, the drain electrode of the 16 PMOS pipe P16 connects, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 20 NMOS pipe N20, the source electrode of the 19 NMOS pipe N19 and collector and the base stage of the 3rd triode Q3, one end of the 4th resistance R 4 connects, the source electrode of the 20 NMOS pipe N20 and collector and the base stage of the 4th triode Q4, one end of the 6th resistance R 6 connects, the emitter of the 4th triode Q4 is connected with an end of the 5th resistance R 5, grid and the drain electrode of the grid of the 16 PMOS pipe P16 and the 17 PMOS pipe P17, the drain electrode of the 21 NMOS pipe N21 connects, grid and the drain electrode of the grid of the 21 NMOS pipe N21 and the 18 PMOS pipe P18, the drain electrode of the 22 NMOS pipe N22 connects, the source ground of the source electrode of the 21 NMOS pipe N21 and the 22 NMOS pipe N22,
The source ground of the source electrode of the source electrode of the source electrode of the source electrode of the emitter of the emitter of the other end of the other end of the other end of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the second triode Q2, the 3rd triode Q3, the 8th NMOS pipe N8, the tenth NMOS pipe N10, the 12 NMOS pipe N12, the 14 NMOS pipe N14 and the 16 NMOS pipe N16;
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 16 PMOS pipe P16, the 17 PMOS pipe P17 is connected power supply with the source electrode of the 18 PMOS pipe P18.
Beneficial effect of the present invention is, by adopting common-source common-gate current mirror, make copying of electric current more accurate, the collector voltage of triode Q1, Q2 is accurately equated, and improved PSRR, and, by adopting maximum current selecting circuit to realize the electric current in the first current reference unit, the second current reference unit is selected, make the temperature coefficient of output current better.
The accompanying drawing explanation
Fig. 1 is existing current reference circuit schematic diagram;
Fig. 2 is the output current wave schematic diagram of existing current reference circuit;
Fig. 3 is the logical schematic of current reference circuit of the present invention;
Fig. 4 is the circuit theory schematic diagram of current reference circuit of the present invention;
Fig. 5 is the reference current waveshape schematic diagram of two reference power supplies output of the present invention;
Fig. 6 is the reference current waveshape schematic diagram of current reference circuit output of the present invention.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
As shown in Figure 3, a kind of current reference circuit that the present invention proposes, comprise the first current reference unit, the second current reference unit and maximum current selecting circuit, the output terminal of described the first current reference unit is connected with described maximum current selecting circuit first input end, the output terminal of described the second current reference unit is connected with described maximum current selecting circuit the second input end, and the output terminal of described maximum current selecting circuit is the output terminal of current reference circuit; Wherein,
Described the first current reference unit, the second current reference unit are for producing respectively an independently reference current output, the reference current that the first current reference unit produces has preferably temperature characterisitic in the time of low temperature and current value is greater than the second current reference unit produces in the time of low temperature reference current, and the reference current that the second current reference unit produces has preferably temperature characterisitic in the time of high temperature and current value is greater than the first current reference unit produces in the time of high temperature reference current;
Described maximum current selecting circuit as output, makes output have simultaneously low-temperature zone and high temperature section temperature coefficient preferably for the electric current Da De mono-road electric current selecting the first current reference unit and the second current reference unit and produce.
As shown in Figure 4, described the first current reference unit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, the one NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5, the 6th NMOS pipe N6, the first triode Q1, the second triode Q2, the first resistance R 1, the second resistance R 2 and the 3rd resistance R 3, described maximum current selecting circuit comprise the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15 and the 16 NMOS pipe N16, described the second current reference unit comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 21 NMOS pipe N21, the 22 NMOS pipe N22 the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 3rd triode Q3 and the 4th triode Q4, wherein,
The grid of the one PMOS pipe P1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a NMOS pipe N1 with drain electrode, the drain and gate of the grid of the one NMOS pipe N1 and the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the source electrode of the 6th PMOS pipe P6 is connected with the grid of the 8th PMOS pipe P8, the grid of the 2nd PMOS pipe P2 is connected with the grid of the 3rd PMOS pipe P3 with the drain electrode of the 2nd NMOS pipe N2 with drain electrode, the source electrode of the 3rd PMOS pipe P3 drain electrode and the 4th NMOS pipe N4, the grid of the 5th NMOS pipe N5, the grid of the 6th NMOS pipe N6 is connected with drain electrode, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 7th PMOS pipe P7 with the grid of the 3rd NMOS pipe N3 with drain electrode, the drain and gate of the drain electrode of the 3rd NMOS pipe N3 and the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7 is connected with the grid of the 9th PMOS pipe P9, the drain electrode of the 5th NMOS pipe N5 is connected with the source electrode of the 3rd NMOS pipe N3, the collector of source electrode and the first triode Q1 and base stage, one end of the first resistance R 1 connects, the emitter of the first triode Q1 is connected with an end of the second resistance R 2, the source electrode of the 6th NMOS pipe N6 and collector and the base stage of the second triode Q2, one end of the 3rd resistance R 3 connects, the source ground of the source electrode of the one NMOS pipe N1 and the 2nd NMOS pipe N2,
The drain electrode of the 8th PMOS pipe P8 is connected with the source electrode of the 9th PMOS pipe P9, the drain and gate of the drain electrode of the 9th PMOS pipe P9 and the 7th NMOS pipe N7, the grid of the 9th NMOS pipe N9, the drain electrode of the 13 NMOS pipe N13 connects, grid and the drain electrode of the source electrode of the 7th NMOS pipe N7 and the 8th NMOS pipe N8, the grid of the tenth NMOS pipe N10 connects, the source electrode of the 9th NMOS pipe N9 is connected with the drain electrode of the tenth NMOS pipe N10, the grid of the 11 NMOS pipe N11, the grid of the 13 NMOS pipe N13, grid and the drain electrode of the 15 NMOS pipe N15, the drain electrode of the 11 PMOS pipe P11 connects, the 11 NMOS pipe N11 source electrode with the drain electrode of the 12 NMOS pipe N12, be connected, the grid of the 12 NMOS pipe N12, the grid of the 14 NMOS pipe N14, grid and the drain electrode of the 16 NMOS pipe N16, the source electrode of the 15 NMOS pipe N15 connects, the tenth PMOS pipe P10 is connected with the source electrode of drain electrode the 11 PMOS pipe P11,
The drain electrode of the 9th NMOS pipe N9 is connected the output terminal as current reference circuit with the drain electrode of the 11 NMOS pipe N11;
The grid of the grid of the tenth PMOS pipe P10 and the 12 PMOS pipe P12, grid and the drain electrode of the 13 PMOS pipe P13, the source electrode of the 15 PMOS pipe P15, the grid of the 22 NMOS pipe N22 connects, the grid of the grid of the 11 PMOS pipe P11 and the 14 PMOS pipe P14, grid and the drain electrode of the 15 PMOS pipe P15, the drain electrode of the 18 NMOS pipe N18 connects, the drain electrode of the 12 PMOS pipe P12 is connected with the source electrode of the 14 PMOS pipe P14, the drain and gate of the drain electrode of the 14 PMOS pipe P14 and the 17 NMOS pipe N17, the grid of the 18 NMOS pipe N18 connects, the drain and gate of the source electrode of the 17 NMOS pipe N17 and the 19 NMOS pipe N19, the drain electrode of the 20 NMOS pipe N20, the drain electrode of the 16 PMOS pipe P16 connects, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 20 NMOS pipe N20, the source electrode of the 19 NMOS pipe N19 and collector and the base stage of the 3rd triode Q3, one end of the 4th resistance R 4 connects, the source electrode of the 20 NMOS pipe N20 and collector and the base stage of the 4th triode Q4, one end of the 6th resistance R 6 connects, the emitter of the 4th triode Q4 is connected with an end of the 5th resistance R 5, grid and the drain electrode of the grid of the 16 PMOS pipe P16 and the 17 PMOS pipe P17, the drain electrode of the 21 NMOS pipe N21 connects, grid and the drain electrode of the grid of the 21 NMOS pipe N21 and the 18 PMOS pipe P18, the drain electrode of the 22 NMOS pipe N22 connects, the source ground of the source electrode of the 21 NMOS pipe N21 and the 22 NMOS pipe N22,
The source electrode of the source electrode of the source electrode of the source electrode of the emitter of the emitter of the other end of the other end of the other end of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the second triode Q2, the 3rd triode Q3, the 8th NMOS pipe N8, the tenth NMOS pipe N10, the 12 NMOS pipe N12, the 14 NMOS pipe N14 is connected with the source electrode of the 16 NMOS pipe N16;
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 16 PMOS pipe P16, the 17 PMOS pipe P17 is connected with the source electrode of the 18 PMOS pipe P18.
Principle of work of the present invention is:
In the first current reference unit, the effect of start-up circuit is when preventing that circuit from powering on, circuit enters idle degeneracy state, its principle of work is as follows: when circuit has just started to power on, the one PMOS pipe P1 and the 2nd NMOS pipe N2 conducting, and the drain voltage of the 2nd NMOS pipe N2 is dragged down, namely the grid voltage of the 3rd PMOS pipe P3 drags down, the 3rd PMOS pipe P3 conducting, the drain voltage of the 5th NMOS pipe N5 is drawn high, make current mirror the 5th NMOS pipe N5, the 6th NMOS pipe N6 works and then makes whole circuit working, after whole circuit normal operation, the drain voltage of the 4th PMOS pipe P4 raises, namely the grid voltage of a NMOS pipe N1 raises, the one NMOS pipe N1 opens, the grid of the 2nd NMOS pipe N2 is dragged down, the 2nd NMOS pipe N2 turn-offs, and then make the 2nd PMOS manage P2, the 3rd PMOS pipe P3 turn-offs.
PMOS common-source common-gate current mirror the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7 keep two branch currents to equate, NMOS common-source common-gate current mirror the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5, the 6th NMOS pipe N6 make the base voltage of the first triode Q1 and the second triode Q2 accurately equate.Voltage above the second resistance R 2 is △ V
Be=V
Be2-V
Be1, R1=R3, the voltage above the first resistance R 1 is V
Be2, such the 4th PMOS pipe P4, the 6th PMOS pipe P6, the 3rd NMOS pipe N3, the 5th this electric current above branch road of NMOS pipe N5 are the first resistance R 1 and the electric current sum above the second resistance R 2, then by current mirror, are mirrored to output, like this I
1=I
R1+ I
R2=V
Be2/ R3+ △ V
Be/ R2, one is the electric current of positive temperature coefficient (PTC), one is the electric current of negative temperature coefficient, is compensated the I obtained
1Electric current is approximate temperature independent.
The second current reference unit is identical with the principle of work of the first current reference unit, specifically, referring to the principle of work of the first above-mentioned current reference unit, does not repeat them here.
The maximum current selecting circuit principle of work is as follows: I
1And I
2For the two-way input current, suppose I
1I
2, the 11 NMOS pipe N11, the 12 NMOS pipe N12 and the 13 NMOS pipe N13, the 14 NMOS pipe N14 excess current mirror mirror image I
2Electric current, the 7th NMOS pipe N7, the electric current above the 8th NMOS pipe N8 are I
1-I
2, the 9th NMOS pipe N9, the tenth NMOS pipe N10 mirror image the 7th NMOS pipe N7, the electric current above the 8th NMOS pipe N8, namely the 9th NMOS pipe N9, the electric current above the tenth NMOS pipe N10 are I
1-I
2, output Iref is the 9th NMOS pipe N9, the tenth NMOS pipe N10 and the 11 NMOS pipe N11, the 12 NMOS pipe N12 Liang Tiaozhi road circuit sum Iref=I
2+ I
1-I
2=I
1Suppose I
1<I
2The 13 NMOS pipe N13 has entered linear zone, cause the 7th NMOS pipe N7 to enter subthreshold region, top electric current is very little, the electric current that the 9th NMOS pipe N9, the tenth NMOS manage above N10 is also very little, can ignore, the 11 NMOS pipe N11, the 12 NMOS pipe N12 mirror image I2 electric current, output Iref=I
2, so just completed I
1And I
2The selection of middle higher value.
Fig. 5 and Fig. 6 are current reference circuit output current wave schematic diagram of the present invention, and the principle of work of integrated circuit is as follows: the first current reference unit and the second current reference unit produce respectively two reference current I
1And I
2, make I by the emitter junction area of triode in regulating circuit and the size of resistance
1And I
2Difference, wherein a reference current I
1In the temperature characterisitic of high-temperature region better and another reference current I
2Temperature characterisitic at low-temperature space is better, and two curves are in a certain temperature T
0Downcrossings.I
1And I
2After maximum current selecting circuit, be output as Iref, can find out at T
0I before
2I
1, Iref=I
2, T
0I afterwards
1I
2, Iref=I
1, the Iref curve obtained like this, all have temperature characterisitic preferably when high low temperature.
In summary it can be seen, compare current reference circuit basic in Fig. 1, the present invention has improved its some intrinsic shortcomings, especially in the situation that not by adding the high-order compensation circuit, the temperature characterisitic of output current benchmark has obtained larger lifting.
Claims (2)
1. current reference circuit, it is characterized in that, comprise the first current reference unit, the second current reference unit and maximum current selecting circuit, the output terminal of described the first current reference unit is connected with described maximum current selecting circuit first input end, the output terminal of described the second current reference unit is connected with described maximum current selecting circuit the second input end, and the output terminal of described maximum current selecting circuit is the output terminal of current reference circuit;
Described the first current reference unit, the second current reference unit are for producing respectively an independently reference current output, the reference current that the first current reference unit produces has preferably temperature characterisitic in the time of low temperature and current value is greater than the second current reference unit produces in the time of low temperature reference current, and the reference current that the second current reference unit produces has preferably temperature characterisitic in the time of high temperature and current value is greater than the first current reference unit produces in the time of high temperature reference current;
Described maximum current selecting circuit is used for selecting the output of the electric current Da De mono-road electric current of the first current reference unit and the generation of the second current reference unit as current reference circuit.
2. a kind of current reference circuit according to claim 1, it is characterized in that, described the first current reference unit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5, the 6th NMOS pipe N6, the first triode Q1, the second triode Q2, the first resistance R 1, the second resistance R 2 and the 3rd resistance R 3
Described maximum current selecting circuit comprises the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15 and the 16 NMOS pipe N16
Described the second current reference unit comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 21 NMOS pipe N21, the 22 NMOS pipe N22 the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 3rd triode Q3 and the 4th triode Q4, wherein,
The grid of the one PMOS pipe P1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a NMOS pipe N1 with drain electrode, the drain and gate of the grid of the one NMOS pipe N1 and the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the source electrode of the 6th PMOS pipe P6 is connected with the grid of the 8th PMOS pipe P8, the grid of the 2nd PMOS pipe P2 is connected with the grid of the 3rd PMOS pipe P3 with the drain electrode of the 2nd NMOS pipe N2 with drain electrode, the source electrode of the 3rd PMOS pipe P3 drain electrode and the 4th NMOS pipe N4, the grid of the 5th NMOS pipe N5, the grid of the 6th NMOS pipe N6 is connected with drain electrode, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 7th PMOS pipe P7 with the grid of the 3rd NMOS pipe N3 with drain electrode, the drain and gate of the drain electrode of the 3rd NMOS pipe N3 and the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7 is connected with the grid of the 9th PMOS pipe P9, the drain electrode of the 5th NMOS pipe N5 is connected with the source electrode of the 3rd NMOS pipe N3, the collector of source electrode and the first triode Q1 and base stage, one end of the first resistance R 1 connects, the emitter of the first triode Q1 is connected with an end of the second resistance R 2, the source electrode of the 6th NMOS pipe N6 and collector and the base stage of the second triode Q2, one end of the 3rd resistance R 3 connects, the source ground of the source electrode of the one NMOS pipe N1 and the 2nd NMOS pipe N2,
The drain electrode of the 8th PMOS pipe P8 is connected with the source electrode of the 9th PMOS pipe P9, the drain and gate of the drain electrode of the 9th PMOS pipe P9 and the 7th NMOS pipe N7, the grid of the 9th NMOS pipe N9, the drain electrode of the 13 NMOS pipe N13 connects, grid and the drain electrode of the source electrode of the 7th NMOS pipe N7 and the 8th NMOS pipe N8, the grid of the tenth NMOS pipe N10 connects, the source electrode of the 9th NMOS pipe N9 is connected with the drain electrode of the tenth NMOS pipe N10, the grid of the 11 NMOS pipe N11, the grid of the 13 NMOS pipe N13, grid and the drain electrode of the 15 NMOS pipe N15, the drain electrode of the 11 PMOS pipe P11 connects, the 11 NMOS pipe N11 source electrode with the drain electrode of the 12 NMOS pipe N12, be connected, the grid of the 12 NMOS pipe N12, the grid of the 14 NMOS pipe N14, grid and the drain electrode of the 16 NMOS pipe N16, the source electrode of the 15 NMOS pipe N15 connects, the tenth PMOS pipe P10 is connected with the source electrode of drain electrode the 11 PMOS pipe P11,
The drain electrode of the 9th NMOS pipe N9 is connected the output terminal as current reference circuit with the drain electrode of the 11 NMOS pipe N11;
The grid of the grid of the tenth PMOS pipe P10 and the 12 PMOS pipe P12, grid and the drain electrode of the 13 PMOS pipe P13, the source electrode of the 15 PMOS pipe P15, the grid of the 22 NMOS pipe N22 connects, the grid of the grid of the 11 PMOS pipe P11 and the 14 PMOS pipe P14, grid and the drain electrode of the 15 PMOS pipe P15, the drain electrode of the 18 NMOS pipe N18 connects, the drain electrode of the 12 PMOS pipe P12 is connected with the source electrode of the 14 PMOS pipe P14, the drain and gate of the drain electrode of the 14 PMOS pipe P14 and the 17 NMOS pipe N17, the grid of the 18 NMOS pipe N18 connects, the drain and gate of the source electrode of the 17 NMOS pipe N17 and the 19 NMOS pipe N19, the drain electrode of the 20 NMOS pipe N20, the drain electrode of the 16 PMOS pipe P16 connects, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 20 NMOS pipe N20, the source electrode of the 19 NMOS pipe N19 and collector and the base stage of the 3rd triode Q3, one end of the 4th resistance R 4 connects, the source electrode of the 20 NMOS pipe N20 and collector and the base stage of the 4th triode Q4, one end of the 6th resistance R 6 connects, the emitter of the 4th triode Q4 is connected with an end of the 5th resistance R 5, grid and the drain electrode of the grid of the 16 PMOS pipe P16 and the 17 PMOS pipe P17, the drain electrode of the 21 NMOS pipe N21 connects, grid and the drain electrode of the grid of the 21 NMOS pipe N21 and the 18 PMOS pipe P18, the drain electrode of the 22 NMOS pipe N22 connects, the source ground of the source electrode of the 21 NMOS pipe N21 and the 22 NMOS pipe N22,
The source grounding of the source electrode of the source electrode of the source electrode of the source electrode of the emitter of the emitter of the other end of the other end of the other end of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the second triode Q2, the 3rd triode Q3, the 8th NMOS pipe N8, the tenth NMOS pipe N10, the 12 NMOS pipe N12, the 14 NMOS pipe N14 and the 16 NMOS pipe N16;
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 16 PMOS pipe P16, the 17 PMOS pipe P17 is connected power supply with the source electrode of the 18 PMOS pipe P18.
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| CN106774584A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
| CN109085875A (en) * | 2017-06-14 | 2018-12-25 | 乐山加兴科技有限公司 | Comparison circuit for a reference source |
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN112825002A (en) * | 2019-11-21 | 2021-05-21 | 中芯国际集成电路制造(上海)有限公司 | Reference current source circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109085875A (en) * | 2017-06-14 | 2018-12-25 | 乐山加兴科技有限公司 | Comparison circuit for a reference source |
| CN112825002A (en) * | 2019-11-21 | 2021-05-21 | 中芯国际集成电路制造(上海)有限公司 | Reference current source circuit |
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
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