CN109085875A - Comparison circuit for a reference source - Google Patents
Comparison circuit for a reference source Download PDFInfo
- Publication number
- CN109085875A CN109085875A CN201710449289.9A CN201710449289A CN109085875A CN 109085875 A CN109085875 A CN 109085875A CN 201710449289 A CN201710449289 A CN 201710449289A CN 109085875 A CN109085875 A CN 109085875A
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- Prior art keywords
- nmos tube
- tube
- connects
- drain electrode
- grid
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000005611 electricity Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of comparison circuits for a reference source.The circuit is made of the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MO4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the first triode Q1, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and resistance R；By selecting biggish signal in two-way input signal, the purpose for improving a reference source output accuracy is realized.It is particularly suitable for the comparison circuit of second order a reference source.
Description
Technical field
The invention belongs to power technique fields, more particularly to a kind of comparison circuit for a reference source.
Background technique
Reference voltage source is widely used in power regulator, A/D and D/A converter, number as basic circuit unit
According in acquisition system and various measuring devices.With the development of integrated circuit technique, increasingly to the performance requirement of chip
Height, many chips need accurate and stable reference voltage source.It is at present the accuracy for improving a reference source, proposes second order very
To a reference source of high-order, but with the increase of subcircuits, the stability of circuit will be by extreme influence, in the benchmark of second order
In source, generallys use two branches and generate two signals, how to select better signal, be current problem.
Summary of the invention
It is to be solved by this invention, mainly aiming at current second order reference current source, propose a kind of for a reference source
Comparison circuit.
To achieve the above object, the present invention adopts the following technical scheme:
A kind of comparison circuit for a reference source, by the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3,
4th PMOS tube MO4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the first triode Q1, the first NMOS tube MN1, the 2nd NMOS
Pipe MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7,
8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and resistance R are constituted；The source electrode of first PMOS tube MP1 connects electricity
Source, its grid and drain interconnection, drain electrode connect the source electrode of the 4th PMOS tube MP4；The grid of 4th PMOS tube MP4 drains mutually with it
Even, drain electrode connects the drain electrode of the first NMOS tube MN1；The drain electrode of first NMOS tube MN1 is first input end, and source electrode connects the 6th
The drain electrode of NMOS tube MN6；The grid and its drain interconnection of 6th NMOS tube MN6, source electrode ground connection；The source of second PMOS tube MP2
Pole connects power supply, grid and drain interconnection, and drain electrode connects the source electrode of the 5th PMOS tube MP5；The grid of 5th PMOS tube MP5 and leakage
Pole interconnection；The source electrode of third PMOS tube MP3 connects power supply, and grid connects the drain electrode of the second PMOS tube MP2, and drain electrode meets the 6th PMOS
The source electrode of pipe MP6；The grid of 6th PMOS tube MP6 connects the drain electrode of the 5th PMOS tube MP5, and drain electrode is followed by first by resistance R
The collector and base stage of triode Q1；The emitter of first triode Q1 is grounded；6th PMOS tube MP6 drain electrode is comparison circuit
Output end；The drain electrode of second NMOS tube MN2 connects the drain electrode of the 5th PMOS tube MP5, and grid connects the grid of the first NMOS tube MN1,
Its source electrode connects the drain electrode of the 7th NMOS tube MN7；The grid of 7th NMOS tube MN7 connects the source electrode of the first NMOS tube MN1, and source electrode connects
Ground；The drain electrode of third NMOS tube MN3 connects the drain electrode of the 5th PMOS tube MP5, and grid connects the grid and the 5th of the 4th NMOS tube MN4
The grid of NMOS tube MN5, source electrode connect the drain electrode of the 8th NMOS tube MN8；The grid of 8th NMOS tube MN8 connects the 5th NMOS tube
The source electrode of MN5, source electrode ground connection；The drain electrode of third NMOS tube MN4 and the drain electrode of the 5th NMOS tube MN5 are the second input terminal；The
The source electrode of four NMOS tube MN4 connects the drain electrode of the 9th NMOS tube MN9；The grid of 9th NMOS tube MN9 connects the source of the 5th NMOS tube MN5
Pole, source electrode ground connection；The drain and gate of tenth NMOS tube MN10 connects the source electrode of the 5th NMOS tube MN5, source electrode ground connection.
Beneficial effects of the present invention are that can effectively select the stronger signal all the way of signal in two-way input end signal.
Detailed description of the invention
Fig. 1 is electrical block diagram of the invention.
Specific embodiment
As shown in Figure 1, a kind of comparison circuit for a reference source of the invention, by the first PMOS tube MP1, the second PMOS tube
MP2, third PMOS tube MP3, the 4th PMOS tube MO4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the first triode Q1, first
NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube
MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and resistance R are constituted；First
The source electrode of PMOS tube MP1 connects power supply, its grid and drain interconnection, and drain electrode connects the source electrode of the 4th PMOS tube MP4；4th PMOS tube
The grid of MP4 and its drain interconnection, drain electrode connect the drain electrode of the first NMOS tube MN1；The drain electrode of first NMOS tube MN1 is first defeated
Enter end, source electrode connects the drain electrode of the 6th NMOS tube MN6；The grid and its drain interconnection of 6th NMOS tube MN6, source electrode ground connection；
The source electrode of second PMOS tube MP2 connects power supply, grid and drain interconnection, and drain electrode connects the source electrode of the 5th PMOS tube MP5；5th
The grid and drain interconnection of PMOS tube MP5；The source electrode of third PMOS tube MP3 connects power supply, and grid connects the leakage of the second PMOS tube MP2
Pole, drain electrode connect the source electrode of the 6th PMOS tube MP6；The grid of 6th PMOS tube MP6 connects the drain electrode of the 5th PMOS tube MP5, leakage
Pole is followed by the collector and base stage of the first triode Q1 by resistance R；The emitter of first triode Q1 is grounded；6th PMOS tube
MP6 drain electrode is the output end of comparison circuit；The drain electrode of second NMOS tube MN2 connects the drain electrode of the 5th PMOS tube MP5, and grid connects
The grid of one NMOS tube MN1, source electrode connect the drain electrode of the 7th NMOS tube MN7；The grid of 7th NMOS tube MN7 connects the first NMOS tube
The source electrode of MN1, source electrode ground connection；The drain electrode of third NMOS tube MN3 connects the drain electrode of the 5th PMOS tube MP5, and grid connects the 4th
The grid of the grid of NMOS tube MN4 and the 5th NMOS tube MN5, source electrode connect the drain electrode of the 8th NMOS tube MN8；8th NMOS tube
The grid of MN8 connects the source electrode of the 5th NMOS tube MN5, source electrode ground connection；The drain electrode of third NMOS tube MN4 and the 5th NMOS tube MN5
Drain electrode be the second input terminal；The source electrode of 4th NMOS tube MN4 connects the drain electrode of the 9th NMOS tube MN9；The grid of 9th NMOS tube MN9
Pole connects the source electrode of the 5th NMOS tube MN5, source electrode ground connection；The drain and gate of tenth NMOS tube MN10 meets the 5th NMOS tube MN5
Source electrode, source electrode ground connection.
The operation principle of the present invention is that:
First input end and the second input terminal input two-way current signal respectively, it is assumed that are respectively I1And I2；If I1>I2；Then
The image current mirror image I that third NMOS tube MN3, the 4th NMOS tube MN4, the 8th NMOS tube MN8, the 9th NMOS tube MN9 are constituted2；
And the electric current I of the second NMOS tube MN2 and the 7th the first NMOS tube of NMOS tube mirror image MN11, then final MN7 then the second NMOS tube
Electric current on MN2, the 7th NMOS tube MN7 is I1-I2；Output electric current is the first NMOS tube MN1 and the 6th NMOS tube MN6 and the 5th
The sum of electric current on NMOS tube MN5, the tenth NMOS tube MN10 I2+I1-I2=I1；If I1<I2, then the 4th NMOS tube MN4 enters
Linear zone, causes the first NMOS tube MN1 also to enter linear zone, the electric current for then flowing through MN1 is very small, then the second NMOS tube
Electric current on MN2 and the 7th NMOS tube MN7 is very small, and output at this time is I2, realize the selection to larger current signal.
Claims (1)
1. the comparison circuit of a reference source is used for, by the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th
PMOS tube MO4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the first triode Q1, the first NMOS tube MN1, the second NMOS tube
MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7,
Eight NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and resistance R are constituted；The source electrode of first PMOS tube MP1 connects electricity
Source, its grid and drain interconnection, drain electrode connect the source electrode of the 4th PMOS tube MP4；The grid of 4th PMOS tube MP4 drains mutually with it
Even, drain electrode connects the drain electrode of the first NMOS tube MN1；The drain electrode of first NMOS tube MN1 is first input end, and source electrode connects the 6th
The drain electrode of NMOS tube MN6；The grid and its drain interconnection of 6th NMOS tube MN6, source electrode ground connection；The source of second PMOS tube MP2
Pole connects power supply, grid and drain interconnection, and drain electrode connects the source electrode of the 5th PMOS tube MP5；The grid of 5th PMOS tube MP5 and leakage
Pole interconnection；The source electrode of third PMOS tube MP3 connects power supply, and grid connects the drain electrode of the second PMOS tube MP2, and drain electrode meets the 6th PMOS
The source electrode of pipe MP6；The grid of 6th PMOS tube MP6 connects the drain electrode of the 5th PMOS tube MP5, and drain electrode is followed by first by resistance R
The collector and base stage of triode Q1；The emitter of first triode Q1 is grounded；6th PMOS tube MP6 drain electrode is comparison circuit
Output end；The drain electrode of second NMOS tube MN2 connects the drain electrode of the 5th PMOS tube MP5, and grid connects the grid of the first NMOS tube MN1,
Its source electrode connects the drain electrode of the 7th NMOS tube MN7；The grid of 7th NMOS tube MN7 connects the source electrode of the first NMOS tube MN1, and source electrode connects
Ground；The drain electrode of third NMOS tube MN3 connects the drain electrode of the 5th PMOS tube MP5, and grid connects the grid and the 5th of the 4th NMOS tube MN4
The grid of NMOS tube MN5, source electrode connect the drain electrode of the 8th NMOS tube MN8；The grid of 8th NMOS tube MN8 connects the 5th NMOS tube
The source electrode of MN5, source electrode ground connection；The drain electrode of third NMOS tube MN4 and the drain electrode of the 5th NMOS tube MN5 are the second input terminal；The
The source electrode of four NMOS tube MN4 connects the drain electrode of the 9th NMOS tube MN9；The grid of 9th NMOS tube MN9 connects the source of the 5th NMOS tube MN5
Pole, source electrode ground connection；The drain and gate of tenth NMOS tube MN10 connects the source electrode of the 5th NMOS tube MN5, source electrode ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710449289.9A CN109085875A (en) | 2017-06-14 | 2017-06-14 | Comparison circuit for a reference source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710449289.9A CN109085875A (en) | 2017-06-14 | 2017-06-14 | Comparison circuit for a reference source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109085875A true CN109085875A (en) | 2018-12-25 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710449289.9A Pending CN109085875A (en) | 2017-06-14 | 2017-06-14 | Comparison circuit for a reference source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109085875A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712590A (en) * | 1995-12-21 | 1998-01-27 | Dries; Michael F. | Temperature stabilized bandgap voltage reference circuit |
| US20050046461A1 (en) * | 2003-08-26 | 2005-03-03 | Texas Instruments Incorporated | Cross-conduction blocked power selection comparison/control circuitry with NTC (negative temperature coefficient) trip voltage |
| US20070046363A1 (en) * | 2005-08-26 | 2007-03-01 | Toru Tanzawa | Method and apparatus for generating a variable output voltage from a bandgap reference |
| CN103412597A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Current reference circuit |
| US20140285175A1 (en) * | 2011-11-04 | 2014-09-25 | Freescale Semiconductor, Inc. | Reference voltage generating circuit, integrated circuit and voltage or current sensing device |
-
2017
- 2017-06-14 CN CN201710449289.9A patent/CN109085875A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712590A (en) * | 1995-12-21 | 1998-01-27 | Dries; Michael F. | Temperature stabilized bandgap voltage reference circuit |
| US20050046461A1 (en) * | 2003-08-26 | 2005-03-03 | Texas Instruments Incorporated | Cross-conduction blocked power selection comparison/control circuitry with NTC (negative temperature coefficient) trip voltage |
| US20070046363A1 (en) * | 2005-08-26 | 2007-03-01 | Toru Tanzawa | Method and apparatus for generating a variable output voltage from a bandgap reference |
| US20140285175A1 (en) * | 2011-11-04 | 2014-09-25 | Freescale Semiconductor, Inc. | Reference voltage generating circuit, integrated circuit and voltage or current sensing device |
| CN103412597A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Current reference circuit |
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Application publication date: 20181225 |