CN115016580A - Current divider with wide input range - Google Patents

Current divider with wide input range Download PDF

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CN115016580A
CN115016580A CN202210526864.1A CN202210526864A CN115016580A CN 115016580 A CN115016580 A CN 115016580A CN 202210526864 A CN202210526864 A CN 202210526864A CN 115016580 A CN115016580 A CN 115016580A
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current
input
voltage
source
nmos transistor
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CN115016580B (en
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樊华
徐凯
常伟鹏
刁小芃
冯浪
赵攀峰
冯全源
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a wide input range current divider, and relates to the field of integrated circuits. The divider circuit is simple in structure, only three MOS devices are needed, the design area of a chip is reduced, in addition, the circuit can work under a lower power supply voltage, and the power consumption of the whole divider circuit is smaller; and by utilizing the linear relation between the MOS tube body voltage and the drain-source current, the voltage which is equivalently converted from the input current is input into the body end of the MOS tube, and the current generated by the MOS tube is used for division operation, so that the range of the input current is reduced in proportion, and the function of dividing the two input currents in a wider range of the input current can be realized.

Description

Current divider with wide input range
Technical Field
The invention relates to the field of integrated circuits, in particular to a current divider with a wide input range.
Background
Dividers are basic functional blocks of cmos signal processing circuits, such as analog computation, fuzzy logic, and communication systems. As electronic devices are gradually miniaturized, the requirements for circuit structures are gradually becoming simpler; meanwhile, the input signal range of any circuit is an important index, and the wider range can enable the circuit to be suitable for more application occasions.
FIG. 1 shows a conventional document 1[ Low-voltage, Low power, Low area, CMOS current-mode divider circuit ]]A current divider circuit structure is realized by using an MOS transistor M in FIG. 1 A Drain-source current I when operating in linear region D1 And drain-source voltage V DS1 Proportional to the gate-source voltage V GS1 And a threshold voltage V T1 The difference is inversely proportional: i is D1 ＝I 1 ＝β 1 (V GS1 -V T1 )·V DS1 In the formula beta 1 For MOS transistor process parameters, pass M B And R 1 Will be reacted with I D The term of inverse proportion is equivalent to a voltage term V X ：I 1 ＝β 1 ·V X ·V DS1 Will V X Conversion to input current I 3 The formula (c) yields: v DS1 ＝(1/β 1 ·V X )·(I 1 /I 3 ) Realizing a current I 1 And current I 3 The structure only needs four MOS tubes, and has the advantages of simple structure, low power consumption, low power supply voltage requirement and the like. But due to problems with the circuit configuration, when I 3 After increasing to a certain value, the NMOS tube M A Will enter a saturation region and further cause I 3 /I 1 The relation of linear change is not existed any more, and the circuit has no division function at this moment, so that the input current I 3 Is limited in scope.
FIG. 2 shows document 2[ Low-power high-speed analog multiplexer/divider based on a new current squarer circuit]The current divider structure provided in (1) realizes the functions of a four-quadrant multiplier and divider by using the characteristic that the gate-source voltage and the drain-source current are in exponential relation when an MOS tube works in a weak inversion type, namely (X + Y) 2 -(X-Y) 2 4 XY; the left half of the circuit is implemented using two new current squaring cells (I) X +I Y ) 2 Right half implementation (I) X -I Y ) 2 Thereby obtaining I O1 ＝2I B +(I X +I Y ) 2 /4I B ，I O2 ＝2I B +(I X -I Y ) 2 /4I B And further to obtain I OUT ＝I O1 -I O2 ＝(I X ·I Y )/I B . The circuit has the advantages of low power consumption, low power supply voltage, low nonlinearity and the like, and weak inversion means that the current of an MOS transistor in the circuit is small, usually between tens and hundreds of nanoamperes, so that the range of input current is limited, and 12 MOS transistors are required.
FIG. 3 shows document 3[ CMOS analog current-mode multiplexer/divider circuit operating in triple-configuration with bulk-drive technologies ]]The multiplier/divider structure based on the body driving technology is provided to expand the range and the precision of the multiplier/divider structure, and the multiplication and division functions are realized by offsetting nonlinear terms in the I-V characteristic of the MOS tube working in a saturation region according to a proper interconnection mode, and the output current I of the upper half circuit of the figure 3 GM And an input current I X And I Y The square root of the product of (c) is proportional to:
Figure BDA0003644727850000021
then the current is input to the lower half circuit through a current mirror to generate
Figure BDA0003644727850000022
The structure has small power consumption and small required area, but relatively speaking, the realization of the circuit is more complex and 20 MOS transistors are needed.
Disclosure of Invention
In view of the above problems, a current divider with a wide input range is proposed.
The technical scheme provided by the invention is as follows:
a wide input range current divider, comprising: comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a first resistor R 1 A second resistor R 2 First current ofSource I 1 A second current source I 2 And a third current source I 3 (ii) a The first current source I 1 Input terminal, second current source I 2 Input end, source electrode of first PMOS transistor MP1 and second resistor R 2 One end of which is connected with a power supply V DD A first current source I 1 Is connected with the first resistor R 1 And a source terminal of a first NMOS transistor MN1, the first resistor R 1 The other end of the first and second electrodes is grounded; the second current source I 2 The output end of the transistor is connected with the grid electrode and the drain electrode of the first NMOS transistor MN1 and the grid electrode of the second NMOS transistor MN 2; a second resistor R 2 The other end of the first PMOS transistor MP1 is connected with the body end of the first PMOS transistor MP1 and the third current source I 3 Of a third current source I 3 The output end of the transformer is grounded; the gate of the first PMOS transistor MP1 is connected with a bias voltage V B The drain is connected with the drain of the second NMOS transistor MN2 and serves as an output end V OUT The source of the second NMOS transistor MN2 is grounded;
the first NMOS transistor MN1 and the first PMOS transistor MP1 work in a saturation region, and the second NMOS transistor MN2 works in a linear region.
The divider circuit has the advantages that the divider circuit is simple in structure, only three MOS devices are needed, the design area of a chip is reduced, in addition, the circuit can work under lower power supply voltage, and the power consumption of the whole divider circuit is smaller; and by utilizing the linear relation between the voltage of the MOS tube body and the drain-source current, the voltage which is equivalently converted by the input current is input to the body end of the MOS tube, and the current generated by the MOS tube is used for division operation, so that the range of the input current is reduced according to a certain proportion, and the function of dividing the two input currents in a wider input current range can be realized.
Drawings
Fig. 1 is a circuit configuration for implementing an analog divider in prior art document 1.
Fig. 2 is a circuit configuration for implementing the analog divider in prior art document 2.
Fig. 3 shows a circuit configuration for implementing the analog divider in prior art document 3.
FIG. 4 is a diagram of a wide input range current divider according to the present invention.
FIG. 5 shows the present inventionThe divider inputs current I 1 When the current is 5 muA, the current I is input 3 And conversion of the current I DP The relationship of (1).
FIG. 6 shows the input current I of the divider according to the present invention 1 When the current is 5 muA, the current I is input 3 And an output voltage V OUT Is measured in the graph (c).
FIG. 7 shows the input current I of the divider according to the present invention 1 When the current is 30 muA, the current I is input 3 And conversion of the current I DP The relationship of (1).
FIG. 8 shows the input current I of the divider according to the present invention 1 When the current is 30 muA, the current I is input 3 And an output voltage V OUT Is measured in the graph (c).
Detailed Description
It should be understood that the embodiments described herein are only for clearly showing the technical advantages of the present invention and are not intended to limit the present invention.
The invention is explained in detail below with reference to the drawings:
fig. 4 shows a current divider circuit structure according to the present invention. In FIG. 4, V DD For the power voltage, the minimum is 2.2V, GND is ground voltage, and in order to implement the function of division, the first NMOS transistor MN1 and the first PMOS transistor MP1 operate in the saturation region, and the second NMOS transistor MN2 operates in the linear region. A third current source I 3 Through a resistance R 2 Then at R 2 Voltage drop V generated in the upper part 1 Comprises the following steps:
V 1 ＝I 3 ·R 2 (1)
voltage V 1 The voltage input to the bulk terminal of the first PMOS transistor MP1 is heard as V because the voltage at the source terminal of MP1 does not change 1 Is equal to the source voltage V of the PMOS transistor MP1 BSP According to the change of the saturation region PMOS tube V GSP And I DP The relationship of (1):
Figure BDA0003644727850000031
in the formula K P The threshold of the first PMOS transistor MP1 is the process parameter of the PMOS transistor MP1Value voltage V TP Can be expressed as:
Figure BDA0003644727850000032
in the formula V T0 Is V BSP A threshold voltage at which the voltage is 0, γ is the coefficient of the body effect,
Figure BDA0003644727850000033
is Fermi potential, V BSP Is the source voltage of the first PMOS transistor MP1, and further arranges the formula (3):
Figure BDA0003644727850000034
taylor expansion and arrangement are carried out on the formula to obtain:
Figure BDA0003644727850000035
substituting formula (5) into formula (2) to obtain:
Figure BDA0003644727850000037
wherein
Figure BDA0003644727850000036
Figure BDA0003644727850000041
Formula (1) is substituted for formula (6), and further:
I DP ＝K 1 +K 2 I 3 R 2 (9)
from equation (6), the right side of the equation divides V BSP Are all constant, soFirst PMOS transistor MP1 drain-source current I DP And a source voltage V BSP In a linear relationship. Thereby leading the drain-source current I of the first PMOS pipe MP1 DP And gate source voltage V GSP Is converted into a drain-source current I DP And source voltage V BSP A linear relationship therebetween. Observation formula (9), input Current I 3 Is equivalently converted into a drain-source current I of a first PMOS tube MP1 DP Change of (3), rational design of K in the formula 1 、K 2 And R 2 Can be used for the current I with larger value and range 3 Conversion to I with smaller value and range DP That is, the equivalent current input to the first PMOS transistor MP1 is relatively small compared to the input current, so even if the input current varies in a large range, the second NMOS transistor MN2 always operates in the linear region, and does not enter the saturation region due to the excessive input current, thereby ensuring that the divider circuit can still operate normally in a wide input current range. The second NMOS transistor MN2 operates in the linear region and its drain-source current I D2 And gate source voltage V GS2 And a drain-source voltage V DS2 The relationship of (1) is:
I D2 ＝K N2 (V GS2 -V T2 )V DS2 (10)
wherein K N2 Is the process parameter, V, of the second NMOS transistor MN2 T2 For the threshold voltage of the second NMOS transistor MN2, the above formula shows that V DS2 And I D2 Is proportional to (V) GS2 -V T2 ) In inverse proportion. To obtain V GS2 And I D2 With the circuit structure of fig. 2, the following relationships are obtained:
V GS2 ＝V GS1 +V 2 ＝V T1 +V GS1 -V T1 +V 2 ≈V T1 +V 2 (11)
in the formula:
V 2 ＝I 1 ·R 1 (12)
in formula (11), (V) GS1 -V T1 ) Setting the bias current I of the MN1 tube for the overdrive voltage of the first NMOS tube MN1 2 At 1 mua, the overdrive voltage of MN1 is very small,negligible, the body terminals of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to their source terminals, so the threshold voltages of MN1 and MN2 are equal. Substituting formula (11) for formula (10) to obtain:
I D2 ＝K N2 ·V 2 ·V DS2 (13)
the bias current of the second NMOS transistor MN2 is provided by the third NMOS transistor MN3, so I D2 ＝I D3 Substituting formulae (1), (6) and (12) into formula (13) and finishing to obtain:
Figure BDA0003644727850000042
according to the above analysis process, the output voltage V OUT And a first input current I 1 And a third input current I 3 The ratio of the two is in direct proportion, and the function of current division is realized.
FIG. 5 shows the first input current I 1 5 muA, third input current I 3 When the current changes, the drain-source current I of the first PMOS pipe MP1 DP When I changes 3 Linearly increasing from 0 muA to 100 muA, I DP Changes about 1.90 muA along with linearity, and outputs voltage V OUT As shown in fig. 6, the linear increase was about 19.31 mV; FIG. 7 shows the first input current I 1 30 μ a, third input current I 3 When the current changes, the drain-source current I of the first PMOS pipe MP1 DP When a change in 3 Linearly increasing from 0 muA to 100 muA, I DP Changes about 1.91 muA along with linearity, and outputs voltage V OUT As shown in fig. 8, the linear increase was about 2.36 mV; table 1 gives I 1 And I 3 Corresponding currents I at different currents DP And an output voltage V OUT Theoretical calculations and simulated values of (c). Observed in combination with the figures and tables to obtain 3 Increasing a larger value will cause I to DP Increasing by a smaller value at the output voltage V OUT Where the equivalent translates into a smaller voltage rise, and I 1 The increase will result in V OUT There is a large voltage drop, and the voltage rise and voltage drop follow equation (14), illustrating the electricity proposed by the present inventionThe current divider can ensure the normal function of the circuit in a wider input current range, and is suitable for application occasions with wide input current ranges.
TABLE 1 output voltage values corresponding to different input currents
Figure BDA0003644727850000051
The table 2 compares the advantages and disadvantages of the proposed structure and the existing structure, and it can be seen that the proposed divider has advantages in both circuit structure and input current range, overcomes the limitation of other structures on the input current range, and can implement the function of dividing two input currents in a larger range. Comparison of current divider presented in Table 2 with existing current divider circuit
Figure BDA0003644727850000052

Claims (1)

1. A wide input range current divider, comprising: comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a first resistor R 1 A second resistor R 2 A first current source I 1 A second current source I 2 And a third current source I 3 (ii) a The first current source I 1 Input terminal, second current source I 2 Input end, source electrode of first PMOS transistor MP1 and second resistor R 2 One end of which is connected with a power supply V DD A first current source I 1 Is connected with the first resistor R 1 And a source terminal of a first NMOS transistor MN1, the first resistor R 1 The other end of the first and second electrodes is grounded; the second current source I 2 The output end of the transistor is connected with the grid electrode and the drain electrode of the first NMOS transistor MN1 and the grid electrode of the second NMOS transistor MN 2; a second resistor R 2 The other end of the first PMOS transistor MP1 is connected with the body end of the first PMOS transistor MP1 and the third current source I 3 Of a third current source I 3 The output end of the transformer is grounded; the gate of the first PMOS transistor MP1 is connected with a bias voltage V B The drain is connected with the drain of the second NMOS transistor MN2 and serves as an output end V OUT The source of the second NMOS transistor MN2 is grounded;
the first NMOS transistor MN1 and the first PMOS transistor MP1 work in a saturation region, and the second NMOS transistor MN2 works in a linear region.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070229166A1 (en) * 2006-03-31 2007-10-04 Joseph Shor Buffered cascode current mirror
CN102437735A (en) * 2011-11-25 2012-05-02 上海新进半导体制造有限公司 Switch power supply and divider therefor
CN103106063A (en) * 2013-02-26 2013-05-15 电子科技大学 Analog multiplication and division method operational circuit
CN107291145A (en) * 2017-08-09 2017-10-24 上海华虹宏力半导体制造有限公司 A kind of current-mode maximum value circuit
CN113778159A (en) * 2021-09-26 2021-12-10 电子科技大学 Low-power-consumption current divider

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070229166A1 (en) * 2006-03-31 2007-10-04 Joseph Shor Buffered cascode current mirror
CN102437735A (en) * 2011-11-25 2012-05-02 上海新进半导体制造有限公司 Switch power supply and divider therefor
CN103106063A (en) * 2013-02-26 2013-05-15 电子科技大学 Analog multiplication and division method operational circuit
CN107291145A (en) * 2017-08-09 2017-10-24 上海华虹宏力半导体制造有限公司 A kind of current-mode maximum value circuit
CN113778159A (en) * 2021-09-26 2021-12-10 电子科技大学 Low-power-consumption current divider

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