CN107248540B - Based on transverse structure LED and preparation method thereof - Google Patents
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- CN107248540B CN107248540B CN201710347693.5A CN201710347693A CN107248540B CN 107248540 B CN107248540 B CN 107248540B CN 201710347693 A CN201710347693 A CN 201710347693A CN 107248540 B CN107248540 B CN 107248540B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 59
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000002425 crystallisation Methods 0.000 claims abstract description 29
- 230000008025 crystallization Effects 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 169
- 239000011241 protective layer Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 7
- 241000931526 Acer campestre Species 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims 2
- 238000005499 laser crystallization Methods 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 238000011161 development Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 239000007924 injection Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
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- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910021627 Tin(IV) chloride Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/34—Materials of the light emitting region containing only elements of Group IV of the Periodic Table
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Abstract
The present invention relates to one kind based on transverse structure LED and preparation method thereof.Wherein, the preparation method includes: selection SOI substrate；Ge seed layer, Ge body layer and oxide layer are successively grown in the SOI substrate using CVD technique；Ge epitaxial layer after forming crystallization using Ge seed layer described in LRC technique crystallization and the Ge body layer；The oxide layer is etched using dry etch process；The Ge epi-layer surface after crystallization grows GeSn layers；Prepare the region N-type Ge and the region p-type Ge；Metal contact electrode is made to complete the preparation of the transverse structure LED；The present invention uses laser crystallization process again, prepares the low Ge epitaxial layer of dislocation density on soi substrates, and prepare GeSn layers of high quality direct band gap, then realizes a kind of p+- Ge/ direct band gap GeSn/n+Transverse structure LED of-Ge and preparation method thereof.
Description
Technical field
The invention belongs to technical field of semiconductor device preparation, in particular to a kind of to be based on transverse structure LED and its preparation side
Method.
Background technique
In recent years, with the development of optical communication technique, speed fiber optic communication systems require also increasingly semiconductor LED
Height, integrated development trend require semiconductor LED and other photoelectric devices integrated.If they can be integrated in a chip
On, information transfer rate, storage and processing capacity will be greatly enhanced, this will make Information Technology Development to a completely new rank
Section.Therefore, to the research of luminescent device, it has also become the focus and emphasis studied in current area.
It is compatible that traditional longitudinal P iN structure luminescent device is unsuitable for waveguide.If considering luminescent device and waveguide in optical interconnection
It is integrated, the area i of lateral PiN luminescent device is not only the light emitting region of device and the waveguide section of optical transport.Therefore, it designs
Manufacture lateral wave conductivity type LED will be integrated one of the important directions of the following photoelectricity.
Meanwhile GeSn alloy (Sn component is higher than 8%) is direct band-gap semicondictor, using it as light source device on Si substrate
Part active layer, not only the luminous efficiency of device is high, but also its process structure and existing Si process compatible, and great development and application is latent
It is relatively difficult directly to prepare high quality GeSn alloy since GeSn alloy and Si substrate lattice mismatch are big on a si substrate for power.Work
Solution in skill is that Ge buffer layer is first prepared on Si substrate, then further prepares GeSn alloy on Ge buffer layer.Cause
This, the quality of Ge buffer layer is directly related to the quality of subsequent GeSn alloy on Si substrate.From Ge buffer layer on current Si substrate
Realization situation from the point of view of, since lattice mismatch is larger between Si substrate and Ge epitaxial layer, common process preparation Ge buffer layer position
Dislocation density is high, is unfavorable for the preparation of subsequent high quality GeSn alloy.
Therefore the LED for selecting which kind of material and technique to prepare high quality becomes particularly important.
Summary of the invention
In order to improve the performance of existing luminescent device, the present invention uses laser crystallization process again, on soi substrates constituency system
The standby low Ge buffer layer of dislocation density, and high quality direct band gap GeSn epitaxial layer is prepared, then realize a kind of p+The direct band of-Ge/
Gap GeSn/n+Transverse structure LED of-Ge and preparation method thereof；The technical problem to be solved in the present invention is by the following technical programs
It realizes:
An embodiment provides a kind of preparation methods based on transverse structure LED, comprising:
(a) SOI substrate is chosen；
(b) Ge seed layer, Ge body layer and oxide layer are successively grown in SOI substrate using CVD technique；
(c) the Ge epitaxial layer after crystallization is formed using LRC technique crystallization Ge seed layer and Ge body layer；
(d) dry etch process etching oxidation layer is used；
(e) the Ge epi-layer surface after crystallization grows GeSn layers；
(f) P ion is injected separately into Ge epitaxial layer and B ion forms the region N-type Ge and the region p-type Ge；
(g) Metal contact electrode is prepared to complete the preparation of transverse structure LED.
In one embodiment of the invention, step (b) includes:
(b1) at a temperature of 275 DEG C~325 DEG C, using chemical vapor deposition (Chemical Vapor Deposition,
CVD) technique grows Ge seed layer on SOI substrate surface；
(b2) at a temperature of 500 DEG C~600 DEG C, Ge body layer is grown in Ge seed crystal surface using CVD technique；
(b3) SiO is deposited in Ge main body layer surface using CVD technique2Form oxide layer.
In one embodiment of the invention, in step (b), Ge seed layer is with a thickness of 40~50nm；Ge main body thickness
Degree is 120~150nm；Oxidated layer thickness is 150nm.
In one embodiment of the invention, step (c) includes:
(c1) the entire substrate material including Si substrate, Ge seed layer, Ge body layer and oxide layer is heated to 700 DEG C；
(c2) the Ge epitaxial layer after crystallization is formed using LRC technique crystallization Ge seed layer and Ge body layer；Wherein LRC technique
Optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/
s。
Wherein, crystallization (Laser re-crystallization, abbreviation LRC) technique is a kind of thermal induced phase transition knot to laser again
Brilliant method makes Ge epitaxial layer fusing recrystallization on Si substrate by laser heat treatment, and the dislocation for laterally discharging Ge epitaxial layer lacks
It falls into, not only reduces the dislocation density and surface roughness of Ge material, and improve Ge/SOI substrate interface quality.
In one embodiment of the invention, step (e) includes:
In H2350 DEG C of temperature are hereinafter, using SnCl in atmosphere4And GeH4Respectively as the source Sn and Ge, in Ge epi-layer surface
Grow undoped direct band gap GeSn layers.
In one embodiment of the invention, in step (e) GeSn layers with a thickness of 250~300nm.
In one embodiment of the invention, step (f) includes:
(f1) the first protective layer is deposited in GeSn layers and Ge epi-layer surface, the first protective layer of selective etch forms the
One Ge epitaxial layer window；
(f2) P ion doping is carried out to the first Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the area N-type Ge
Domain, high annealing etch away the first protective layer；
(f3) the second protective layer is deposited in GeSn layers and Ge epi-layer surface, the second protective layer of selective etch forms the
Two Ge epitaxial layer windows；
(f4) B ion doping is carried out to the 2nd Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the area p-type Ge
Domain, high annealing etch away the second protective layer.
In one embodiment of the invention, step (g) includes:
(g1) in the SiO that the region N-type Ge, the region p-type Ge and GeSn layer surface deposition thickness are 150~200nm2Passivation
Layer, the SiO in specified region is fallen with etching technics selective etch2Passivation layer formation metal contact hole；
(g2) using electron beam evaporation process in SiO2Deposition thickness is 150~200nm on passivation layer and metal contact hole
Cr/Au alloy-layer；The Cr/Au alloy-layer that selective eating away specifies region is carved using etching technics, using chemically mechanical polishing
(Chemical Mechanical PolishingCMP) carries out planarization process.
Compared with prior art, the invention has the following advantages:
1) laser that uses of present invention crystallization process again, has the advantages that Ge buffer layer dislocation density is low, can solve Si and serve as a contrast
The problem of on bottom prepared by high quality GeSn epitaxial layer.
2) present invention uses p+- Ge/ direct band gap GeSn/n+The lateral wave conductivity type structure PiN of-Ge, not only device, which shines, imitates
Rate is high, is also beneficial to the integrated of luminescent device and waveguide.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is a kind of preparation method flow chart based on transverse structure LED provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 l is a kind of preparation method process flow diagram based on transverse structure LED of the embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram based on transverse structure LED provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of preparation method flow chart based on transverse structure LED provided in an embodiment of the present invention,
Include:
(a) SOI substrate is chosen；
(b) Ge seed layer, Ge body layer and oxide layer are successively grown in SOI substrate using CVD technique；
(c) the Ge epitaxial layer after crystallization is formed using LRC technique crystallization Ge seed layer and Ge body layer；
(d) dry etch process etching oxidation layer is used；
(e) the Ge epi-layer surface after crystallization grows GeSn layers；
(f) P ion is injected separately into Ge epitaxial layer and B ion forms the region N-type Ge and the region p-type Ge；
(g) Metal contact electrode is made to complete the preparation of transverse structure LED.
Preferably, step (b) may include:
(b1) at a temperature of 275 DEG C~325 DEG C, Ge seed layer is grown on SOI substrate surface using CVD technique；
(b2) at a temperature of 500 DEG C~600 DEG C, Ge body layer is grown in Ge seed crystal surface using CVD technique；
(b3) SiO is deposited in Ge main body layer surface using CVD technique2Form oxide layer.
Preferably, in step (b), Ge seed layer is with a thickness of 40~50nm；Ge body layer is with a thickness of 120~150nm；Oxygen
Change layer with a thickness of 150nm.
Preferably, step (c) includes:
(c1) the entire substrate material including Si substrate, Ge seed layer, Ge body layer and oxide layer is heated to 700 DEG C；
(c2) the Ge epitaxial layer after crystallization is formed using LRC technique crystallization Ge seed layer and Ge body layer；Wherein LRC technique
Optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/
s；
Wherein, LRC technique is that a kind of method of thermal induced phase transition crystallization makes Ge extension on Si substrate by laser heat treatment
Layer fusing recrystallization, laterally discharges the dislocation defects of Ge epitaxial layer, not only reduces the dislocation density and rough surface of Ge material
Degree, and improve Ge/SOI substrate interface quality.
Preferably, step (e) includes:
In H2350 DEG C of temperature are hereinafter, using SnCl in atmosphere4And GeH4Respectively as the source Sn and Ge, in Ge epi-layer surface
Grow undoped direct band gap GeSn layers.
Wherein, in step (e) GeSn layers with a thickness of 250~300nm.
Preferably, step (f) includes:
(f1) the first protective layer is deposited in GeSn layers and Ge epi-layer surface, the first protective layer of selective etch forms the
One Ge epitaxial layer window；
(f2) P ion doping is carried out to the first Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the area N-type Ge
Domain, high annealing etch away the first protective layer；
(f3) the second protective layer is deposited in GeSn layers and Ge epi-layer surface, the second protective layer of selective etch forms the
Two Ge epitaxial layer windows；
(f4) B ion doping is carried out to the 2nd Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the area p-type Ge
Domain, high annealing etch away the second protective layer.
Preferably, step (g) includes:
(g1) in the SiO that the region N-type Ge, the region p-type Ge and GeSn layer surface deposition thickness are 150~200nm2Passivation
Layer, the SiO in specified region is fallen with etching technics selective etch2Passivation layer formation metal contact hole；
(g2) using electron beam evaporation process in SiO2Deposition thickness is 150~200nm on passivation layer and metal contact hole
Cr/Au alloy-layer；The Cr/Au alloy-layer that selective eating away specifies region is carved using etching technics, using chemically mechanical polishing
(CMP) planarization process is carried out.
The present invention uses laser crystallization process again, prepares the low Ge epitaxial layer of dislocation density on soi substrates, and prepare high-quality
Direct band gap GeSn layers of amount, then realizes a kind of p+- Ge/ direct band gap GeSn/n+The transverse structure LED of-Ge and its preparation side
Method.
Embodiment two
A- Fig. 2 l referring to figure 2., Fig. 2 a- Fig. 2 l are another system based on transverse structure LED of the embodiment of the present invention
Preparation Method process flow diagram, the preparation method include the following steps:
S201, substrate are chosen.As shown in Figure 2 a, choosing SOI substrate piece 001 is original material；
The growth of S202, Ge seed layer.As shown in Figure 2 b, at a temperature of 275 DEG C~325 DEG C, using CVD technique epitaxial growth
The Ge seed layer 002 of 40~50nm；
The growth of S203, Ge body layer.As shown in Figure 2 c, at a temperature of 500 DEG C~600 DEG C, using CVD technique in Ge seed
002 surface of crystal layer grows the Ge body layer 003 of 120~150nm；
The preparation of S204, oxide layer.As shown in Figure 2 d, 150nm is deposited on 003 surface of Ge body layer using CVD technique
SiO2Layer oxide layer 004；
S205, such as Fig. 2 e.It will include the entire lining of SOI substrate 001, Ge seed layer 002, Ge body layer 003 and oxide layer
Bottom material is heated to 700 DEG C, continuously uses the entire substrate material of laser technology crystallization, wherein optical maser wavelength 808nm, laser
Spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s, the entire substrate material of natural cooling
Material forms crystallization Ge epitaxial layer.Using the dislocation density and surface roughness for reducing Ge material after laser technology crystallization, improve
Ge/SOI substrate interface quality.Then the SiO in Fig. 2 d is etched using dry etch process2Oxide layer 004.
S206, GeSn layers of selectivity growth are carried out on crystallization Ge epitaxial layer 005.As shown in figure 2f, in H2It will in atmosphere
Temperature drops to 350 DEG C hereinafter, SnCl4And GeH4Respectively as the source Sn and Ge, growth thickness is the undoped straight of 250~300nm
Tape splicing gap GeSn layer 006；
The injection of the region S207, Ge N-type ion.In GeSn layer 006 and 005 surface deposition of Ge epitaxial layer with a thickness of 200nm
SiO2First protective layer 007, selective etch SiO2First protective layer 007, as shown in Figure 2 g；P ion injection, formation 1 ×
1019cm-3The region N-type Ge 008, high annealing etches away SiO2First protective layer 007, as shown in fig. 2h；
The injection of the region S208, Ge P-type ion.As shown in fig. 2i, in 005 surface deposition of GeSn layer 006 and Ge epitaxial layer
With a thickness of the SiO of 200nm2Second protective layer 009, selective etch SiO2Second protective layer 009, B ion implanting form concentration
It is 1 × 1019cm-3The region p-type Ge 010, high annealing etches away SiO2Second protective layer 009, as shown in figure 2j；
S209, metal contact hole preparation.As shown in Fig. 2 k, deposition thickness is the SiO of 150~200nm2Passivation layer 011, every
Destage face and extraneous electrical contact.Contact hole is etched, falls specified SiO with etching technics selective etch2Form metal contact hole.
S210, metal interconnection preparation.As illustrated in figure 21.Use electron beam evaporation deposition thickness for the Cr of 150~200nm or
Au metal layer 012.Cr the or Au metal layer that selective eating away specifies region is carved using etching technics, using chemically mechanical polishing
(CMP) planarization process is carried out.
Embodiment three
Referring to figure 3., Fig. 3 is a kind of structural schematic diagram based on transverse structure LED provided in an embodiment of the present invention.It should
LED is made of the above-mentioned preparation method as shown in Fig. 2 a- Fig. 2 l.Specifically, LED includes: SOI substrate (301), Ge epitaxial layer
(302), GeSn layers (303), the region N-type Ge (304), the region p-type Ge (305), SiO2Passivation layer (306) and metal contact electricity
Pole (307)；
Wherein, Ge epitaxial layer (302) includes Ge seed layer and Ge body layer；Ge seed layer and Ge body layer are used into LRC
Ge epitaxial layer (302) are formed after technique crystallization.
To sum up, specific case used herein is to a kind of principle and embodiment based on transverse structure LED of the present invention
It is expounded, the above description of the embodiment is only used to help understand the method for the present invention and its core ideas；Meanwhile for
Those of ordinary skill in the art have change according to the thought of the present invention in specific embodiments and applications
Place, to sum up, the contents of this specification are not to be construed as limiting the invention, and protection scope of the present invention should be wanted with appended right
Subject to asking.
Claims (9)
1. a kind of preparation method based on transverse structure LED characterized by comprising
(a) SOI substrate is chosen；
(b) Ge seed layer, Ge body layer and oxide layer are successively grown in the SOI substrate using CVD technique；
(c) the Ge epitaxial layer after crystallization is formed using Ge seed layer described in laser again crystallization process crystallization and the Ge body layer；
(d) oxide layer is etched using dry etch process；
(e) the Ge epi-layer surface after crystallization grows GeSn layers；
(f) P ion is injected separately into the Ge epitaxial layer and B ion forms the region N-type Ge and the region p-type Ge；
(g) Metal contact electrode is prepared to complete the preparation of the transverse structure LED.
2. preparation method according to claim 1, which is characterized in that step (b) includes:
(b1) at a temperature of 275 DEG C~325 DEG C, the Ge seed layer is grown on the SOI substrate surface using CVD technique；
(b2) at a temperature of 500 DEG C~600 DEG C, the Ge body layer is grown in the Ge seed crystal surface using CVD technique；
(b3) SiO is deposited in the Ge main body layer surface using CVD technique2Form the oxide layer.
3. preparation method according to claim 1, which is characterized in that in step (b), the Ge seed layer is with a thickness of 40
~50nm；The Ge body layer is with a thickness of 120~150nm；The oxidated layer thickness is 150nm.
4. preparation method according to claim 1, which is characterized in that step (c) includes:
It (c1) will include the entire substrate material of the Si substrate, the Ge seed layer, the Ge body layer and the oxide layer
It is heated to 700 DEG C；
(c2) the Ge epitaxial layer after crystallization is formed using Ge seed layer described in laser again crystallization process crystallization and the Ge body layer；
Wherein crystallization process optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm to laser again2,
Laser traverse speed is 25mm/s.
5. preparation method according to claim 1, which is characterized in that step (e) includes:
In H2350 DEG C of temperature are hereinafter, using SnCl in atmosphere4And GeH4Respectively as the source Sn and the source Ge, in the Ge epitaxial layer table
It looks unfamiliar undoped direct band gap GeSn layers long.
6. preparation method according to claim 1, which is characterized in that GeSn described in step (e) layers with a thickness of 250~
300nm。
7. preparation method according to claim 1, which is characterized in that step (f) includes:
(f1) the first protective layer, the first protection described in selective etch are deposited in described GeSn layers and the Ge epi-layer surface
Layer forms the first Ge epitaxial layer window；
(f2) P ion doping is carried out to the first Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the N-type Ge
Region, high annealing etch away first protective layer；
(f3) the second protective layer, the second protection described in selective etch are deposited in described GeSn layers and the Ge epi-layer surface
Layer forms the 2nd Ge epitaxial layer window；
(f4) B ion doping is carried out to the 2nd Ge epitaxial layer window, doping concentration is 1 × 1019cm-3, form the p-type Ge
Region, high annealing etch away second protective layer.
8. preparation method according to claim 1, which is characterized in that step (g) includes:
It (g1) is 150~200nm's in the region the N-type Ge, the region the p-type Ge and the GeSn layer surface deposition thickness
SiO2Passivation layer falls the SiO in specified region with etching technics selective etch2Passivation layer formation metal contact hole；
(g2) using electron beam evaporation process in the SiO2On passivation layer and the metal contact hole deposition thickness be 150~
The Cr metal layer of 200nm；The Cr metal layer that selective eating away specifies region is carved using etching technics, is thrown using chemical machinery
Light carries out planarization process.
9. one kind is based on transverse structure LED, which is characterized in that the LED is by method system according to any one of claims 1 to 8
It is standby to be formed.
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| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070170536A1 (en) * | 2006-01-25 | 2007-07-26 | Sharp Laboratories Of America, Inc. | Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer |
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|---|---|---|---|---|
| US5548128A (en) * | 1994-12-14 | 1996-08-20 | The United States Of America As Represented By The Secretary Of The Air Force | Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates |
| CN101393944A (en) * | 2007-09-19 | 2009-03-25 | 中国科学院半导体研究所 | Germanium/silicon mixed integrated waveguide type photoelectric converter and manufacturing method thereof |
| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
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