CN107275458A - Light emitting diode based on ledge structure - Google Patents
Light emitting diode based on ledge structure Download PDFInfo
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- CN107275458A CN107275458A CN201710337000.4A CN201710337000A CN107275458A CN 107275458 A CN107275458 A CN 107275458A CN 201710337000 A CN201710337000 A CN 201710337000A CN 107275458 A CN107275458 A CN 107275458A
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- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 238000002425 crystallisation Methods 0.000 claims description 50
- 230000008025 crystallization Effects 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 44
- 239000013078 crystal Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 21
- 238000011282 treatment Methods 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 7
- 241000931526 Acer campestre Species 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 238000005499 laser crystallization Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present invention relates to a kind of light emitting diode (10) based on ledge structure, including：Ge layers of single crystal Si substrate (11) the first (12), is arranged at single crystal Si substrate (11) surface；Ge base stations stage structure (13), is arranged at the center position on the first Ge layers of (12) surface；Positive electrode (14), is arranged at the upper surface of the first Ge layers (12) and at the position of Ge base stations stage structure (13) both sides；Negative electrode (15), is arranged at the upper surface of Ge base stations stage structure (13)；Passivation layer (16), is arranged at the first Ge layers (12) and the upper surface and the centre of positive electrode (14) and Ge base stations stage structure (13) of Ge base stations stage structure (13).Epitaxial ge layer on the light emitting diode of ledge structure of the present invention, Si substrates, prepares high-quality GeSn layers, is greatly enhanced the luminous efficiency of light emitting diode.
Description
Technical field
The invention belongs to technical field of semiconductor device, more particularly to a kind of light emitting diode based on ledge structure.
Background technology
Fiber optic communication be by the use of semiconductor laser (LD) or semiconductor light-emitting-diode (LED) as light source device,
Electric signal is converted to optical signal and is transmitted, and with the development of optical communication technique, speed fiber optic communication systems are to semiconductor light emitting
The requirement of diode also more and more higher, integrated development trend requires that semiconductor LED and other photoelectric devices are integrated.
Luminescent device of good performance is obtained, it is necessary to study the various factors of influence device performance, the material of semiconductor
Characteristic, doping concentration, structure choice, and manufacture craft etc..Generally reduce impurity, lattice defect and the dislocation of semi-conducting material
The luminous efficiency of light emitting diode can be improved.
However, current LED is limited due to preparation technology etc., its luminous efficiency is still that a limitation LED further develops
Major reason.How to improve luminous efficiency just becomes of crucial importance.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of light emitting diode 10 based on ledge structure, wherein,
Including：
Single crystal Si substrate 11；
First Ge layers 12, are arranged at the surface of single crystal Si substrate 11；
Ge base stations stage structure 13, is arranged at the center position on the surface of the first Ge layers 12；
Positive electrode 14, is arranged at the upper surface of the first Ge layers 12 and positioned at the position of the both sides of Ge base stations stage structure 13
Put place；
Negative electrode 15, is arranged at the upper surface of the Ge base stations stage structure 13；
Passivation layer 16, is arranged at upper surface and the positive electricity of the first Ge layers 12 and the Ge base stations stage structure 13
Pole 14 and the centre of the Ge base stations stage structure 13, to form the light emitting diode 10.
In one embodiment of the invention, the first Ge layers 12 include crystallization Ge inculating crystal layers, crystallization Ge body layers and
2nd Ge layers；Wherein, the Ge body layers are arranged at the Ge inculating crystal layers upper surface, the described 2nd Ge layers be arranged at the Ge master
Body layer upper surface.
In one embodiment of the invention, the thickness of the crystallization Ge inculating crystal layers is 40~50nm；The crystallization Ge master
The thickness of body layer is 150~250nm；Described 2nd Ge layers thickness be 400-450nm.
In one embodiment of the invention, the crystallization Ge inculating crystal layers and the crystallization Ge body layers (are swashed by LRC
Light crystallization again) formed after technique Crystallizing treatment.
In one embodiment of the invention, the Crystallizing treatment includes：
The whole substrate material of the single crystal Si substrate 11, the crystallization Ge inculating crystal layers and the crystallization Ge body layers will be included
Material is heated to 700 DEG C；
Using whole backing material described in LRC technique crystallization, wherein, optical maser wavelength is 808nm, laser spot size 10mm
× 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s；
Whole backing material described in natural cooling.
In one embodiment of the invention, the first Ge layers 12 are p-type, and doping concentration is 5 × 1018cm-3。
In one embodiment of the invention, the Ge base stations stage structure 13 includes GeSn layer and the 3rd Ge layers；Wherein,
Described 3rd Ge layers be arranged at the GeSn layers of upper surface.
In one embodiment of the invention, described GeSn layers thickness is 150~200nm.
In one embodiment of the invention, the described 3rd Ge layers be N-type, and thickness is that 40~60nm, doping concentration are 1
×1019cm-3。
In one embodiment of the invention, the positive electrode 14 and the negative electrode 15 are Cr or Au materials, and its
Thickness is 150~200nm.
Compared with prior art, the invention has the advantages that：
1) laser that uses of present invention crystallization process again, high with Ge epitaxial layers crystal mass, processing step is simple, technique
Cycle is short, the low advantage of heat budget；
2) present invention utilizes LRC techniques, Si substrates is become excellent with Ge epitaxial layer interfaces characteristic, with Ge epitaxial layer dislocations
Low density advantage, so as to further improve the luminous efficiency of light emitting diode；
3) present invention is by the empty substrates of continuous laser auxiliary crystallization Ge/Si, and the dislocation that can effectively reduce the empty substrates of Ge/Si is close
Degree and surface roughness, are remarkably improved the quality of follow-up GeSn epitaxial layers, and then be remarkably improved the performance of luminescent device.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment to the present invention is described in detail.
Fig. 1 is a kind of structural representation of light emitting diode provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic flow sheet of Crystallizing treatment technique provided in an embodiment of the present invention；
Fig. 3 is a kind of LRC processes schematic diagram provided in an embodiment of the present invention；
Fig. 4 is the structural representation of another light emitting diode provided in an embodiment of the present invention；
Fig. 5 a- Fig. 5 l illustrate for a kind of preparation technology of light emitting diode based on ledge structure of the embodiment of the present invention
Figure.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of light emitting diode provided in an embodiment of the present invention.This luminous two
Pole pipe 10 includes：
Single crystal Si substrate 11；
First Ge layers 12, are arranged at the surface of single crystal Si substrate 11；
Ge base stations stage structure 13, is arranged at the center position on the surface of the first Ge layers 12；
Positive electrode 14, is arranged at the upper surface of the first Ge layers 12 and positioned at the position of the both sides of Ge base stations stage structure 13
Put place；
Negative electrode 15, is arranged at the upper surface of the Ge base stations stage structure 13；
Passivation layer 16, is arranged at upper surface and the positive electricity of the first Ge layers 12 and the Ge base stations stage structure 13
Pole 14 and the centre of the Ge base stations stage structure 13, to form the light emitting diode 10.
Wherein, the first Ge layers 12 include crystallization Ge inculating crystal layers, crystallization Ge body layers and the 2nd Ge layers；Wherein, it is described
Ge body layers are arranged at the Ge inculating crystal layers upper surface, the described 2nd Ge layers be arranged at the Ge body layers upper surface.
Preferably, the thickness of the crystallization Ge inculating crystal layers is 40~50nm；The thickness of the crystallization Ge body layers be 150~
250nm；Described 2nd Ge layers thickness be 400-450nm.
Wherein, the crystallization Ge inculating crystal layers and the crystallization Ge body layers are formed after LRC technique Crystallizing treatments.
Preferably, Fig. 2 is referred to, Fig. 2 is a kind of schematic flow sheet of Crystallizing treatment technique provided in an embodiment of the present invention.
The Crystallizing treatment includes：
Step 1, by including the whole of the single crystal Si substrate 11, the crystallization Ge inculating crystal layers and the crystallization Ge body layers
Individual backing material is heated to 700 DEG C；
Step 2, using whole backing material described in LRC technique crystallization, wherein, optical maser wavelength is 808nm, laser facula chi
Very little 10mm × 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s；
Whole backing material described in step 3, natural cooling.
Please with further reference to Fig. 3, Fig. 3 is a kind of LRC processes schematic diagram provided in an embodiment of the present invention, LRC techniques
I.e. laser crystallization (Laser Re-Crystallization, abbreviation LRC) technique again, is a kind of method of thermal induced phase transition crystallization,
By laser heat treatment, make the dislocation defects of Ge epitaxial layers fusing recrystallization, laterally release Ge epitaxial layers on Si substrates, not only may be used
High-quality Ge epitaxial layers are obtained, simultaneously as LRC techniques accurately control crystalline areas, common process are on the one hand avoided
Material interface characteristic is good between Si/Ge exclusive problems between middle Si substrates and Ge epitaxial layers, another aspect Si/Ge.
Wherein, the first Ge layers 12 are p-type, and doping concentration is 5 × 1018cm-3。
Wherein, the Ge base stations stage structure 13 includes GeSn layer and the 3rd Ge layers；Wherein, the described 3rd Ge layers be arranged at institute
State GeSn layers of upper surface.
Preferably, described GeSn layers thickness is 150~200nm.
Preferably, the described 3rd Ge layers be N-type, and thickness is that 40~60nm, doping concentration are 1 × 1019cm-3。
Preferably, the positive electrode 14 and the negative electrode 15 are Cr or Au materials, and its thickness is 150~200nm.
The present invention can effectively reduce the dislocation density of the empty substrates of Ge/Si by the empty substrates of continuous laser auxiliary crystallization Ge/Si
And surface roughness, the quality of follow-up GeSn epitaxial layers is remarkably improved, and then be remarkably improved the performance of luminescent device.
Embodiment two
Fig. 4 is referred to, Fig. 4 is the structural representation of another light emitting diode provided in an embodiment of the present invention.This lights
Diode 40 includes single crystal Si substrate 41, p-type crystallization Ge layers 42, undoped GeSn layers 43, N-type Ge layers 44 and metal electrode
45。
Wherein p-type crystallization Ge layers 42 include：Crystallization Ge inculating crystal layers 401, crystallization Ge body layers 402 and the first Ge layers 403.
The embodiment of the present invention, using LRC techniques have solve existing process under the conditions of Ge epitaxial layer qualities it is low the problem of.Together
When, because LRC techniques accurately control crystalline areas, it can effectively reduce the dislocation density, surface roughness, boundary of the empty substrates of Ge
Planar defect, the quality of the empty substrates of lifting Ge is remarkably improved luminescent device so as to obtain higher-quality GeSn epitaxial layers
Performance.
Embodiment three
It refer to a kind of light emitting diode based on ledge structure that Fig. 5 a- Fig. 5 l, Fig. 5 a- Fig. 5 l are the embodiment of the present invention
Preparation technology schematic diagram, the preparation method comprises the following steps：
S101, selection single crystal Si substrate 001, as shown in Figure 5 a；
S102, at a temperature of 275 DEG C~325 DEG C, 50nm Ge seeds are grown on single crystal Si substrate 001 using CVD techniques
Crystal layer 002, as shown in Figure 5 b；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the superficial growth 200nm of Ge inculating crystal layers 002 Ge master
Body layer 003, as shown in Figure 5 c；
S104, using CVD techniques 120nm SiO are deposited on the surface of Ge body layers 0032Layer 004, as fig 5d；
S105, single crystal Si substrate 001, Ge inculating crystal layers 002, Ge body layers 003 and SiO will be included2The whole substrate of layer 004
Material is heated to 700 DEG C, continuous to use LRC technique crystallization
Whole backing material, wherein optical maser wavelength are 808nm, laser spot size 10mm × 1mm, and laser power is
1.5kW/cm2, laser traverse speed is 25mm/s, the whole backing material of natural cooling；
S106, utilize dry etch process etching SiO2Layer 004, obtains the layers of the Ge after laser crystallization 005, wherein, Ge layers
005 represents the general designation of the Ge inculating crystal layers 002 after laser crystallization and Ge body layers 003, as depicted in fig. 5e；
S107, at 300-400 DEG C of temperature, grown using CVD techniques on the Ge layers 005 after LRC technique crystallization
Ge layers 006 thick 450nm, as shown in figure 5f.
S108, using ion implantation technology the Ge layers 005 after Ge layers 006 and LRC technique crystallization are doped, adulterated
Concentration is 5 × 1018cm-3, p-type crystallization Ge layers 007 are formed (for the ease of diagram viewing, by the Ge layers 005 and crystalline substance after crystallization
007) the Ge layers 006 grown after change are collectively referred to as Ge layers of p-type crystallization, are annealed afterwards, as shown in fig. 5g；
S109, in H2Less than 350 DEG C, SnCl are reduced the temperature in atmosphere4And GeH4Respectively as Sn and Ge sources, Sn groups are mixed
Divide and reach 8%.Grow the thick undoped Ge of 200nm0.92Sn0.08Layer 008, as shown in figure 5h；
At S110, followed by preceding identical temperature, continue to deposit Ge layers.P doping concentrations are 1 × 1019cm-3.Use N2It is used as delivery
Gas can improve growth rate, 1% PH3It is used as P doped sources.The thick N-type Ge Rotating fields 009 of 50nm are grown, such as Fig. 5 i institutes
Show；
S112, at room temperature, uses HCl:H2O2:H2O=1:1:20 chemical solvent, is entered with steady rate 100nm/min
Row mesa etch, etching it is deep-controlled in 500nm, expose p-type crystallization Ge layers 007 and do metal contact, as shown in figure 5j；
S111, utilize plasma enhanced CVD technique, SiO thick deposit 150nm2Passivation layer 010, isolation
Table top is made electrical contact with extraneous, and the SiO of designated area is fallen with etching technics selective etch2Contact hole is formed, as shown in figure 5k；
S112, using electron beam evaporation depositing technics, thick 150nm Cr or Au layers 011 utilize etching technics to carve selectively
The metal Cr or Au of eating away designated area, carry out planarization process, as shown in Fig. 5 l using chemically mechanical polishing (CMP).
Example IV
Continue referring to Fig. 5 a- Fig. 5 l, Fig. 5 a- Fig. 5 l for the embodiment of the present invention it is a kind of based on ledge structure luminous two
The preparation technology schematic diagram of pole pipe, the preparation method also comprises the following steps：
S101, selection single crystal Si substrate 001, as shown in Figure 5 a；
S102, at a temperature of 275 DEG C~325 DEG C, grow 40~50nm's on single crystal Si substrate 001 using CVD techniques
Ge inculating crystal layers 002, as shown in Figure 5 b；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the 150~250nm of superficial growth of Ge inculating crystal layers 002
Ge body layers 003, as shown in Figure 5 c；
S104, using CVD techniques 100~150nm SiO are deposited on the surface of Ge body layers 0032Layer 004, such as Fig. 5 d institutes
Show；
S105, single crystal Si substrate 001, Ge inculating crystal layers 002, Ge body layers 003 and SiO will be included2The whole substrate of layer 004
Material is heated to 700 DEG C, and continuous to use the whole backing material of LRC technique crystallization, wherein optical maser wavelength is 808nm, laser facula
Size 10mm × 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s, the whole backing material of natural cooling；
S106, utilize dry etch process etching SiO2Layer 004, the Ge layers 005 formed after laser crystallization, wherein, Ge layers
005 represents the general designation of the Ge inculating crystal layers 002 after laser crystallization and Ge body layers 003, as depicted in fig. 5e；
S107, at 300-400 DEG C of temperature, grow 400- on the Ge layers 005 after LRC technique crystallization using CVD techniques
Ge layers 006 thick 450nm, as shown in figure 5f.
S108, using ion implantation technology the Ge layers 005 after Ge layers 006 and LRC technique crystallization are doped, adulterated
Concentration is 5 × 1018cm-3, p-type crystallization Ge layers 007 are formed (for the ease of diagram viewing, by the Ge layers 005 and crystalline substance after crystallization
007) the Ge layers 006 grown after change are collectively referred to as Ge layers of p-type crystallization, are annealed afterwards, as shown in fig. 5g；
S109, in H2Less than 350 DEG C, SnCl are reduced the temperature in atmosphere4And GeH4Respectively as Sn and Ge sources, Sn groups are mixed
Divide and reach 8%.Grow the thick undoped Ge of 150~200nm0.92Sn0.08Layer 008, as shown in figure 5h；
At S110, followed by preceding identical temperature, continue to deposit Ge layers.P doping concentrations are 1 × 1019cm-3.Use N2It is used as delivery
Gas can improve growth rate, 1% PH3It is used as P doped sources.The thick N-type Ge Rotating fields 009 of 40~60nm are grown, are such as schemed
Shown in 5i；
S112, at room temperature, uses HCl:H2O2:H2O=1:1:20 chemical solvent, is entered with steady rate 100nm/min
Row mesa etch, etching it is deep-controlled in 500nm, expose p-type crystallization Ge layers 007 and do metal contact, as shown in figure 5j；
S111, using plasma enhancing chemical vapor deposition techniques, SiO thick 150~200nm of deposit2Passivation layer
010, isolation table top is made electrical contact with extraneous, and the SiO of designated area is fallen with etching technics selective etch2Contact hole is formed, is such as schemed
Shown in 5k；
S112, using electron beam evaporation process, thick 150~200nm of deposit Cr or Au layers 011 are carved using etching technics
The metal Cr or Au of selective eating away designated area, carry out planarization process, such as Fig. 5 l institutes using chemically mechanical polishing (CMP)
Show.
To sum up, specific case used herein LED based on ledge structure a kind of to present invention structure and embodiment party
Formula is set forth, and the explanation of above example is only intended to the method and its core concept for helping to understand the present invention；Meanwhile, it is right
In those of ordinary skill in the art, according to the thought of the present invention, change is had in specific embodiments and applications
Part, to sum up, this specification content should not be construed as limiting the invention, and protection scope of the present invention should be with appended right
It is required that being defined.
Claims (10)
1. a kind of light emitting diode (10) based on ledge structure, it is characterised in that including：
Single crystal Si substrate (11)；
First Ge layers (12), are arranged at the single crystal Si substrate (11) surface；
Ge base stations stage structure (13), is arranged at the center position on the described first Ge layers of (12) surface；
Positive electrode (14), is arranged at the upper surface of the described first Ge layers (12) and positioned at Ge base stations stage structure (13) both sides
At position；
Negative electrode (15), is arranged at the upper surface of the Ge base stations stage structure (13)；
Passivation layer (16), be arranged at the described first Ge layers (12) and the Ge base stations stage structure (13) upper surface and it is described just
Electrode (14) and the centre of the Ge base stations stage structure (13), to form the light emitting diode (10).
2. light emitting diode (10) according to claim 1, it is characterised in that the described first Ge layers (12) include crystallization Ge
Inculating crystal layer, crystallization Ge body layers and the 2nd Ge layers；Wherein, the Ge body layers are arranged at the Ge inculating crystal layers upper surface, described
2nd Ge layers be arranged at the Ge body layers upper surface.
3. light emitting diode (10) according to claim 2, it is characterised in that the thickness of the crystallization Ge inculating crystal layers is 40
~50nm；The thickness of the crystallization Ge body layers is 150~250nm；Described 2nd Ge layers thickness be 400-450nm.
4. light emitting diode (10) according to claim 3, it is characterised in that the crystallization Ge inculating crystal layers and the crystallization
Ge body layers are formed after LRC technique Crystallizing treatments.
5. light emitting diode (10) according to claim 4, it is characterised in that the Crystallizing treatment includes：
The whole backing material of the single crystal Si substrate (11), the crystallization Ge inculating crystal layers and the crystallization Ge body layers will be included
It is heated to 700 DEG C；
Using whole backing material described in LRC technique crystallization, wherein, optical maser wavelength is 808nm, laser spot size 10mm ×
1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s；
Whole backing material described in natural cooling.
6. light emitting diode (10) according to claim 1, it is characterised in that the described first Ge layers (12) are p-type, and are mixed
Miscellaneous concentration is 5 × 1018cm-3。
7. light emitting diode (10) according to claim 1, it is characterised in that the Ge base stations stage structure (13) includes
GeSn layers and the 3rd Ge layers；Wherein, the described 3rd Ge layers be arranged at the GeSn layers of upper surface.
8. light emitting diode (10) according to claim 7, it is characterised in that described GeSn layers thickness is 150~
200nm。
9. light emitting diode (10) according to claim 7, it is characterised in that the described 3rd Ge layers be N-type, and thickness is
40~60nm, doping concentration are 1 × 1019cm-3。
10. light emitting diode (10) according to claim 1, it is characterised in that the positive electrode (14) and the negative electricity
Pole (15) is Cr or Au materials, and its thickness is 150~200nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710337000.4A CN107275458A (en) | 2017-05-17 | 2017-05-17 | Light emitting diode based on ledge structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710337000.4A CN107275458A (en) | 2017-05-17 | 2017-05-17 | Light emitting diode based on ledge structure |
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| Publication Number | Publication Date |
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| CN107275458A true CN107275458A (en) | 2017-10-20 |
Family
ID=60073756
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|---|---|---|---|
| CN201710337000.4A Pending CN107275458A (en) | 2017-05-17 | 2017-05-17 | Light emitting diode based on ledge structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150129911A1 (en) * | 2013-11-08 | 2015-05-14 | Wisconsin Alumni Research Foundation | Strain tunable light emitting diodes with germanium p-i-n heterojunctions |
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
| CN207021280U (en) * | 2017-05-17 | 2018-02-16 | 西藏民族大学 | Light emitting diode based on ledge structure |
-
2017
- 2017-05-17 CN CN201710337000.4A patent/CN107275458A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
| US20150129911A1 (en) * | 2013-11-08 | 2015-05-14 | Wisconsin Alumni Research Foundation | Strain tunable light emitting diodes with germanium p-i-n heterojunctions |
| CN207021280U (en) * | 2017-05-17 | 2018-02-16 | 西藏民族大学 | Light emitting diode based on ledge structure |
Non-Patent Citations (2)
| Title |
|---|
| ERICH KASPER AND MICHAEL OEHME: ""Germanium tin light emitters on silicon"", 《JAPANESE JOURNAL OF APPLIED PHYSICS》 * |
| 黄志伟 等: ""激光退火改善Si上外延Ge晶体质量"", 《第十一届全国硅基光电子材料及器件研讨会论文摘要集》 * |
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Application publication date: 20171020 |