CN207021280U - Light emitting diode based on ledge structure - Google Patents

Light emitting diode based on ledge structure Download PDF

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Publication number
CN207021280U
CN207021280U CN201720544312.8U CN201720544312U CN207021280U CN 207021280 U CN207021280 U CN 207021280U CN 201720544312 U CN201720544312 U CN 201720544312U CN 207021280 U CN207021280 U CN 207021280U
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layers
light emitting
emitting diode
base stations
utility
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CN201720544312.8U
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乔丽萍
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Xizang Minzu University
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Xizang Minzu University
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Abstract

A kind of light emitting diode 10 based on ledge structure is the utility model is related to, including：The Ge layers 12 of single crystal Si substrate 11 the oneth, it is arranged at the surface of single crystal Si substrate 11；Ge base stations stage structure 13, it is arranged at the center position on the surface of the first Ge layers 12；Positive electrode 14, it is arranged at the upper surface of the first Ge layers 12 and positioned at the opening position of the both sides of ledge structure 13；Negative electrode 15, it is arranged at the upper surface of ledge structure 13；Passivation layer 16, the upper surface and the centre of positive electrode (14) and Ge base stations stage structure (13) of the first Ge layers (12) and Ge base stations stage structure (13) are arranged at, to form light emitting diode 10.The light emitting diode of the utility model ledge structure, epitaxial ge layer on Si substrates, prepares high quality GeSn layers, is greatly enhanced the luminous efficiency of light emitting diode.

Description

Light emitting diode based on ledge structure
Technical field
The utility model category technical field of semiconductor device, more particularly to a kind of light emitting diode based on ledge structure.
Background technology
Fiber optic communication be by the use of semiconductor laser (LD) or semiconductor light-emitting-diode (LED) as light source device, Electric signal is converted to optical signal and is transmitted, and with the development of optical communication technique, speed fiber optic communication systems are to semiconductor light emitting Also more and more higher, integrated development trend require that semiconductor LED integrates with other photoelectric devices for the requirement of diode.
With being bonded skill between the technology such as extension III-V material and iii-v luminous tube and Si on a si substrate The fast development of art, the iii-v mixing laser that Si bases are bonded extension on photophore and Si substrates also succeed in succession.Mesh For preceding LED because preparation technology etc. limits, its luminous efficiency is still the major reason that a limitation LED further develops.How Improving luminous efficiency just becomes of crucial importance.
Utility model content
In order to solve the above-mentioned technical problem, the utility model provides a kind of light emitting diode 10 based on ledge structure, Wherein, including：
Single crystal Si substrate 11；
First Ge layers 12, it is arranged at the surface of single crystal Si substrate 11；
Ge base stations stage structure 13, it is arranged at the center position on the surface of the first Ge layers 12；
Positive electrode 14, it is arranged at the upper surface of the first Ge layers 12 and positioned at the opening position of ledge structure (13) both sides；
Negative electrode 15, it is arranged at the upper surface of the ledge structure 13；
Passivation layer 16, it is arranged at the upper surface of the first Ge layers (12) and the Ge base stations stage structure (13) and described Positive electrode (14) and the centre of the Ge base stations stage structure (13), to form the light emitting diode 10.
In one embodiment of the present utility model, the first Ge layers 12 include Ge inculating crystal layers, Ge body layers and second Ge layers；Wherein, the Ge body layers are arranged at the Ge inculating crystal layers upper surface, and the 2nd Ge layers are arranged at the Ge body layers Upper surface.
In one embodiment of the present utility model, the thickness of the Ge inculating crystal layers is 40~50nm；The Ge body layers Thickness be 150~250nm；The thickness of the 2nd Ge layers is 400-450nm.
In one embodiment of the present utility model, the Ge base stations stage structure 13 includes GeSn layers and the 3rd Ge layers；Its In, the 3rd Ge layers are arranged at the GeSn layers upper surface.
In one embodiment of the present utility model, the thickness of the GeSn layers is 150~200nm.
In one embodiment of the present utility model, the thickness of the 3rd Ge layers is 40~60nm.
Compared with prior art, the utility model has the advantages that：
1) light emitting diode of the utility model ledge structure, epitaxial ge layer on Si substrates, prepares high quality GeSn layers；
2) the utility model realizes the preparation of longitudinal P IN GeSn luminous tubes in Ge/Si void substrates, so as to further improve The luminous efficiency of light emitting diode.
Brief description of the drawings
Below in conjunction with accompanying drawing, specific embodiment of the present utility model is described in detail.
Fig. 1 is a kind of structural representation for light emitting diode based on ledge structure that the utility model embodiment provides；
Fig. 2 is a kind of schematic flow sheet for Crystallizing treatment technique that the utility model embodiment provides；
Fig. 3 is a kind of LRC processes schematic diagram that the utility model embodiment provides；
Fig. 4 is the structural representation for another light emitting diode based on ledge structure that the utility model embodiment provides Figure；
Fig. 5 a- Fig. 5 l are that a kind of preparation technology of light emitting diode based on ledge structure of the utility model embodiment shows It is intended to.
Embodiment
Further detailed description, but embodiment party of the present utility model are to the utility model with reference to specific embodiment Formula not limited to this.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation for light emitting diode that the utility model embodiment provides.The hair Optical diode 10 includes：
Single crystal Si substrate 11；
First Ge layers 12, it is arranged at the surface of single crystal Si substrate 11；
Ge base stations stage structure 13, it is arranged at the center position on the surface of the first Ge layers 12；
Positive electrode 14, it is arranged at the upper surface of the first Ge layers 12 and positioned at the opening position of the both sides of ledge structure 13；
Negative electrode 15, it is arranged at the upper surface of the ledge structure 13；
Passivation layer 16, it is arranged at the upper surface of the first Ge layers (12) and the Ge base stations stage structure (13) and described Positive electrode (14) and the centre of the Ge base stations stage structure (13), to form the light emitting diode 10.
Wherein, the first Ge layers 12 include crystallization Ge inculating crystal layers, crystallization Ge body layers and the 2nd Ge layers；Wherein, it is described Ge body layers are arranged at the Ge inculating crystal layers upper surface, and the 2nd Ge layers are arranged at the Ge body layers upper surface.
Preferably, the thickness of the Ge inculating crystal layers is 40~50nm；The thickness of the Ge body layers is 150~250nm； The thickness of the 2nd Ge layers is 400-450nm.
Wherein, the crystallization Ge inculating crystal layers and the crystallization Ge body layers are formed after LRC technique Crystallizing treatments.
Preferably, Fig. 2 is referred to, Fig. 2 is that a kind of flow for Crystallizing treatment technique that the utility model embodiment provides is shown It is intended to.The Crystallizing treatment includes：
Step 1, the whole backing material that the single crystal Si substrate 11, the Ge inculating crystal layers and the Ge body layers will be included It is heated to 700 DEG C；
Step 2, using whole backing material described in LRC technique crystallization, wherein, optical maser wavelength 808nm, laser facula chi Very little 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
Whole backing material described in step 3, natural cooling.
A kind of LRC processes schematic diagram please provided with further reference to Fig. 3, Fig. 3 for the utility model embodiment, LRC Technique is that crystallization (Laser Re-Crystallization, abbreviation LRC) technique is a kind of side of thermal induced phase transition crystallization to laser again Method, by laser heat treatment, make Ge epitaxial layers fusing recrystallization on Si substrates, laterally discharge the dislocation defects of Ge epitaxial layers, no The Ge epitaxial layers of high quality can be only obtained, simultaneously as LRC techniques accurately control crystalline areas, on the one hand avoid routine Si, Ge exclusive problem in technique between Si substrates and Ge epitaxial layers, material interface characteristic is good between another aspect Si/Ge.
Wherein, the first Ge layers 12 are p-type, and doping concentration is 5 × 1018cm-3。
Wherein, the Ge base stations stage structure 13 includes GeSn layers and the 3rd Ge layers；Wherein, the 3rd Ge layers are arranged at institute State GeSn layers upper surface.
Preferably, the thickness of the GeSn layers is 150~200nm.
Preferably, the 3rd Ge layers are N-type, and thickness is 40~60nm, doping concentration is 1 × 1019cm-3。
Preferably, the positive electrode 14 and the negative electrode 15 are Cr or Au materials, and its thickness is 150~200nm.
The utility model can effectively reduce the dislocation of Ge/Si void substrates by continuous laser auxiliary crystallization Ge/Si void substrates Density and surface roughness, are remarkably improved the quality of follow-up GeSn epitaxial layers, and then are remarkably improved the performance of luminescent device.
Embodiment two
Fig. 4 is referred to, Fig. 4 is the structural representation for another light emitting diode that the utility model embodiment provides.Should Light emitting diode 40 includes single crystal Si substrate 41, p-type crystallization Ge layers 42, undoped GeSn layers 43, N-type Ge layers 44 and metal electricity Pole 45.
Wherein p-type crystallization Ge layers 42 include：Crystallization Ge inculating crystal layers 401, crystallization Ge body layers 402 and the first Ge layers 403.
The utility model embodiment, have using LRC techniques and solve under the conditions of existing process that Ge epitaxial layer qualities are low asks Topic.Simultaneously as LRC techniques accurately control crystalline areas, dislocation density, the rough surface of Ge void substrates can be effectively reduced Degree, boundary defect, the quality of Ge void substrates is lifted so as to obtain higher-quality GeSn epitaxial layers, and then be remarkably improved luminous The performance of device.
Embodiment three
Refer to Fig. 5 a- Fig. 5 l, Fig. 5 a- Fig. 5 l be the utility model embodiment it is a kind of based on ledge structure luminous two The preparation technology schematic diagram of pole pipe, the preparation method comprise the following steps：
S101, single crystal Si substrate 001 is chosen, as shown in Figure 5 a；
S102, at a temperature of 275 DEG C~325 DEG C, 50nm Ge seeds are grown on single crystal Si substrate 001 using CVD techniques Crystal layer 002, as shown in Figure 5 b；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the superficial growth 200nm of Ge inculating crystal layers 002 Ge master Body layer 003, as shown in Figure 5 c；
S104, using CVD techniques 120nm SiO are deposited on the surface of Ge body layers 0032Layer 004, as fig 5d；
S105, single crystal Si substrate 001, Ge inculating crystal layers 002, Ge body layers 003 and SiO will be included2The whole substrate of layer 004 Material is heated to 700 DEG C, continuous to use the whole backing material of LRC technique crystallization, and wherein optical maser wavelength is 808nm, laser facula Size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s, the whole backing material of natural cooling；
S106, utilize dry etch process etching SiO2Layer 004, obtains the Ge layers 005 after laser crystallization, wherein, Ge layers 005 represents the general designation of the Ge inculating crystal layers 002 after laser crystallization and Ge body layers 003, as depicted in fig. 5e；
S107, at 300-400 DEG C of temperature, grown using CVD techniques on the Ge layers 005 after LRC technique crystallization Ge layers 006 thick 450nm, as shown in figure 5f；
S108, using ion implantation technology the Ge layers 005 after Ge layers 006 and LRC technique crystallization are doped, adulterated Concentration is 5 × 1018cm-3, form p-type crystallization Ge layers 007 and (watched for the ease of diagram, by the Ge layers 005 and crystalline substance after crystallization The Ge layers 006 grown after change are collectively referred to as p-type crystallization Ge layers 007), annealed afterwards, as shown in fig. 5g；
S109, in H2Less than 350 DEG C are reduced the temperature in atmosphere, SnCl4And GeH4Respectively as Sn and Ge sources, Sn groups are mixed Divide and reach 8%.Grow the thick undoped Ge of 200nm0.92Sn0.08Layer 008, as shown in figure 5h；
At S110, followed by preceding identical temperature, continue to deposit Ge layers.P doping concentrations are 1 × 1019cm-3.Use N2As delivery Gas can improve growth rate, 1% PH3As P doped sources.The thick N-type Ge Rotating fields 009 of 50nm are grown, such as Fig. 5 i institutes Show；
S112, at room temperature, uses HCl:H2O2:H2O=1:1:20 chemical solvent, entered with steady rate 100nm/min Row mesa etch, etching it is deep-controlled in 500nm, expose p-type crystallization Ge layers 007 and do metal contact, as shown in figure 5j；
S111, utilize plasma enhanced CVD technique, SiO thick deposit 150nm2Passivation layer 010, isolation Table top and the extraneous SiO for making electrical contact with, designated area being fallen with etching technics selective etch2Contact hole is formed, as shown in figure 5k；
S112, using electron beam evaporation depositing technics, Cr or Au layers 011 thick 150nm, utilize etching technics to carve selectivity The metal Cr or Au of eating away designated area, planarization process is carried out using chemically mechanical polishing (CMP), as shown in Fig. 5 l.
Example IV
Continue referring to a kind of hair based on ledge structure that Fig. 5 a- Fig. 5 l, Fig. 5 a- Fig. 5 l are the utility model embodiment The preparation technology schematic diagram of optical diode, the preparation method also comprise the following steps：
S101, single crystal Si substrate 001 is chosen, as shown in Figure 5 a；
S102, at a temperature of 275 DEG C~325 DEG C, grow 40~50nm's on single crystal Si substrate 001 using CVD techniques Ge inculating crystal layers 002, as shown in Figure 5 b；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the 150~250nm of superficial growth of Ge inculating crystal layers 002 Ge body layers 003, as shown in Figure 5 c；
S104, using CVD techniques 100~150nm SiO are deposited on the surface of Ge body layers 0032Layer 004, such as Fig. 5 d institutes Show；
S105, single crystal Si substrate 001, Ge inculating crystal layers 002, Ge body layers 003 and SiO will be included2The whole substrate of layer 004 Material is heated to 700 DEG C, continuous to use the whole backing material of LRC technique crystallization, and wherein optical maser wavelength is 808nm, laser facula Size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s, the whole backing material of natural cooling；
S106, utilize dry etch process etching SiO2Layer 004, the Ge layers 005 formed after laser crystallization, wherein, Ge layers 005 represents the general designation of the Ge inculating crystal layers 002 after laser crystallization and Ge body layers 003, as depicted in fig. 5e；
S107, at 300-400 DEG C of temperature, grow 400- on the Ge layers 005 after LRC technique crystallization using CVD techniques Ge layers 006 thick 450nm, as shown in figure 5f；
S108, using ion implantation technology the Ge layers 005 after Ge layers 006 and LRC technique crystallization are doped, adulterated Concentration is 5 × 1018cm-3, form p-type crystallization Ge layers 007 and (watched for the ease of diagram, by the Ge layers 005 and crystalline substance after crystallization The Ge layers 006 grown after change are collectively referred to as p-type crystallization Ge layers 007), annealed afterwards, as shown in fig. 5g；
S109, in H2Less than 350 DEG C are reduced the temperature in atmosphere, SnCl4And GeH4Respectively as Sn and Ge sources, Sn groups are mixed Divide and reach 8%.Grow the thick undoped Ge of 150~200nm0.92Sn0.08Layer 008, as shown in figure 5h；
At S110, followed by preceding identical temperature, continue to deposit Ge layers.P doping concentrations are 1 × 1019cm-3.Use N2As delivery Gas can improve growth rate, 1% PH3As P doped sources.The thick N-type Ge Rotating fields 009 of 40~60nm are grown, are such as schemed Shown in 5i；
S112, at room temperature, uses HCl:H2O2:H2O=1:1:20 chemical solvent, entered with steady rate 100nm/min Row mesa etch, etching it is deep-controlled in 500nm, expose p-type crystallization Ge layers 007 and do metal contact, as shown in figure 5j；
S111, using plasma enhancing chemical vapor deposition techniques, SiO thick 150~200nm of deposit2Passivation layer 010, isolation table top is made electrical contact with the external world, and the SiO of designated area is fallen with etching technics selective etch2Contact hole is formed, is such as schemed Shown in 5k；
S112, using electron beam evaporation process, Cr or Au layers 011 thick 150~200nm of deposit, carved using etching technics The metal Cr or Au of selective eating away designated area, planarization process is carried out using chemically mechanical polishing (CMP), such as Fig. 5 l institutes Show.
To sum up, specific case LED based on ledge structure a kind of to the utility model structure and reality used herein The mode of applying is set forth, and the explanation of above example is only intended to help and understands that method and its core of the present utility model are thought Think；Meanwhile for those of ordinary skill in the art, according to thought of the present utility model, in embodiment and using model There will be changes are placed, to sum up, this specification content should not be construed as to limitation of the present utility model, of the present utility model Protection domain should be defined by appended claim.

Claims (6)

  1. A kind of 1. light emitting diode (10) based on ledge structure, it is characterised in that including：
    Single crystal Si substrate (11)；
    First Ge layers (12), it is arranged at the single crystal Si substrate (11) upper surface；
    Ge base stations stage structure (13), it is arranged at the center position of the first Ge layers (12) upper surface；
    Positive electrode (14), it is arranged at the upper surface of the first Ge layers (12) and positioned at Ge base stations stage structure (13) both sides Opening position；
    Negative electrode (15), it is arranged at the upper surface of the Ge base stations stage structure (13)；
    Passivation layer (16), be arranged at the first Ge layers (12) and the Ge base stations stage structure (13) upper surface and it is described just Electrode (14) and the centre of the Ge base stations stage structure (13), to form the light emitting diode (10).
  2. 2. light emitting diode (10) according to claim 1, it is characterised in that the first Ge layers (12) include Ge seed crystals Layer, Ge body layers and the 2nd Ge layers；Wherein, the Ge body layers are arranged at the Ge inculating crystal layers upper surface, the 2nd Ge layers It is arranged at the Ge body layers upper surface.
  3. 3. light emitting diode (10) according to claim 2, it is characterised in that the thickness of the Ge inculating crystal layers be 40~ 50nm；The thickness of the Ge body layers is 150~250nm；The thickness of the 2nd Ge layers is 400-450nm.
  4. 4. light emitting diode (10) according to claim 1, it is characterised in that the Ge base stations stage structure (13) includes GeSn layers and the 3rd Ge layers；Wherein, the 3rd Ge layers are arranged at the GeSn layers upper surface.
  5. 5. light emitting diode (10) according to claim 4, it is characterised in that the thickness of the GeSn layers be 150~ 200nm。
  6. 6. light emitting diode (10) according to claim 4, it is characterised in that the thickness of the 3rd Ge layers be 40~ 60nm。
CN201720544312.8U 2017-05-17 2017-05-17 Light emitting diode based on ledge structure Expired - Fee Related CN207021280U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275458A (en) * 2017-05-17 2017-10-20 西安科锐盛创新科技有限公司 Light emitting diode based on ledge structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275458A (en) * 2017-05-17 2017-10-20 西安科锐盛创新科技有限公司 Light emitting diode based on ledge structure

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Granted publication date: 20180216

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