CN107170859A - Based on transversary light emitting diode - Google Patents
Based on transversary light emitting diode Download PDFInfo
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- CN107170859A CN107170859A CN201710347695.4A CN201710347695A CN107170859A CN 107170859 A CN107170859 A CN 107170859A CN 201710347695 A CN201710347695 A CN 201710347695A CN 107170859 A CN107170859 A CN 107170859A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
- H01L33/0012—Devices characterised by their operation having p-n or hi-lo junctions p-i-n devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/34—Materials of the light emitting region containing only elements of group IV of the periodic system
Abstract
Transversary light emitting diode is based on the present invention relates to one kind, including：SOI substrate；Ge epitaxial layers, are arranged at the upper surface of SOI substrate；GeSn layers, it is arranged at the middle position of the upper surface of Ge epitaxial layers；N-type Ge regions, are adulterated by Ge epitaxial layers and are formed, positioned at GeSn layers of side；P-type Ge regions, are adulterated by Ge epitaxial layers and are formed, positioned at GeSn layers of opposite side；P-type Ge regions, GeSn layers and N-type Ge regions form the horizontal PiN structures of ridged：Positive electrode, is arranged at the upper surface in p-type Ge regions；Negative electrode, is arranged at the upper surface in N-type Ge regions, and transversary light emitting diode is based on to be formed.The present invention provide based on transversary light emitting diode, using the low advantage of Ge epitaxial layer dislocation densities, utilize p+Ge/ direct band gaps GeSn/n+Ge transversary light emitting diode, is greatly enhanced the luminous efficiency of light emitting diode.
Description
Technical field
It is more particularly to a kind of to be based on transversary light emitting diode the invention belongs to technical field of semiconductor device preparation.
Background technology
In recent years, with the development of optical communication technique, speed fiber optic communication systems are to semiconductor light-emitting-diode (Light-
Emitting Diode, abbreviation LED) also more and more higher is required, integrated development trend requires semiconductor LED and other photoelectricity
Device is integrated.If can be integrated on a single die by them, information transfer rate, storage and disposal ability will be carried significantly
Height, this will make Information Technology Development to a brand-new stage.Therefore, to the research of luminescent device, it has also become in current area
The focus and emphasis of research.
It is compatible that traditional longitudinal P iN structure light-emitting devices are unsuitable for waveguide.If considering luminescent device and waveguide in optical interconnection
It is integrated, the i areas of horizontal PiN luminescent devices are not only the light-emitting zone of device, are also the waveguide section of optical transport.Therefore, design
It will be one of integrated important directions of following photoelectricity to manufacture lateral wave conductivity type LED.
However, current transverse direction LED is limited due to preparation technology etc., its luminous efficiency is still a limitation LED further
The major reason of development.Therefore how to improve luminous efficiency just becomes of crucial importance.
The content of the invention
In order to solve the above-mentioned technical problem, transversary light emitting diode 1 is based on the invention provides one kind, including：
SOI substrate 11；
Ge epitaxial layers 12, are arranged at the upper surface of SOI substrate 11；
GeSn layers 13, are arranged at the middle position of the upper surface of Ge epitaxial layers 12；
N-type Ge regions 14, are adulterated by Ge epitaxial layers 12 and are formed, positioned at the side of GeSn layers 13；
P-type Ge regions 15, are adulterated by Ge epitaxial layers 12 and are formed, positioned at the opposite side of GeSn layers 13；
P-type Ge regions 15, GeSn layers 13 and N-type Ge regions 14 form the horizontal PiN structures of ridged：
Positive electrode 16, is arranged at the upper surface in p-type Ge regions 15；
Negative electrode 17, is arranged at the upper surface in N-type Ge regions 14, and transversary light emitting diode 1 is based on to be formed.
In one embodiment of the invention, Ge epitaxial layers 12 include Ge inculating crystal layers and Ge body layers；By Ge inculating crystal layers and
Ge body layers form Ge epitaxial layers 12 after Crystallizing treatment.
In one embodiment of the invention, Crystallizing treatment comprises the following steps：
Whole backing material including SOI substrate 11, Ge inculating crystal layers, Ge body layers is heated to 700 DEG C；
Using laser crystallization (Laser re-crystallization, abbreviation LRC) the whole backing material of technique crystallization again；
Wherein LRC techniques optical maser wavelength is 808nm, laser spot size 10mm × 1mm, and laser power is 1.5kW/cm2, laser movement
Speed is 25mm/s；
High-temperature thermal annealing processing is carried out to whole backing material to complete Crystallizing treatment.
In one embodiment of the invention, Ge inculating crystal layers thickness is 40~50nm；Ge body layers thickness be 120~
150nm。
In one embodiment of the invention, the thickness of GeSn layers 13 is 250~300nm.
In one embodiment of the invention, N-type Ge region dopings source is P ion, and doping concentration is 1 × 1019cm-3。
In one embodiment of the invention, p-type Ge region dopings source is B ions, and doping concentration is 1 × 1019cm-3。
In one embodiment of the invention, in addition to passivation layer, passivation layer is arranged at the upper surface of PiN structures, is used for
Isolate positive electrode 16 and negative electrode 17.
In one embodiment of the invention, passivation layer is SiO2Material, and its thickness is 150~200nm.
In one embodiment of the invention, positive electrode 16 and negative electrode 17 are Cr or Au materials, and its thickness is 150
~200nm.
Explanation is needed, it is emphasized that LRC techniques are a kind of methods of thermal induced phase transition crystallization, by laser heat treatment, makes SOI
The dislocation defects of Ge epitaxial layers fusing recrystallization, laterally release Ge epitaxial layers, can not only obtain high-quality Ge extensions on substrate
Layer, simultaneously as LRC techniques accurately control crystalline areas, on the one hand avoids SOI substrate and Ge epitaxial layers in common process
Between Si, Ge exclusive problem, material interface characteristic is good between another aspect Si/Ge.
Compared with prior art, the invention has the advantages that：
1) laser that uses of present invention crystallization process again, has the advantages that Ge epitaxial layer dislocation densities are low, so that further
Improve the luminous efficiency of light emitting diode.
2) present invention uses p+- Ge/ direct band gaps GeSn/n+- Ge lateral wave conductivity type structure PiN, not only device is luminous imitates
Rate is high, is also beneficial to the integrated of luminescent device and waveguide.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment to the present invention is described in detail.
Fig. 1 is a kind of structural representation based on transversary light emitting diode provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic flow sheet of Crystallizing treatment technique provided in an embodiment of the present invention；
Fig. 3 is a kind of LRC processes schematic diagram provided in an embodiment of the present invention；
Fig. 4 is another structural representation based on transversary light emitting diode provided in an embodiment of the present invention；
Fig. 5 a- Fig. 5 l are a kind of preparation technology schematic diagram based on transversary light emitting diode of the embodiment of the present invention.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation based on transversary light emitting diode provided in an embodiment of the present invention
Figure, including：
SOI substrate 11；
Ge epitaxial layers 12, are arranged at the upper surface of SOI substrate 11；
GeSn layers 13, are arranged at the middle position of the upper surface of Ge epitaxial layers 12；
N-type Ge regions 14, are adulterated by Ge epitaxial layers 12 and are formed, positioned at the side of GeSn layers 13；
P-type Ge regions 15, are adulterated by Ge epitaxial layers 12 and are formed, positioned at the opposite side of GeSn layers 13；
P-type Ge regions 15, GeSn layers 13 and N-type Ge regions 14 form the horizontal PiN structures of ridged：
Positive electrode 16, is arranged at the upper surface in p-type Ge regions 15；
Negative electrode 17, is arranged at the upper surface in N-type Ge regions 14, and transversary light emitting diode 1 is based on to be formed.
Wherein, Ge epitaxial layers 12 include Ge inculating crystal layers and Ge body layers；By Ge inculating crystal layers and Ge body layers by crystallization
Ge epitaxial layers 12 are formed after reason.
Preferably, Fig. 2 is referred to, Fig. 2 is a kind of schematic flow sheet of Crystallizing treatment technique provided in an embodiment of the present invention.
Crystallizing treatment comprises the following steps：
Step 1, the whole backing material including SOI substrate 11, Ge inculating crystal layers, Ge body layers is heated to 700 DEG C；
Step 2, using laser, crystallization (Laser re-crystallization, abbreviation LRC) technique crystallization is entirely served as a contrast again
Bottom material；Wherein LRC techniques optical maser wavelength is 808nm, laser spot size 10mm × 1mm, and laser power is 1.5kW/cm2,
Laser traverse speed is 25mm/s；
Step 3, high-temperature thermal annealing processing is carried out to whole backing material to complete Crystallizing treatment.
Please with further reference to Fig. 3, Fig. 3 is a kind of LRC processes schematic diagram provided in an embodiment of the present invention, LRC techniques
It is a kind of method of thermal induced phase transition crystallization, by laser heat treatment, makes Ge epitaxial layers fusing recrystallization in SOI substrate, laterally release
The dislocation defects of Ge epitaxial layers are put, high-quality Ge epitaxial layers can be not only obtained, simultaneously as LRC techniques accurately control crystalline substance
Change region, on the one hand avoid Si, Ge exclusive problem between SOI substrate and Ge epitaxial layers, another aspect Si/ in common process
Material interface characteristic is good between Ge.
Alternatively, Ge inculating crystal layers thickness is 40~50nm；Ge body layers thickness is 120~150nm.
Alternatively, the thickness of GeSn layers 13 is 250~300nm.
Alternatively, N-type Ge region dopings source is P ion, and doping concentration is 1 × 1019cm-3。
Alternatively, p-type Ge region dopings source is B ions, and doping concentration is 1 × 1019cm-3。
Preferably, in addition to passivation layer, passivation layer is arranged at the upper surface of PiN structures, for isolating positive electrode 16 and negative
Electrode 17.
Wherein, passivation layer is SiO2Material, and its thickness is 150~200nm.
Further, positive electrode 16 and negative electrode 17 are Cr or Au materials, and its thickness is 150~200nm.
The present invention uses laser crystallization process again, the low Ge epitaxial layers of dislocation density is prepared on soi substrates, and prepare high-quality
GeSn layers of direct band gap is measured, a kind of p is then realized+- Ge/ direct band gaps GeSn/n+- Ge transversary light emitting diode, greatly
Improve the luminous efficiency of light emitting diode in ground..
Embodiment two
Fig. 4 is refer to, Fig. 4 is that another structure based on transversary light emitting diode provided in an embodiment of the present invention is shown
It is intended to.The light emitting diode 40 includes：SOI substrate 401, p+- Ge structures 405, GeSn layers 404, n+- Ge structures 406, SiO2It is blunt
Change layer 407 and Metal contact electrode 408；
Wherein, p+- Ge structures 405 and n+- Ge structures 406 are adulterated by Ge epitaxial layers forms and is located at respectively 404 liang of GeSn layers
Side；
Further, Ge epitaxial layers include Ge inculating crystal layers 402 and Ge body layers 403；By Ge inculating crystal layers 402 and Ge body layers
403 using formation Ge epitaxial layers after LRC technique crystallization.
Embodiment three
Refer to Fig. 5 a- Fig. 5 l, Fig. 5 a- Fig. 5 l is a kind of based on transversary light emitting diode of the embodiment of the present invention
Preparation technology schematic diagram, the preparation method comprises the following steps：
S201, substrate are chosen.As shown in Figure 5 a, it is original material to choose SOI substrate piece 001；
S202, Ge inculating crystal layer grow.As shown in Figure 5 b, at a temperature of 275 DEG C~325 DEG C, using CVD technique epitaxial growths
40~50nm Ge inculating crystal layers 002；
S203, Ge body layer grow.As shown in Figure 5 c, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in Ge seeds
120~the 150nm of superficial growth of crystal layer 002 Ge body layers 003；
S204, oxide layer preparation.As fig 5d, 150nm is deposited on the surface of Ge body layers 003 using CVD techniques
SiO2Layer oxide layer 004；
S205, such as Fig. 5 e.The whole lining of SOI substrate 001, Ge inculating crystal layers 002, Ge body layers 003 and oxide layer will be included
Bottom material is heated to 700 DEG C, continuous to use the whole backing material of laser technology crystallization, wherein, optical maser wavelength is 808nm, laser
Spot size 10mm × 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s, the whole substrate material of natural cooling
Material, forms crystallization Ge epitaxial layers.Using the dislocation density and surface roughness that Ge materials are reduced after laser technology crystallization, improve
Ge/SOI substrate interface quality.Then the SiO in Fig. 5 d is etched using dry etch process2Oxide layer 004.
S206, GeSn layers of growth of progress selectivity on crystallization Ge epitaxial layers 005.As shown in figure 5f, in H2Will in atmosphere
Temperature drops to less than 350 DEG C, SnCl4And GeH4Respectively as Sn and Ge sources, growth thickness is the undoped straight of 250~300nm
Tape splicing gap GeSn layers 006；
S207, Ge region N-type ion implanting.It is 200nm in GeSn layers 006 and the surface deposition thickness of Ge epitaxial layers 005
SiO2First protective layer 007, selective etch SiO2First protective layer 007, as shown in fig. 5g；P ion injects, and formation 1 ×
1019cm-3N-type Ge regions 008, high annealing etches away SiO2First protective layer 007, as shown in figure 5h；
S208, Ge region p-type ion implanting.As shown in figure 5i, in GeSn layers 006 and the surface deposition of Ge epitaxial layers 005
Thickness is 200nm SiO2Second protective layer 009, selective etch SiO2Second protective layer 009, B ion implantings form concentration
For 1 × 1019cm-3P-type Ge regions 010, high annealing etches away SiO2Second protective layer 009, as shown in figure 5j；
It is prepared by S209, metal contact hole.As shown in figure 5k, deposition thickness is 150~200nm SiO2Passivation layer 011, every
Destage face makes electrical contact with extraneous.Contact hole is etched, specified SiO is fallen with etching technics selective etch2Form metal contact hole.
It is prepared by S210, metal interconnection.As shown in Fig. 5 l.Use electron beam evaporation deposition thickness for 150~200nm Cr or
Au metal levels 012.Cr the or Au metal levels of selective eating away designated area are carved using etching technics, using chemically mechanical polishing
(CMP) planarization process is carried out.
To sum up, specific case used herein is to the present invention a kind of principle and reality based on transversary light emitting diode
The mode of applying is set forth, and the explanation of above example is only intended to the method and its core concept for helping to understand the present invention；Together
When, for those of ordinary skill in the art, according to the thought of the present invention, have in specific embodiments and applications
Change part, to sum up, this specification content should not be construed as limiting the invention, and protection scope of the present invention should be with appended
Claim is defined.
Claims (10)
1. one kind is based on transversary light emitting diode (1), it is characterised in that including：
SOI substrate (11)；
Ge epitaxial layers (12), are arranged at the upper surface of the SOI substrate (11)；
GeSn layers (13), are arranged at the middle position of the upper surface of the Ge epitaxial layers (12)；
N-type Ge regions (14), are formed by the Ge epitaxial layers (12) doping, positioned at described GeSn layers (13) side；
P-type Ge regions (15), are formed by the Ge epitaxial layers (12) doping, positioned at described GeSn layers (13) opposite side；
The p-type Ge regions (15), described GeSn layers (13) and the N-type Ge regions (14) form the horizontal PiN structures of ridged：
Positive electrode (16), is arranged at the upper surface in p-type Ge regions (15)；
Negative electrode (17), is arranged at the upper surface in N-type Ge regions (14), described based on transversary light emitting diode to be formed
(1)。
2. light emitting diode (1) according to claim 1, it is characterised in that the Ge epitaxial layers (12) include Ge seed crystals
Layer and Ge body layers；The Ge inculating crystal layers and the Ge body layers are formed into the Ge epitaxial layers (12) after Crystallizing treatment.
3. light emitting diode (1) according to claim 2, it is characterised in that the Crystallizing treatment comprises the following steps：
Whole backing material including the SOI substrate (11), the Ge inculating crystal layers, the Ge body layers is heated to 700 DEG C；
Using whole backing material described in LRC technique crystallization；Wherein LRC techniques optical maser wavelength is 808nm, laser spot size
10mm × 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s；
The whole backing material is carried out high-temperature thermal annealing processing to complete the Crystallizing treatment.
4. light emitting diode (1) according to claim 2, it is characterised in that the Ge inculating crystal layers thickness is 40~50nm；
The Ge body layers thickness is 120~150nm.
5. light emitting diode (1) according to claim 1, it is characterised in that described GeSn layers (13) thickness is 250~
300nm。
6. light emitting diode (1) according to claim 1, it is characterised in that the N-type Ge region dopings source is P ion,
Doping concentration is 1 × 1019cm-3。
7. light emitting diode (1) according to claim 1, it is characterised in that the p-type Ge region dopings source is B ions,
Doping concentration is 1 × 1019cm-3。
8. light emitting diode (1) according to claim 1, it is characterised in that also including passivation layer, the passivation layer is set
In the upper surface of the PiN structures, for isolating the positive electrode (16) and the negative electrode (17).
9. light emitting diode (1) according to claim 8, it is characterised in that the passivation layer is SiO2Material, and it is thick
Spend for 150~200nm.
10. light emitting diode (1) according to claim 1, it is characterised in that the positive electrode (16) and the negative electrode
(17) it is Cr or Au materials, and its thickness is 150~200nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710347695.4A CN107170859A (en) | 2017-05-17 | 2017-05-17 | Based on transversary light emitting diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710347695.4A CN107170859A (en) | 2017-05-17 | 2017-05-17 | Based on transversary light emitting diode |
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ID=59816417
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85103942A (en) * | 1985-05-16 | 1986-12-24 | 中国科学院上海冶金所 | The LASER HEATING recrystallization method of polysilicon on the insulation layer |
| WO2010033641A1 (en) * | 2008-09-16 | 2010-03-25 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Gesn infrared photodetectors |
| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
-
2017
- 2017-05-17 CN CN201710347695.4A patent/CN107170859A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85103942A (en) * | 1985-05-16 | 1986-12-24 | 中国科学院上海冶金所 | The LASER HEATING recrystallization method of polysilicon on the insulation layer |
| WO2010033641A1 (en) * | 2008-09-16 | 2010-03-25 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Gesn infrared photodetectors |
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| ERICH KASPER AND MICHAEL OEHME: "Germanium tin light emitters on silicon", 《JAPANESE JOURNAL OF APPLIED PHYSICS》 * |
| 黄志伟等: "激光退火改善Si 上外延Ge 晶体质量", 《第十一届全国硅基光电子材料及器件研讨会论文摘要集》 * |
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Application publication date: 20170915 |