CN107123711B - A kind of carinate LED and preparation method thereof - Google Patents
A kind of carinate LED and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000002425 crystallisation Methods 0.000 claims abstract description 17
- 230000008025 crystallization Effects 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 134
- 239000011241 protective layer Substances 0.000 claims description 26
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 241000931526 Acer campestre Species 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000005499 laser crystallization Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 description 11
- 229910052906 cristobalite Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052682 stishovite Inorganic materials 0.000 description 11
- 229910052905 tridymite Inorganic materials 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
- H01L33/0012—Devices characterised by their operation having p-n or hi-lo junctions p-i-n devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/34—Materials of the light emitting region containing only elements of Group IV of the Periodic Table
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Abstract
The present invention relates to a kind of carinate LED and preparation method thereof.Wherein, the preparation method includes: selection SOI substrate；Ge epitaxial layer is grown on SOI substrate surface using CVD technique；Oxide layer is grown in Ge epi-layer surface using CVD technique；Modified Ge epitaxial layer is formed using LRC technique crystallization Ge epitaxial layer；Utilize dry etch process etching oxidation layer；At modified intrinsic Ge layers of the growth of Ge epi-layer surface；The intrinsic Ge layers of formation ridge structure of selective etch；P ion is injected separately into the two sides of ridge structure and B ion forms the region N-type Ge and the region p-type Ge；Metal contact electrode is prepared to complete the preparation of carinate LED；The present invention prepares the low Ge epitaxial layer of dislocation density, and prepare high quality direct band gap Ge epitaxial layer using laser crystallization process again on soi substrates, then realizes a kind of carinate LED and preparation method thereof.
Description
Technical field
The invention belongs to technical field of semiconductor device preparation, in particular to a kind of carinate LED and preparation method thereof.
Background technique
With the continuous development of integrated circuit, the delay of metal interconnection signal with more protruded the problem of power consumption, high-speed light is mutual
Connection technology is to solve the problems, such as this effective technology means.It realizes high-speed light interconnection technique, needs to solve many problem in science.Its
In, waveguide type luminescent device (LED) integrated light-emitting device and waveguide are in an important research in Si base monolithic optoelectronic integration
Hold.
Ge semiconductor can be changed into collimation by modification technology (such as stress, alloying) for indirect band-gap semiconductor
Tape splicing gap or direct band-gap semicondictor, it is high to be applied to Si fundamental wave conductivity type LED luminous efficiency, and with Si process compatible, be current
The emphasis studied, applied in field.
From the point of view of the case where current device technology is realized, not using the thermal expansion coefficient between Si substrate and Ge epitaxial layer
Together, reasonable thermal anneal process system is used during common process, Ge epitaxial layer can introduce low-intensity and answer on Si substrate
Become, and then realizes quasi- direct band gap Ge.However, due between Si substrate and Ge epitaxial layer lattice mismatch it is larger, on Si substrate often
The Ge epitaxial layer dislocation density for advising technique preparation is high, constrains the promotion of device performance.
Therefore the LED for selecting which kind of material and technique to prepare high quality becomes particularly important.
Summary of the invention
In order to improve the performance of existing luminescent device, the present invention utilizes laser crystallization process again, prepares position on soi substrates
Dislocation density is low, high quality direct band gap Ge epitaxial layer, then realizes a kind of carinate LED and preparation method thereof；The invention solves
The technical issues of be achieved through the following technical solutions:
An embodiment provides the preparation methods of carinate LED a kind of, comprising:
(a) SOI substrate is chosen；
(b) raw on SOI substrate surface using chemical vapor deposition (Chemical Vapor Deposition, CVD) technique
Long Ge epitaxial layer；
(c) oxide layer is grown in Ge epi-layer surface using CVD technique；
(d) modified Ge epitaxial layer is formed using LRC technique crystallization Ge epitaxial layer；
(e) dry etch process etching oxidation layer is utilized；
(f) intrinsic Ge layers is grown in modified Ge epi-layer surface using CVD technique；
(g) the intrinsic Ge layers of formation ridge structure of selective etch；
(h) P ion is injected separately into the two sides of ridge structure and B ion forms the region N-type Ge and the region p-type Ge；
(i) Metal contact electrode is prepared to complete the preparation of carinate LED.
In one embodiment of the invention, step (b) includes:
It (b1) in SOI substrate surface growth thickness is 40~50nm using CVD technique at a temperature of 275 DEG C~325 DEG C
Ge seed layer；
(b2) at a temperature of 500 DEG C~600 DEG C, using CVD technique Ge seed crystal surface growth thickness be 120~
The Ge body layer of 150nm is to form Ge epitaxial layer.
In one embodiment of the invention, step (d) includes:
(d1) the entire substrate material including SOI substrate, Ge epitaxial layer and oxide layer is heated to 700 DEG C；
(d2) laser crystallization (Laser re-crystallization, abbreviation LRC) technique crystallization Ge epitaxial layer again is utilized；
Wherein, optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm in LRC technique2, laser
Movement speed is 25mm/s；
(d3) cooling entire substrate material forms modified Ge epitaxial layer.
Wherein, LRC technique is that a kind of method of thermal induced phase transition crystallization makes Ge extension in SOI substrate by laser heat treatment
Layer fusing recrystallization, laterally discharges the dislocation defects of Ge epitaxial layer, not only reduces the dislocation density and rough surface of Ge material
Degree, and improve Ge/SOI substrate interface quality.
In one embodiment of the invention, step (f) is included: and is existed at a temperature of 500 DEG C~600 DEG C using CVD technique
Modified Ge epi-layer surface growth thickness is intrinsic Ge layers of 500~550nm.
Wherein, since this Ge layers is grown on Ge epitaxial layer after crystallization, so the quality of Ge is preferable, lattice mismatch
Rate is lower.
In one embodiment of the invention, in step (g), ridge segment thickness is 350nm, and width is 1 μm.
In one embodiment of the invention, step (h) includes:
(h1) the first protective layer is deposited in intrinsic Ge layer surface, the first protective layer of selective etch forms N-type ion injection
Window；
(h2) P ion injection is carried out to N-type ion injection window, forming doping concentration is 1 × 1019cm-3The area NXing Ge
Domain, high annealing etch away the first protective layer；
(h3) the second protective layer is deposited in intrinsic Ge layer surface, the second protective layer of selective etch forms P-type ion injection
Window；
(h4) B ion doping is carried out to P-type ion injection window, forming doping concentration is 1 × 1019cm-3The area PXing Ge
Domain, high annealing etch away the second protective layer.
In one embodiment of the invention, step (i) includes:
It (i1) is the passivation layer of 150~200nm in the region N-type Ge, the region p-type Ge and intrinsic Ge layer surface deposition thickness,
Fall the passivation layer formation metal contact hole in specified region with etching technics selective etch；
(i2) using electron beam evaporation process, deposition thickness is the Cr of 150~200nm on passivation layer and metal contact hole
Metal layer；
(i3) the Cr metal layer that selective eating away specifies region is carved using etching technics, is carried out using chemically mechanical polishing flat
Smoothization processing is to form the Metal contact electrode.
Another embodiment of the present invention provides a kind of carinate LED, the preparation method provided by any of the above-described embodiment
It is formed.
Another embodiment of the invention provides a kind of carinate LED, comprising: SOI substrate is modified Ge epitaxial layer, is intrinsic
Ge layers, the region N-type Ge, the region p-type Ge, passivation layer and Metal contact electrode；
Wherein, the modified Ge epitaxial layer is by being formed after LRC technique crystallization Ge epitaxial layer by thermal anneal process；
Wherein, described intrinsic Ge layers are ridge structure, and intrinsic Ge layers of the ridge segment thickness is 350nm, width 1
μm。
Compared with prior art, the invention has the following advantages:
1) laser that uses of present invention crystallization process again, has the advantages that Ge epitaxial layer dislocation density is low, utilizes it as
Carinate LED active area, device light emitting efficiency are promoted.
2) LED structure of the present invention is carinate p+- Ge/ low-intensity tensile strain Ge/n+The transverse structure PiN of-Ge, after being conducive to
The realization of continuous monolithic optoelectronic integration.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is a kind of preparation method flow chart of carinate LED provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 m is the preparation method process flow diagram of carinate LED of the embodiment of the present invention a kind of；
Fig. 3 is a kind of structural schematic diagram of carinate LED provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of preparation method flow chart of carinate LED provided in an embodiment of the present invention, comprising:
(a) SOI substrate is chosen；
(b) Ge epitaxial layer is grown on SOI substrate surface using CVD technique；
(c) oxide layer is grown in Ge epi-layer surface using CVD technique；
(d) modified Ge epitaxial layer is formed using LRC technique crystallization Ge epitaxial layer；
(e) dry etch process etching oxidation layer is utilized；
(f) intrinsic Ge layers is grown in modified Ge epi-layer surface using CVD technique；
(g) the intrinsic Ge layers of formation ridge structure of selective etch；
(h) P ion is injected separately into the two sides of ridge structure and B ion forms the region N-type Ge and the region p-type Ge；
(i) Metal contact electrode is prepared to complete the preparation of carinate LED.
Preferably, step (b) may include:
It (b1) in SOI substrate surface growth thickness is 40~50nm using CVD technique at a temperature of 275 DEG C~325 DEG C
Ge seed layer；
(b2) at a temperature of 500 DEG C~600 DEG C, using CVD technique Ge seed crystal surface growth thickness be 120~
The Ge body layer of 150nm is to form Ge epitaxial layer.
Preferably, step (d) may include:
(d1) the entire substrate material including SOI substrate, Ge epitaxial layer and oxide layer is heated to 700 DEG C；
(d2) LRC technique crystallization Ge epitaxial layer is utilized；Wherein, optical maser wavelength is 808nm, laser facula ruler in LRC technique
Very little 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
(d3) cooling entire substrate material forms modified Ge epitaxial layer.
Preferably, step (f) may include: at a temperature of 500 DEG C~600 DEG C, using CVD technique in modified Ge epitaxial layer
Surface growth thickness is intrinsic Ge layers of 500~550nm.
Preferably, in step (g), ridge segment thickness is 350nm, and width is 1 μm.
Preferably, step (h) may include:
(h1) the first protective layer is deposited in intrinsic Ge layer surface, the first protective layer of selective etch forms N-type ion injection
Window；
(h2) P ion injection is carried out to N-type ion injection window, forming doping concentration is 1 × 1019cm-3The area NXing Ge
Domain, high annealing etch away the first protective layer；
(h3) the second protective layer is deposited in intrinsic Ge layer surface, the second protective layer of selective etch forms P-type ion injection
Window；
(h4) B ion doping is carried out to P-type ion injection window, forming doping concentration is 1 × 1019cm-3The area PXing Ge
Domain, high annealing etch away the second protective layer.
Preferably, step (i) may include:
It (i1) is the passivation layer of 150~200nm in the region N-type Ge, the region p-type Ge and intrinsic Ge layer surface deposition thickness,
Fall the passivation layer formation metal contact hole in specified region with etching technics selective etch；
(i2) using electron beam evaporation process, deposition thickness is the Cr of 150~200nm on passivation layer and metal contact hole
Metal layer；
(i3) the Cr metal layer that selective eating away specifies region is carved using etching technics, is carried out using chemically mechanical polishing flat
Smoothization processing.
The present invention proposes to use LRC technique, by laser heat treatment, makes Ge epitaxial layer fusing recrystallization in SOI substrate, horizontal
To the dislocation defects of release Ge epitaxial layer, the Ge epitaxial layer of low-dislocation-density is obtained, to improve device performance.Meanwhile the present invention
The carinate p of proposed adoption+- Ge/ low-intensity tensile strain Ge/n+The transverse structure PiN of-Ge, conducive to the realization of subsequent monolithic optoelectronic integration.
Embodiment two
A- Fig. 2 m referring to figure 2., Fig. 2 a- Fig. 2 m are the preparation method work of another carinate LED of the embodiment of the present invention
Skill flow diagram, the preparation method include the following steps:
S101, substrate are chosen.As shown in Figure 2 a, choosing SOI substrate piece 001 is original material；
S102, Ge outer layer growth.
S1021, Ge seed crystal layer epitaxially grown.As shown in Figure 2 b, at a temperature of 275 DEG C~325 DEG C, using CVD technique outside
Prolong the Ge seed layer 002 that growth thickness is 40~50nm；
The growth of S1022, Ge body layer.As shown in Figure 2 c, at a temperature of 500 DEG C~600 DEG C, using CVD technique in Ge
Seed crystal surface growth thickness is the Ge body layer 003 of 120~150nm；
The preparation of S103, oxide layer.As shown in Figure 2 d, using CVD technique, deposition thickness is in Ge main body layer surface
150nm SiO2Oxide layer 004；
The crystallization and oxide layer of S104, Ge epitaxial layer etch；It will include SOI substrate, Ge epitaxial layer and oxide layer such as Fig. 2 e
Entire substrate material be heated to 700 DEG C, using the entire substrate material of LRC technique crystallization, wherein optical maser wavelength 808nm, swash
Light spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s, cooling entire substrate material
Material.This method reduce the dislocation density of Ge material and surface roughnesses, improve crystal quality.Then dry etching work is utilized
Skill etching oxidation layer 004, the modification Ge epitaxial layer 005 after obtaining laser crystallization；
S105, as shown in figure 2f, at a temperature of 330 DEG C, using decompression CVD growth with a thickness of the intrinsic Ge of 500~550nm
Layer, (watch for the ease of illustration, by after crystallization Ge layer and crystallization after the intrinsic Ge that grows it is laminated be i-Ge layers 006).By
It is to grow on Ge epitaxial layer after crystallization in this intrinsic Ge layers, so the quality of Ge is preferable, lattice mismatch rate is lower.
S106, as shown in Figure 2 g, forms with a thickness of 350nm by i-Ge layer of selective etch, and width is 1 μm of ridge structure；
The injection of the region S107, Ge N-type ion.
S1071, as shown in fig. 2h, in the SiO that i-Ge layer surface deposition thickness is 200nm2Protective layer, selective etch
SiO2Protective layer obtains SiO2Protective layer 007；
S1072, as shown in fig. 2i, to i-Ge layers of progress P ion injection, forming doping concentration is 1 × 1019cm-3N-type
The region Ge 008, high annealing etch away SiO2Protective layer 007；
The injection of the region S108, Ge P-type ion.
S1081, as shown in figure 2j, the SiO for being 200nm in i-Ge layers and N-type Ge region surface deposition thickness2Protective layer,
Selective etch SiO2Protective layer obtains SiO2Protective layer 009,
S1082, as shown in Fig. 2 k, to i-Ge layers of progress B ion implanting, forming doping concentration is 1 × 1019cm-3P-type
The region Ge 010, high annealing etch away SiO2Protective layer 009；
S009, metal contact hole preparation.As illustrated in figure 21, it is deposited in i-Ge layers, the region N-type Ge and p-type Ge region surface
With a thickness of the SiO of 150~200nm2Passivation layer 011, isolation table top and extraneous electrical contact.Contact hole is etched, is selected with etching technics
Selecting property etches away specified region SiO2Passivation layer formation metal contact hole.
S010, metal interconnection preparation.As shown in Fig. 2 m, using electron beam evaporation process in SiO2Passivation layer and metal contact
Hole deposition thickness is the metal Cr layer 012 of 150~200nm.The metal Cr that selective eating away specifies region is carved using etching technics,
Planarization process is carried out using CMP process (CMP).
Embodiment three
Referring to figure 3., Fig. 3 is a kind of structural schematic diagram of carinate LED provided in an embodiment of the present invention.The LED utilizes upper
The preparation method as shown in Fig. 2 a- Fig. 2 m is stated to be made.Specifically, LED includes: SOI substrate (301), modified Ge epitaxial layer
(302), Ge layers intrinsic (303), the region N-type Ge (304), the region p-type Ge (305), SiO2Passivation layer (306) and metal contact
Electrode (307)；
Wherein, the modified Ge epitaxial layer is by being formed after LRC technique crystallization Ge epitaxial layer by thermal anneal process.
Preferably, described intrinsic Ge layers are ridge structure, and intrinsic Ge layers of the ridge segment thickness is 350nm, width
It is 1 μm.
To sum up, specific case used herein explains a kind of principle and embodiment of carinate LED of the present invention
It states, the above description of the embodiment is only used to help understand the method for the present invention and its core ideas；Meanwhile for this field
Those skilled in the art, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, to sum up,
The contents of this specification are not to be construed as limiting the invention, and protection scope of the present invention should be subject to the attached claims.
Claims (8)
1. a kind of preparation method of carinate LED characterized by comprising
(a) SOI substrate is chosen；
(b) Ge epitaxial layer is grown on the SOI substrate surface using CVD technique；
(c) oxide layer is grown in the Ge epi-layer surface using CVD technique；
(d) modified Ge epitaxial layer is formed using Ge epitaxial layer described in LRC technique crystallization；
(e) oxide layer is etched using dry etch process；
(f) intrinsic Ge layers is grown in the modified Ge epi-layer surface using CVD technique；
(g) intrinsic Ge layers of formation ridge structure described in selective etch；
(h) P ion is injected separately into the two sides of the ridge structure and B ion forms the region N-type Ge and the region p-type Ge；
(i) Metal contact electrode is prepared to complete the preparation of the carinate LED.
2. preparation method according to claim 1, which is characterized in that step (b) includes:
It (b1) in SOI substrate surface growth thickness is 40~50nm using CVD technique at a temperature of 275 DEG C~325 DEG C
Ge seed layer；
(b2) at a temperature of 500 DEG C~600 DEG C, using CVD technique the Ge seed crystal surface growth thickness be 120~
The Ge body layer of 150nm is to form the Ge epitaxial layer.
3. preparation method according to claim 1, which is characterized in that step (d) includes:
(d1) the entire substrate material including the SOI substrate, the Ge epitaxial layer and the oxide layer is heated to 700 DEG C；
(d2) Ge epitaxial layer described in LRC technique crystallization is utilized；Wherein, optical maser wavelength is 808nm, laser facula ruler in LRC technique
Very little 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
(d3) cooling entire substrate material forms the modified Ge epitaxial layer.
4. preparation method according to claim 1, which is characterized in that step (f) includes:
At a temperature of 500 DEG C~600 DEG C, using CVD technique the modified Ge epi-layer surface growth thickness be 500~
Intrinsic Ge layers of 550nm.
5. preparation method according to claim 1, which is characterized in that in step (g), the ridge part of the ridge structure
With a thickness of 350nm, width is 1 μm.
6. preparation method according to claim 1, which is characterized in that step (h) includes:
(h1) the first protective layer is deposited in the intrinsic Ge layer surface, the first protective layer described in selective etch forms N-type ion
Inject window；
(h2) P ion injection is carried out to N-type ion injection window, forming doping concentration is 1 × 1019cm-3The N-type Ge
Region, high annealing etch away first protective layer；
(h3) the second protective layer is deposited in the intrinsic Ge layer surface, the second protective layer described in selective etch forms P-type ion
Inject window；
(h4) B ion doping is carried out to P-type ion injection window, forming doping concentration is 1 × 1019cm-3The p-type Ge
Region, high annealing etch away second protective layer.
7. preparation method according to claim 1, which is characterized in that step (i) includes:
It (i1) is 150~200nm's in the region the N-type Ge, the region the p-type Ge and the intrinsic Ge layer surface deposition thickness
Passivation layer falls the passivation layer formation metal contact hole in specified region with etching technics selective etch；
(i2) using electron beam evaporation process, deposition thickness is 150~200nm on the passivation layer and the metal contact hole
Cr metal layer；
(i3) the Cr metal layer that selective eating away specifies region is carved using etching technics, is carried out using chemically mechanical polishing flat
Smoothization processing is to form the Metal contact electrode.
8. a kind of carinate LED, which is characterized in that the LED is prepared by the described in any item methods of claim 1~7 and formed.
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