CN107275453A - Carinate light emitting diode - Google Patents
Carinate light emitting diode Download PDFInfo
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- CN107275453A CN107275453A CN201710347986.3A CN201710347986A CN107275453A CN 107275453 A CN107275453 A CN 107275453A CN 201710347986 A CN201710347986 A CN 201710347986A CN 107275453 A CN107275453 A CN 107275453A
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- 238000000034 method Methods 0.000 claims abstract description 31
- 238000002425 crystallisation Methods 0.000 claims abstract description 24
- 230000008025 crystallization Effects 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 14
- 229910005939 Ge—Sn Inorganic materials 0.000 claims description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910001020 Au alloy Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 96
- 239000011241 protective layer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000026267 regulation of growth Effects 0.000 description 3
- 241000931526 Acer campestre Species 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910021627 Tin(IV) chloride Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present invention relates to a kind of carinate light emitting diode, including：SOI substrate layer, Ge layers of crystallization, carinate Ge Sn alloy-layers, N-type Ge Sn alloy-layers, p-type Ge Sn alloy-layers, wherein：Described crystallization Ge layers are located on SOI substrate layer；The carinate Ge Sn alloy-layers are located at centre position on the crystallization Ge layer surfaces；The N-type Ge Sn alloy-layers and p-type Ge Sn alloy-layers are located at the carinate Ge Sn alloy-layers both sides on the crystallization Ge layer surfaces.The present invention utilizes LRC PROCESS FOR TREATMENT Ge epitaxial layers, and laterally the dislocation defects of release Ge epitaxial layers, obtain the Ge epitaxial layers of low-dislocation-density；Simultaneously as LRC techniques accurately control crystalline areas, material interface characteristic is good between Si and Ge, so as to improve device performance.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of carinate light emitting diode.
Background technology
In recent years, the semiconductor devices using silicon as substrate has become the development priority in the field.High-quality silicon substrate light
Source device is the research emphasis of silicon optoelectronic technical field.Ge is indirect band-gap semiconductor, but Ge-Sn alloys are direct band gap half
Conductor, the development applied to silicon substrate LED.But in Ge-Sn alloy LED technical process is prepared, in order to improve LED quality,
Need first to prepare Ge cushions on a silicon substrate, but Ge cushions and Si substrate lattice mismatches are larger, have had a strong impact on LED hair
Light efficiency.
Therefore, how to develop a kind of higher Ge-Sn alloys LED of high-quality, luminous efficiency and have become the field urgently
To be solved the problem of.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of carinate light emitting diode.
An embodiment provides a kind of carinate light emitting diode, including：SOI substrate layer, Ge layers of crystallization, ridge
Shape Ge-Sn alloy-layers, N-type Ge-Sn alloy-layers, p-type Ge-Sn alloy-layers, wherein：
Described crystallization Ge layers are located on SOI substrate layer；
The carinate Ge-Sn alloy-layers are located at centre position on the crystallization Ge layer surfaces；
The N-type Ge-Sn alloy-layers and the p-type Ge-Sn alloy-layers are located at the ridge on the crystallization Ge layer surfaces
Shape Ge-Sn alloy-layers both sides.
In one embodiment of the invention, described crystallization Ge layers are to pass through laser crystallization (Laser re- again
Crystallization, abbreviation LRC) technique formation Ge layers.
In one embodiment of the invention, laser parameter is in the parameter of the LRC techniques：Optical maser wavelength is 808nm,
Laser spot size is 10mm × 1mm, and laser power is 1.5kW/cm2, and laser traverse speed is 25mm/s.
In one embodiment of the invention, in addition to passivation layer, the passivation layer be located at the N-type Ge-Sn alloy-layers,
On the carinate Ge-Sn alloy-layers, the p-type Ge-Sn alloy-layers.
In one embodiment of the invention, the material of the passivation layer is SiO2。
In one embodiment of the invention, in addition to first electrode and second electrode, wherein：
The first electrode, on the N-type Ge-Sn alloy-layers；
The second electrode, on the p-type Ge-Sn alloy-layers.
In one embodiment of the invention, the material of the first electrode and the second electrode is Cr-Au alloys.
In one embodiment of the invention, the doping concentration of the N-type Ge-Sn alloy-layers is 1 × 1019cm-3。
In one embodiment of the invention, the doping concentration of the p-type Ge-Sn alloy-layers is 1 × 1019cm-3。
In one embodiment of the invention, the carinate Ge-Sn alloy layer thicknesses are 150~200nm, and mixing Sn components is
8%, it is 92% to mix Ge components.
The embodiment of the present invention, using the dislocation defects of LRC PROCESS FOR TREATMENT Ge epitaxial layers, laterally release Ge epitaxial layers, is obtained
The Ge epitaxial layers of low-dislocation-density；Simultaneously as LRC techniques accurately control crystalline areas, material interface is special between Si and Ge
Property is good, so as to improve device performance.
Brief description of the drawings
Fig. 1 is a kind of structural representation of carinate light emitting diode provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 l are a kind of preparation technology schematic diagram of carinate light emitting diode of the embodiment of the present invention；
Fig. 3 is a kind of LRC process schematic representations provided in an embodiment of the present invention.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, is a kind of structural representation of carinate light emitting diode provided in an embodiment of the present invention.The carinate hair
Optical diode includes：SOI substrate layer 401, crystallization Ge layers 402, carinate Ge-Sn alloy-layers 403, N-type Ge-Sn alloy-layers 404, P
Type Ge-Sn alloy-layers 405, wherein：
The crystallization Ge layers 402 are located on SOI substrate layer 401；
The carinate Ge-Sn alloy-layers 403 are located at centre position on the surface of crystallization Ge layers 402；
The N-type Ge-Sn alloy-layers 404 and p-type Ge-Sn alloy-layers 405 are located at institute on the surface of crystallization Ge layers 402
State the carinate both sides of Ge-Sn alloy-layers 403.
Wherein, the crystallization Ge layers 402 are the Ge layers by the formation of LRC techniques.
Wherein, laser parameter is in the parameter of the LRC techniques：Optical maser wavelength is 808nm, and laser spot size is 10mm
× 1mm, laser power is 1.5kW/cm2, laser traverse speed is 25mm/s.
In addition, the light emitting diode also includes passivation layer 406, the passivation layer 406 is located at the N-type Ge-Sn alloys
Layer 404, carinate Ge-Sn alloy-layers 403, on p-type Ge-Sn alloy-layers 405.
Preferably, the material of the passivation layer 406 is SiO2。
Wherein, the light emitting diode also includes first electrode 407 and second electrode 408, wherein：
First electrode 407, on the N-type Ge-Sn alloy-layers 404；
Second electrode 408, on the p-type Ge-Sn alloy-layers 405.
Preferably, the material of the first electrode 407 and the second electrode 408 is Cr-Au alloys.
Preferably, the doping concentration of the N-type Ge-Sn alloy-layers 404 is 1 × 1019cm-3。
Preferably, the doping concentration of the p-type Ge-Sn alloy-layers 405 is 1 × 1019cm-3。
Preferably, the carinate thickness of Ge-Sn alloy-layers 403 is 150~200nm, and it is 8% to mix Sn components, mixes Ge components
For 92%.
The present invention utilizes LRC PROCESS FOR TREATMENT Ge epitaxial layers, and laterally the dislocation defects of release Ge epitaxial layers, obtain low dislocation close
The Ge epitaxial layers of degree；Simultaneously as LRC techniques accurately control crystalline areas, material interface characteristic is good between Si and Ge, so that
Improve device performance.
Embodiment two
The preparation technology that refer to a kind of carinate light emitting diode of Fig. 2 a- Fig. 2 l, Fig. 2 a- Fig. 2 l embodiment of the present invention shows
It is intended to, the preparation method comprises the following steps：
1st step, selection substrate.SOI substrate 301 is chosen, as shown in Figure 2 a.
2nd step, growth Ge inculating crystal layers 302.At a temperature of 275 DEG C~325 DEG C, using CVD techniques, in SOI substrate 301
Growth thickness is 40~50nm Ge inculating crystal layers 302, as shown in Figure 2 b.
3rd step, growth Ge body layers 303.At a temperature of 500 DEG C~600 DEG C, using CVD techniques, in Ge inculating crystal layers 302
Upper growth thickness is 120~150nm Ge body layers 303, as shown in Figure 2 c.
4th step, the SiO of growth regulation one2Protective layer 304.Using CVD techniques, growth thickness is first on Ge body layers 303
150nm SiO2Oxide layer 304, as shown in Figure 2 d.
5th step, making crystallization Ge layers 305.SOI substrate 001, Ge inculating crystal layers 302, Ge body layers 303 and first will be included
SiO2The whole backing material of oxide layer 304 is heated to 700 DEG C, and continuous using laser, crystallization process handles whole material again, so
After recycle dry etch process, etch the first SiO2Oxide layer 304 obtains crystallization Ge layers 305, as shown in Figure 2 e.
Fig. 3 is referred to, Fig. 3 is a kind of LRC processes schematic diagram provided in an embodiment of the present invention.LRC techniques are a kind of
The method of thermal induced phase transition crystallization, by laser heat treatment, makes Ge epitaxial layers fusing recrystallization on Si substrates, laterally release Ge extensions
The dislocation defects of layer, can not only obtain high-quality Ge epitaxial layers, simultaneously as LRC techniques accurately control crystalline areas, one
Aspect avoids in common process material between Si, Ge exclusive problem between Si substrates and Ge epitaxial layers, another aspect Si/Ge
Interfacial characteristics is good.
6th step, growth Ge-Sn alloy-layers 306.In H2In atmosphere, below 350 DEG C of temperature, with SnCl4And GeH4Respectively
As Sn and Ge sources, it is 8% to mix Sn components, and it is 92% to mix Ge components, grows 150~200nm Ge-Sn alloy-layers, Ran Houli
With dry etch process, the Ge-Sn alloy-layers in etched portions region form carinate Ge-Sn alloy-layers 306, as shown in figure 2f.
7th step, the SiO of growth regulation two2Doped region is treated in protective layer 307 and making first.On carinate Ge-Sn alloy-layers
Growth thickness is 200nm the 2nd SiO2Protective layer 307；Using dry etch process, the 2nd SiO is etched2The finger of protective layer 307
Determine region, forming first on the carinate surface of Ge-Sn alloy-layers 306 treats doped region, as shown in Figure 2 g.
8th step, making N-type Ge-Sn alloy-layers.Using ion implantation technology, treat that doped region injects P ion first,
It is 1 × 10 to form doping concentration19cm-3N-type Ge-Sn alloy-layers 308；Whole material to including N-type Ge-Sn alloy-layers 308
Made annealing treatment, then using dry etch process, etch away the 2nd SiO2Protective layer 307, as shown in fig. 2h.
9th step, the SiO of growth regulation three2Doped region is treated in protective layer 309 and making second.On carinate Ge-Sn alloy-layers
Growth thickness is 200nm the 3rd SiO2Protective layer 309；Using dry etch process, the 3rd SiO is etched2The specified area of protective layer
Domain, treats doped region, as shown in fig. 2i in carinate Ge-Sn alloyed layers formation second.
10th step, making p-type Ge-Sn alloy-layers 310.Using ion implantation technology, second treat doped region injection B from
Son, it is 1 × 10 to form doping concentration19cm-3P-type Ge-Sn alloy-layers 310；Whole material to including p-type Ge-Sn alloy-layers
Made annealing treatment, then using dry etch process, etch away the 3rd SiO2Protective layer 309, as shown in figure 2j.
11st step, growth SiO2Passivation layer 311 and making metal contact hole 312.In carinate Ge-Sn alloy-layers 306, N
Type Ge-Sn alloy-layers 308 and the SiO that the superficial growth thickness of p-type Ge-Sn alloy-layers 310 is 150~200nm2Passivation layer 311；Profit
With dry etch process, SiO is etched2The designated area of passivation layer, forms metal contact hole 312, as shown in Fig. 2 k.
12nd step, growth Cr-Au alloy electrodes 313.Using electron beam evaporation process, in the life of the region of metal contact hole 312
Long thickness for 150~200nm Cr-Au alloy-layers 313 as electrode, as illustrated in figure 21.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (10)
1. a kind of carinate light emitting diode, it is characterised in that including：SOI substrate layer, Ge layers of crystallization, carinate Ge-Sn alloy-layers, N
Type Ge-Sn alloy-layers, p-type Ge-Sn alloy-layers, wherein：
Described crystallization Ge layers are located on SOI substrate layer；
The carinate Ge-Sn alloy-layers are located at centre position on the crystallization Ge layer surfaces；
The N-type Ge-Sn alloy-layers and the p-type Ge-Sn alloy-layers are located at the carinate Ge- on the crystallization Ge layer surfaces
Sn alloy-layers both sides.
2. diode according to claim 1, it is characterised in that described crystallization Ge layers are the Ge formed by LRC techniques
Layer.
3. diode according to claim 2, it is characterised in that laser parameter is in the parameter of the LRC techniques：Laser
Wavelength is 808nm, and laser spot size is 10mm × 1mm, and laser power is 1.5kW/cm2, laser traverse speed is 25mm/s.
4. diode according to claim 1, it is characterised in that the light emitting diode also includes passivation layer, described blunt
Change layer on the N-type Ge-Sn alloy-layers, the carinate Ge-Sn alloy-layers, the p-type Ge-Sn alloy-layers.
5. diode according to claim 4, it is characterised in that the material of the passivation layer is SiO2。
6. diode according to claim 1, it is characterised in that the light emitting diode also includes first electrode and second
Electrode, wherein：
The first electrode, on the N-type Ge-Sn alloy-layers；
The second electrode, on the p-type Ge-Sn alloy-layers.
7. diode according to claim 6, it is characterised in that the material of the first electrode and the second electrode is
Cr-Au alloys.
8. diode according to claim 1, it is characterised in that the doping concentration of the N-type Ge-Sn alloy-layers is 1 ×
1019cm-3。
9. diode according to claim 1, it is characterised in that the doping concentration of the p-type Ge-Sn alloy-layers is 1 ×
1019cm-3。
10. diode according to claim 1, it is characterised in that the carinate Ge-Sn alloy layer thicknesses are 150~
200nm, it is 8% to mix Sn components, and it is 92% to mix Ge components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710347986.3A CN107275453A (en) | 2017-05-17 | 2017-05-17 | Carinate light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710347986.3A CN107275453A (en) | 2017-05-17 | 2017-05-17 | Carinate light emitting diode |
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|---|---|
| CN107275453A true CN107275453A (en) | 2017-10-20 |
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ID=60064491
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|---|---|---|---|
| CN201710347986.3A Pending CN107275453A (en) | 2017-05-17 | 2017-05-17 | Carinate light emitting diode |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150129911A1 (en) * | 2013-11-08 | 2015-05-14 | Wisconsin Alumni Research Foundation | Strain tunable light emitting diodes with germanium p-i-n heterojunctions |
| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
| CN206992138U (en) * | 2017-05-17 | 2018-02-09 | 西安科锐盛创新科技有限公司 | Carinate light emitting diode |
-
2017
- 2017-05-17 CN CN201710347986.3A patent/CN107275453A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206509A (en) * | 2009-11-30 | 2015-12-30 | 应用材料公司 | Crystallization Processing For Semiconductor Applications |
| US20150129911A1 (en) * | 2013-11-08 | 2015-05-14 | Wisconsin Alumni Research Foundation | Strain tunable light emitting diodes with germanium p-i-n heterojunctions |
| CN104993025A (en) * | 2015-07-01 | 2015-10-21 | 西安电子科技大学 | Silicon nitride membrane strained GeSn infrared LED device and preparation method thereof |
| CN206992138U (en) * | 2017-05-17 | 2018-02-09 | 西安科锐盛创新科技有限公司 | Carinate light emitting diode |
Non-Patent Citations (1)
| Title |
|---|
| 黄志伟 等: ""激光退火改善Si上外延Ge晶体质量"", 《第十一届全国硅基光电子材料及器件研讨会论文摘要集》 * |
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Application publication date: 20171020 |