KR20090028581A - Thin film photovoltaic structure and fabrication - Google Patents

Abstract

Novel photovoltaic structures comprising an insulator structure bonded to an exfoliation layer, preferably of a substantially single-crystal donor semiconductor wafer, and at least one photovoltaic device layer, such as a conductive layer, and systems and methods of production of a photovoltaic device, comprising creating on a donor semiconductor wafer an exfoliation layer and transferring the exfoliation layer to an insulator substrate.

Description

Thin film photovoltaic structure and its manufacturing method {THIN FILM PHOTOVOLTAIC STRUCTURE AND FABRICATION}

FIELD OF THE INVENTION The present invention relates to methods and articles of manufacture for thin film photovoltaic structures, preferably having substantially single crystal thin films using an improved process. In particular, the method includes transferring the basic or partially completed photovoltaic structure of the insulating substrate to the insulating substrate and anodically bonding the insulating substrate.

Photovoltaic structures (PVS) are a specific form of semiconductor structure that converts photons into electricity. Basically, the device needs to fulfill only two functions: separating the charge carriers into conductive contacts that transport the photovoltaic and electricity of the charge carriers (electrons and holes) in the light-absorbing material. It is to let. This conversion, called the photovoltaic (PV) effect, is used in solar cells that convert light energy into electrical energy. The research field related to solar cells is also known as photovoltaics. Some PVSs are semiconductor-on-insulator (SOI) structures.

1 to 3, block diagrams show single-junction, dual-junction, and triple-junction photovoltaic structures, respectively. Reference numerals in the drawings have the following meanings: A101: Ge substrate; A103 / 105: 1.4eV GaAs cell; A107: grid contact; A201: Ge substrate; A203: 1.4eV GaAs cell; A207: AlGaLnP or AlGaAs tunnel junction; A209 / 211: 1.9 eV InGaP cell; A213: grid contact; A301: 0.7 eV Ge cell and substrate; A305: GaAs tunnel junction; A307 / 309: 1.4 eV GaAs cell; A311: tunnel junction; A313 / 315: 1.9 eV InGaP cell; and A317: tunnel junction. The germanium substrate shown is a single crystal Ge wafer. Efficiency has increased by 1 to 3.5% each over the last few years, but a significant increase in efficiency has been achieved with each additional junction adding about 4.5%. The benefit of this additional junction is due to the ability of the PVS device to absorb light across different bandgaps, which translates power and allows the use of more useful light.

Mechanically strong, large area and low cost solar cells were required. GaAs based solar cells are one means for improved conversion efficiency and improved external reliability. GaAs has a bandgap of 1.42 eV, close to the most suitable band gap energy value (1.5 eV) for solar energy conversion. Unlike silicon cells, GaAs cells are relatively heat sensitive. Another significant advantage of gallium arsenide and alloys thereof as PV cells is that they can be based on a wide range of designs. It is most notable for high efficiency multijunction solar cells to use thin films of GaAs or group III-V base materials such as GaInP ₂ and GaInAs on bulk Ge single crystal substrates. Ga-As based multi-junction solar cells have a peak measurement efficiency of at least 37%. Germanium substrates have been used in these cells as GaAs, and Ge closely matches the lattice spacing and thermal expansion.

Substrates that are lower in cost than crystalline silicon, including glass and ceramic alumina, are being investigated for III-V compound semiconductor solar cell products. In one example, fused silica and ceramic alumina coated with thick film Ge are used as Ge-coated surrogate substrates for epitaxial growth of high performance GaAs / InGaP solar cells. Germanium films (2-5 μm) are deposited on polycrystalline alumina (p-Al ₂ O ₃ ) to which thermal expansion is matched. The germanium film is then capped with various metals and oxide films and then recrystallized by heat treatment of the property. An average particle size greater than 1 mm is obtained. An epitaxial layer of GaAs is grown using CSVT technology on this large grain (> 1 mm) thin (~ 2 μm) Ge layer. Such GaAs / Ge / ceramic structures have been proposed as starting points for tandem junction devices.

Having a III-V semiconductor thin film solar cell directly on the cover glass is very useful in that it can reduce the weight of the substrate and reduce the overall process cost. Substantially the solar cell will have a configuration that takes incident solar radiation on the cover glass substrate side.

The researchers studied deposited polycrystalline thin films on glass substrates for space solar cell applications. The crystalline properties limit the performance of the III-V solar cells with polycrystalline films. In other words, any structure described above on inexpensive glass substrates cannot reach GaAs with high efficiency (> 30%). Therefore, processes and products based on low cost and transparent glass substrates are required to overcome the problems associated with the prior art.

Derived from the semiconductor world of microelectronics, for ease of presentation, the discussion that follows will often be for semiconductor-on-insulator (SOI) structures. Reference to this particular type of SOI structure is intended to facilitate the description of the present invention and should not be construed to limit the scope of the invention in any way. The SOI abbreviation is generally used herein to refer to a semiconductor-on-insulator structure, and is not limited to, but includes a silicon-on-insulator structure, for example a silicon-on-glass (SiOG) structure. Likewise, the abbreviation SiOG generally refers to a semiconductor-on-glass structure, but is also used to refer to a silicon-on-glass structure, although not limited thereto. The nomenclature of SiOG is also intended to include semiconductor-on-glass-ceramic structures, but is also used with the intention to include, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI includes a SiOG structure.

Various methods of obtaining a wafer of SOI structure include: (1) epitaxial growth of silicon (Si) on a lattice-matched substrate; (2) A method of bonding a single crystal silicon wafer to another silicon wafer having a SiO ₂ oxide layer grown thereon and polishing or etching the top wafer with a single crystal silicon layer of, for example, 0.05 to 0.3 microns (50-300 nm). ; And (3) ion-implantation methods, wherein the ions (eg hydrogen or oxygen ions) are buried oxide layers in a silicon wafer topping with Si, for example in the case of oxygen ion implantation. It is implanted to form a thin film, or as in the case of hydrogen ion implantation, to separate (peel) the thin Si layer from one silicon wafer to bond another Si wafer to the oxide layer.

Chemical mechanical polishing (CMP) can also be used to process the SOI structure after the thin silicon film is stripped from the silicon material wafer. Disadvantageously, however, the CMP process does not remove material uniformly across the surface of the thin silicon film during polishing. Typical surface non-uniformity (standard deviation / mean removal thickness) is in the 3-5% range for semiconductor films. As the thickness of the more silicon surface is removed, the change in its film thickness deteriorates accordingly.

In contrast to the microelectronic applications of SOI structures, photovoltaic structures are more durable against such defects, although such defects may adversely affect the performance of the photovoltaic cell in some way. While finishing processes such as CMP can improve surface properties, defect-durable photovoltaic structures lead to cost overuse. Therefore, incorporating the benefits of advances in SOI structure fabrication into the needs of photovoltaic structure fabrication would be desirable while minimizing the drawbacks in related SOI structure fabrication advances.

Summary of the Invention

In connection with one or more embodiments of the present invention, systems, methods, and apparatuses for forming a photovoltaic device include forming a release layer and transferring it to an insulator structure. The exfoliation layer may be formed from a donor semiconductor wafer. The donor semiconductor wafer and release layer may preferably comprise a substantially single crystal semiconductor material. The release layer may preferably comprise one or more photovoltaic device layers, eg, conductive layers, formed prior to transfer to the insulating substrate. Transferring of the exfoliation layer may comprise electrolytically forming a bipolar bond between the exfoliation layer and the insulating substrate, and then separating the exfoliation layer from the donor semiconductor wafer using thermo-mechanical stress. It may include. One or more photovoltaic device layers may also be formed in or on the release layer after the release layer is transferred to the insulating substrate. One or more finishing processes may be performed before or after the release of the release layer, and the action of the finishing process may form a photovoltaic device layer.

According to one or more embodiments of the present invention, systems, methods, and apparatus for forming a photovoltaic semiconductor-on-insulator structure include forming a photovoltaic structure foundation on a donor semiconductor wafer, insulating the photovoltaic structure foundation. Transferring to a substrate, and depositing a plurality of photovoltaic structure layers on the PV foundation. The transferring step may include bipolar bonding an insulator structure to the photovoltaic structure foundation, and separating the photovoltaic structure foundation from the donor semiconductor wafer.

According to one or more embodiments of the present invention, a system, method and apparatus for forming a photovoltaic semiconductor-on-insulator structure comprises forming a partially completed photovoltaic cell on a donor semiconductor wafer, the partially completed Transferring the photovoltaic cell to the insulating substrate. The transferring step may include anodic bonding a partially completed photovoltaic cell to the insulator structure, and separating the partially completed photovoltaic cell from a donor semiconductor wafer.

According to one or more embodiments of the present invention, a system, method, and apparatus for forming a photovoltaic device includes introducing a donor semiconductor wafer into an ion implantation process to form a release layer in the donor semiconductor wafer; Bonding the release layer to an insulating substrate; Separating the exfoliation layer from the donor semiconductor wafer; The release layer acts as a photovoltaic structure foundation and includes forming a plurality of photovoltaic structure layers on the photovoltaic structure foundation.

According to one or more embodiments of the present invention, a system, method, and apparatus for forming a photovoltaic device includes introducing a donor semiconductor wafer into an ion implantation process to form a release layer in the donor semiconductor wafer; Forming a partially completed photovoltaic cell on the release layer; Bonding the release layer to an insulating substrate; Separating the exfoliation layer with the partially completed photovoltaic cell from a donor semiconductor wafer to expose one or more cleaved surfaces; And introducing the at least one cleaved surface into a finishing process.

According to one or more embodiments of the present invention, a system, method and apparatus for forming a photovoltaic device includes forming a partially completed photovoltaic cell on a donor semiconductor wafer; Introducing the partially completed photovoltaic cell and the prepared donor surface of the donor semiconductor wafer into an ion implantation process to form a release layer in the donor semiconductor wafer; Bonding the release layer to an insulating substrate; Separating the exfoliation layer with the partially completed photovoltaic cell from the donor semiconductor wafer to expose one or more cleaved surfaces; And introducing the at least one cleaved surface into a finishing process.

In at least one embodiment, the bonding step comprises: heating at least one of the insulating substrate and the donor semiconductor wafer; Contacting the insulating substrate directly or indirectly with a release layer of the donor semiconductor wafer; And inducing coupling by applying a voltage potential across the insulating substrate and the donor semiconductor wafer. The temperature of the insulating substrate and the semiconductor wafer may be raised to within about 150 ° C., which is a strain point of the insulating substrate. The temperature of the insulating substrate and the semiconductor wafer will be raised to different levels. The voltage potential across the insulating substrate and the donor semiconductor wafer may be about 100 to 10000 volts. Stress is induced by cooling the bonded insulating substrate, the exfoliation layer and the donor semiconductor wafer, such that in an ion-defect phase where fracture establishes the boundaries of the exfoliation layer in the donor semiconductor wafer. Practically occurring. Thermal expansion and thermal expansion differential coefficients of the wafers around the ion-defective relative (Vs) cause the exfoliation layer to cleave on the ion-defective. This result corresponds to a thin film of semiconductor bonded to the insulator.

The one or more cleaved surfaces may comprise a first cleaved surface of the donor semiconductor wafer and a second cleaved surface of the exfoliation layer. For the first cleaved surface associated with a donor semiconductor wafer, the finishing process may include preparing the donor semiconductor wafer for reuse. For the second cleaved surface associated with the release layer, the finishing process may include completing the partially completed photovoltaic cell.

According to one or more embodiments of the invention, the new solar cell may be based on a single crystal Ge, Si, or GaAs film on a transparent glass or glass ceramic substrate. For GaAs-based cells, as an additional advantage, a germanium layer may be present between the substrate and the monocrystalline GaAs layer. The germanium layer may be doped to use the substrate as the bottom layer (ie, back contact layer) of the multi-junction solar cell. The glass or glass ceramic substrate may be expansion matched with Ge, Si, GaAs, or Ge / GaAs. Strongly adhered monocrystalline layers of Ge, Si, GaAs, or Ge / GaAs films can be obtained on glass or glass ceramics through the bipolar bonding process described in US Application 2004/0229444.

The process first involves hydrogen or hydrogen and helium implantation of a Ge, Si, or GaAs wafer, in the case of GaAs, followed by the deposition of a germanium film on the surface of the GaAs wafer, possibly. The Ge, Si or Ge-coated GaAs wafer is then bonded with the glass substrate followed by separation of the thin film structure of Ge, Si, GaAs, or Ge / GaAs. The SOG structure thus obtained is polished to remove damaged regions and to expose the high quality single crystal layer of the semiconductor. This SOG structure will then be used as a template for successive epitaxial growth of multiple layers of Si, Ge, GaAs, GaInP ₂ , GaInAs, etc., to form the desired solar cell. The glass added in an expansion match to the semiconductor layer may also have a high strain point sufficient to withstand continuous deposition conditions.

Common photovoltaic structures are called p-type-intrinsic-n-type (PIN), metal-insulator-semiconductor (MIS), what are called "tandem" junction cells, multi-junction cells, and composite pn multiplexing. A layer structure is included, but the invention is not limited to such a structure, depending on the characteristics of the desired product, forming a partially completed photovoltaic cell on the donor semiconductor wafer, such as, for example, a single junction versus multiple junctions. It is within the capabilities of those skilled in the photovoltaic art, and likewise, whether partially completed photovoltaic cells are formed before or after ion implantation is determined by those skilled in the art in view of the proper ion transmission depth in the semiconductor material. .

The donor semiconductor wafer may be part of a structure that includes a substantially single crystal donor semiconductor wafer and optionally includes an epitaxial semiconductor layer located on the donor semiconductor wafer. The exfoliation layer (eg, a layer bonded to the insulating substrate and separated from the donor semiconductor structure) is then formed from substantially a single crystal donor semiconductor wafer material. Or the exfoliation layer may be formed substantially from the epitaxial semiconductor layer (and it may also include a portion of the single crystal donor semiconductor wafer material).

The advantages of one or more embodiments of the invention will be best understood after reading the detailed technical description of the SOI process present. However, primary advantages include: photovoltaic structure changes; Thinner silicon film; More uniform silicone films with higher crystalline properties; Faster manufacturing throughput; Improved manufacturing yields; Reduced pollution; And scalability for large substrates. This advantage naturally corresponds to lower costs.

The photovoltaic structure (PVS) may vary depending on the composite photovoltaic structure that can be produced through a high temperature process on a donor semiconductor wafer. The resulting high performance PVS can then be transferred to a low cost glass substrate and completed, for example, with deposition for any patterning required to complete the remaining layers and circuits.

The present invention allows the use of only semiconductors of the required thickness (about 10 to 30 microns for Si, 1 to 3 microns for direct bandgap semiconductors such as GaAs). Whereas thicker silicon films are then polished and transferred to the insulator substrate which removes the damaged surface, very thin films are difficult to control and there is little material removed in the process as described herein. This directly allows to be transferred with the deposited additional thickness or later grown thickness.

Uniform films are very desirable. That is, since there is almost no material removed in the process, the uniformity of the silicon film thickness is determined by ion implantation. This shows very uniform in certain embodiments with a standard deviation of about 1 nm. On the other hand, the polishing process generally exhibits a deviation of the film thickness of 5%.

As is constantly required, faster throughput is important. However, the polishing technique specified for producing SiOG has a treatment time of tens of minutes, and furnace annealing may take several hours. For more uniform films, the need in photovoltaic cells for polishing or roannel has been reduced.

Improved manufacturing yields are also important for waste and cost savings. By avoiding wire-saw kerf losses, waste will be significantly reduced. Likewise, expensive donor semiconductor wafers will be polished and reused several times. By using thin film, the material consumed will likewise be significantly reduced. If polishing of the SOI structure is avoided, the overall manufacturing yield is expected to be increased. This is especially true if the polishing process is expected with low process yields. The process window is expected to be large due to the crystalline nature of the film and therefore the yield is expected to be high.

Based on the sensitive nature of the SOI, contamination will adversely affect performance and therefore it is highly desirable to reduce contamination. With this in mind, avoiding the need for polishing by abrasive slurries that reduce the thickness of the layer is to reduce potential contamination. Avoiding the need for furnace annealing will also prevent the spread of contamination that can occur during long thermal annealing processes. This will play an important role in view of the efficiency of photovoltaic devices.

This process can be scaled up to large process scale. This scalability increases with increasing substrate size demand, which potentially consumes product life. Solar panels are often large to maximize the available space, resulting in larger photovoltaic cells, and fewer photovoltaic cells need to be contacted to form large solar panels. On the other hand, surface polishing and furnace annealing become more different for larger substrate sizes.

In particular, important advantages of the preferred embodiments of the present invention are 1) other more expensive semiconductor substrates (eg, silicon and continuous GaAs growth for Ge layers, as previously used), but as described in the prior art. Use of low cost, expansion-matched glass or glass-ceramic substrates, as compared to such thermally mismatched ceramic materials; 2) The presence of multiple monocrystalline template layers of Si, Ge, or GaAs / Ge on glass substrates, which is lattice matched for solar cells with high efficiency, unlike polycrystalline templates used in the prior art ) And is used as a template to form a semiconductor layer with very few defects; 3) The flexibility of the module manufacturing is included based on the transparency of the substrate.

Other aspects, features, advantages, and the like will become apparent to those skilled in the art in view of the accompanying drawings and the detailed description of the invention.

Unless otherwise specified, it is to be understood that all numbers used to express weight percents, dimensions, and specific property values for ingredients in this specification and claims are to be modified by the term “about”. It is also to be understood that the precise numerical values used in this specification and claims constitute an additional embodiment of the invention. The numerical values disclosed in the examples have been tried to ensure accuracy. However, any measured numerical value may be inherently mistaken as a standard deviation found in each measurement technique.

By "crystalline semiconductor material" is meant a material that is either completely crystalline or substantially crystalline and which is intentionally or accidentally introduced into or without defects and / or dopants therein. It thus comprises (i) a precursor material for forming a material having semiconducting properties, the semiconductor or non-semiconductor itself, and (ii) a semiconducting material formed by, for example, a doping precursor material. The crystalline semiconductor material can be monocrystalline or polycrystalline. In practice, semiconducting materials generally include internal or surface defects, such as lattice defects or grain boundaries, which are added essentially or intentionally as at least a part. The term “substantially crystalline” also reflects the fact that a particular dopant may affect or even distort the crystal structure of the semiconductor material.

4, 5 and 6 (sometimes referred to collectively as FIGS. 4-6), PVS changes 100A, 100B, 100C of photovoltaic SOI structure 100 in accordance with one or more embodiments of the present invention. Is showing each). Photovoltaic SOI structure 100 may be referred to as PV SOI structure 100 or simply PVS 100. In the figure, SOI structure 100 is an example of an SIOG structure. The SiOG structure 100 includes an insulating substrate 101 made of glass, a photovoltaic structure foundation 102 (FIG. 4), an ion transport region 103, a back contact layer 104, a p-type semiconductor layer 106 ), an n-type semiconductor layer 108 and a conducting window layer 110. The SiOG structure 100 has suitable uses in connection with photovoltaic devices.

Conductive window layer 110 is a layer of electrically conductive material that acts as an ohmic contact. The conductive window layer may be translucent, transparent or semi-transparent. An exemplary material is indium tin oxide, which is generally a material formed by reactive sputtering of an In—Sn target in an oxidizing atmosphere. In place of indium tin oxide, for example, aluminum-doped zinc oxide, boron-doped zinc oxide, or even carbon nanotubes may be included. Indium tin oxide (ITO, or tin-doped indium oxide) is a mixture of indium (III) oxide (In2O3) and tin (IV) oxide (SnO ₂ ), typically 90% by weight of In ₂ O ₃ , 10% by weight May be% SnO ₂ . It is transparent and colorless in thin layers. In bulk form, yellow to grey. The main feature of indium tin oxide is a combination of electrical conductivity and optical transparency. However, while high charge carrier densities increase the conductivity of the material, transparency is reduced, so a compromise must be reached during film deposition. Thin films of indium tin oxide are most commonly deposited on surfaces by the scope of electron beam evaporation, physical vapor deposition, or sputtering techniques.

The semiconductor material layers 106 and 108 may be substantially in the form of a single crystal material. The term “substantially” refers to the layer 106 in view of the fact that the semiconductor material generally comprises internal or surface defects, such as lattice defects or grain boundaries, added essentially or intentionally as at least a part. Used to describe 108. The term substantially also reflects the fact that a particular dopant may affect or even distort the crystal structure of the semiconductor material. In particular, the p-type semiconductor layer 106 includes a p-type dopant, whereas the n-type semiconductor layer 108 includes an n-type dopant. The p-type layer 106 is thicker than the n-type layer 108 in all cases where most electron hole pairs are desired to be formed in the p-type layer 106.

For the purposes of discussion, it is assumed that semiconductor layers 106 and 108 are formed from silicon, unless otherwise noted. However, it is understood that the semiconductor material may correspond to any form of silicon-based semiconductor or semiconductor classification such as, for example, III-V, III-IV, and the like. Examples of such materials include silicon, germanium-doped silicon (SiGe), silicon carbide (SiC), germanium, gallium arsenide (GaAs), gallium phosphide (GaP), and indium phosphide (InP).

The back contact layer 104 may be a conductive layer, such as a conductive metal-based or metal oxide-based layer. The back contact layer allows resistive contact, i.e., the area on the fabricated semiconductor device, so that the current-voltage (I-V) curve of the device is linear and symmetrical. The back contact material may be selected for thermal robustnes in contact with Si. For example, the back contact layer 104 may be a film based on aluminum or silicide, for example titanium disilicide, tungsten disilicide, or nickel silicide, examples of which are discussed below. The silicide-polysilicon combination has better electrical properties than polysilicon alone and does not melt in subsequent processes.

The back contact layer 104 is formed by, for example, deposition, which is for example LPE, CVD, or PECVD. Mesotaxy or epitaxy may also be used. Whereas epitaxy is the growth of a matching phase over the substrate surface, mesotaxy is the growth of a crystallographicall matching phase underneath the surface of the host crystal. In this process, ions are implanted with sufficiently high energy, dosed into the material to form a second phase layer, and the temperature is controlled so that the crystal structure of the target is not destroyed. The crystal orientation of the layer can be processed to match the orientation of the target, although the exact crystal structure and lattice constants are very different. For example, after nickel ions are implanted into a silicon wafer, the nickel silicide layer can be grown at a portion where the crystal orientation of the silicide matches the orientation of the silicon.

The use of epitaxy or mesotaxy for the formation of back contact layer 104 requires that the exfoliation layer 122 discussed in FIGS. 7-9 and 11 comprise an epitaxial or mesoscopic layer. As long as the back contact layer 104 and the semiconductor layer are formed thereon, it may be considered as a conceptual interface between the structure 100A disclosed in FIG. 4 and the structures 100B and 100C disclosed in FIGS. 5 and 6. will be. The semiconductor layer alone will serve as the photovoltaic structure foundation (PVSF) 102 in FIG. 4, but the combination of the semiconductor layer and the back contact layer 104 is partially completed as introduced in FIGS. 8 and 13. Can be regarded as PVS 124. Thus, forming the back contact layer 104 prior to the bipolar bonding step (step 208) using epitaxy or mesotax or ion implantation is transferred to the substrate 101 as in processes 200B and 200C. Forming the partially completed PVS 124 and then back contact layer 104 using epitaxy or mesotax or ion implantation after the transferred PVSF 102 and then exfoliation separation (step 210). Forming follows process 200A. Likewise, back contact layer 104 may be formed by heavy doping of PVSF 102 after exfoliation separation. Such strong doping can generally be carried out by ion implantation.

Further, if the back contact layer 104 is deposited on top of the PVSF 102 after delamination separation (step 210), the strain 100A PVS 100 will appear. Instead, if PVSF 102 is doped before or after mesotax as a p-type semiconductor, and if back contact layer 104 is formed by mesotax, variation 100A or PVS 100, similar to 100B, will appear. If the depth of mesoscopic growth of the back contact layer 104 is within the middle of the PVSF 102, the PVSF 102 layer will remain below the back contact layer 104, within a change 100A. If the depth of mesoscopic growth of the back contact layer 104 reaches the bonding surface 126 of the PVSF 102, then any layer of the PVSF 102 is within the change 100B, such that the back contact layer 104 Will not remain under).

As long as the conductive layer is formed on or in the release layer 122, the conductive layer may be formed by epitaxial, mesotax, ion implantation, doping, vapor transfer, vapor deposition, or the like. 122) will be integral. When the conductive layer is formed on or in the release layer 122 before the release layer 122 is bonded to the insulating substrate 101, the release layer 122 may be formed by the release layer 122. Will bond to the insulating substrate 101 when bonded to the substrate. In other words, the conductive layer is formed close to the release layer 122 facing the insulating substrate, such that a final conductive layer will be between the insulating substrate and the release layer. If the release layer 122 is initially bonded with the insulating substrate 101 and then the conductive layer is subsequently formed on or in the release layer 122, the conductive layer is the insulating substrate 101. It will be on or near the release layer 122 on the opposite side, and thus will be located at the distal end of the insulating substrate 101. Similarly, after the release layer 122 is bonded to the insulation substrate 101, all of the photovoltaic device layers formed therein, in or on the release layer 122 are terminated at the end of the insulation substrate 101. Will be located at

As discussed in more detail in FIGS. 15-17, the ion migration region 103 is in the PVS foundation, within the insulating substrate 101 and the layer bonded to the insulating substrate 101, ie, variation 100A. 102; Within change 100B, back contact layer 104; Or on either side of the bipolar bond between the conductive window layers 110 at a change 100C. The ion migration region 103 is due to the bipolar bonding process described in FIG. This ion migration region 103 did not exist in the conventional photovoltaic structure technology.

Unlike changes 100B and 100C in FIGS. 5 and 6, change 100A in FIG. 4 includes a PV structure foundation 102. The photovoltaic structure foundation 102 may occur when the release layer 122 is transferred to the insulating substrate 101 without any additional layer (s) leading to the partially completed PVS 124 (PCPVS). In essence, it is believed that the release layer 122 becomes the PVSF 102 upon bonding to the insulating substrate 101. For example, PVSF 102 will preferably comprise a substantially monocrystalline semiconductor layer, as derived from donor wafer 120 introduced in FIGS. 7 and 10.

The insulating substrate 101, here the glass substrate 101, may be formed from oxide glass or oxide glass-ceramic. Although not required, the embodiments described herein may include glass oxide or glass-ceramic showing strain points up to about 1000 ° C. As is common in the art of making glass, the strain point is the temperature at which the glass or glass-ceramic has a viscosity of 1014.6 poise (1013.6 Pa.s). Between oxidized glass and oxidized glass-ceramic, the glasses may have the advantage of being simpler to manufacture, thus allowing them to be used for a wider range of applications and at lower costs.

As an example, the glass substrate 101 may be formed from a glass substrate containing alkaline earth ions, for example, Glass No., all supplied by Corning Corporation (Corning, New York, USA). Substrate manufactured from 1737 and Eagle 2000. Such glass materials have other uses, in particular, for example, in the manufacture of liquid crystal displays.

The glass substrate may have a thickness in a range of about 0.1 mm to about 10 mm, for example, in a range of about 0.5 mm to 3 mm. In some SOI structures, an insulating layer having a thickness equal to or greater than about 1 micron (ie, 0.001 mm or 1000 nm) may be used at high frequencies, for example, in a standard SOI structure having a silicon / silicon dioxide / silicon shape. It is desirable to avoid parasitic capacitive effects that occur when operated. In the past, such thicknesses were difficult to achieve. According to the present invention, an SOI structure having an insulation layer thicker than about 1 micron can be easily achieved by simply using a glass substrate 101 having a thickness equal to or greater than about 1 micron. The lower limit on the thickness of the glass substrate 101 will be about 1 micron, or 1000 nm.

In general, the glass substrate 101 should be thick enough to support the semiconductor layers 106 and 108 through a continuous process in the photovoltaic SiOG structure 100 as well as the bonding process step. There is no theoretical upper limit on the thickness of the glass substrate 101, but the thickness beyond that required for the supporting action or required for the ultimate photovoltaic SiOG structure 100 is that the larger the thickness of the glass substrate 101 is, It would not be advantageous because at least some of the process steps become more difficult to achieve in forming the photovoltaic SiOG structure 100.

The oxide glass or oxide glass-ceramic substrate 101 may be silica-based. Thus, the mole percent of SiO 2 in the oxidized glass or oxide glass-ceramic may be at least 30 mole percent, and at least 40 mole percent. In the case of glass-ceramic, the crystalline phase may be mullite, cordierite, ileite, spinel or other crystalline phases known in the glass-ceramic art. Non-silica based glass and glass-ceramic may be used in the practice of one or more embodiments according to the present invention but are generally not advantageous because they have higher costs or exhibit poor performance characteristics.

Likewise, in some applications, for example in SOI structures employing non-silicon-based semiconductor materials, glass substrates that are not oxide based, such as non-oxide glass, are preferred, but generally more It is not advantageous because of the high cost. As will be discussed in more detail, in one or more embodiments, the glass or glass-ceramic substrate 101 may comprise one or more semiconductor material (eg, silicon, germanium, etc.) layers (potentially 102, bonded directly or indirectly). It is designed to match the coefficient of thermal expansion (CTE) of 104, 106, 108 or 110. CTE matching allows to exhibit desirable mechanical properties during thermal cycling of the deposition process.

In photovoltaic applications, glass or glass-ceramic 101 may be transparent in the visible, near-ultraviolet, and / or infrared wavelength ranges, for example, glass or glass ceramic 101 in the 350 nm to 2 micron wavelength range. It can be transparent. Glass having transparency or at least translucency is particularly important at change 100C, where light is incident on the insulating substrate 101 before reaching the rest of the PV structure 100C. However, at the changes 100A and 100B, the light does not enter the insulating substrate 101, and therefore it is irrelevant whether the insulating substrate 101 is transparent as well as translucent, in which case the insulating substrate 101 This other criterion, cost, is not a problem, but is chosen based in particular on CTE.

Although the glass substrate 101 may be made of a single glass or glass-ceramic layer, a laminate structure may also be preferably used. If a laminate structure is used, the laminate layer (eg 102, 104 or 110) closest to the layer bonded thereto will have the properties discussed herein for the glass substrate 101 made of a single glass or glass-ceramic. Can be. Layers further away from the bonded layer may also have such properties but will have relaxed properties since they do not interact directly with the bonded layer. In the latter case, the glass substrate 101 is believed to terminate when the characteristics characterized for the glass substrate 101 are no longer satisfied.

7, 8 and 9 (often referred to as FIGS. 7-9 at one time), the process steps shown to produce the PV structure 100 may be performed in accordance with one or more embodiments of the present invention. Process 200A is shown in FIG. 7, process 200B is shown in FIG. 8, and process 200C is shown in FIG. 9. In this block diagram the individual execution (step) has the following meaning:

202: prepare a surface of a donor semiconductor wafer;

203: Introducing the donor semiconductor wafer into an ion implantation process;

204: introducing the donor semiconductor wafer to relaxed oxidation;

205: form a partially completed PVS;

206: introducing the partially completed PVS and donor semiconductor wafer into an ion implantation process;

207: forming a bipolar bond between the photovoltaic structure (or partially completed photovoltaic) foundation and the glass;

210: separate the glass layer / PVSF / peel layer from the donor semiconductor wafer;

212: Introduce the donor semiconductor wafer and / or PVS foundation into a finishing process.

10-18 illustrate structures close to the intermediate and final structures that may be formed by performing the processes of FIGS. 7, 8 and 9. In Fig. 10, the arrows indicate the surface manufacturing action. In FIG. 11, the arrows indicate the flow of ions (eg hydrogen ions) implanted and their general direction according to certain embodiments of the invention. In FIG. 12, the arrows indicate, for example, an O ₂ plasma or other material or action and its general orientation in the surface finishing process for the exfoliation layer according to certain embodiments of the invention. In FIG. 13, the arrows indicate materials and / or actions, and general deposition techniques for forming back contact layers and / or conductive windows in certain embodiments of the present invention. In FIG. 14, the arrows indicate the material (eg dopant) and / or action (doping process) and the general direction for the doping of each layer.

In actions 202 of FIGS. 7-10, the prepared donor surface 121 of the donor semiconductor wafer 120 is prepared by, for example, polishing, cleaning, or the like, and is suitable for bonding to a continuous layer of PVS. To produce a flat and uniform donor surface 121. The manufactured donor surface 121 forms the underside of the PV structure foundation 102 or the semiconductor layers 106 and 108. For the purposes of this discussion, the semiconductor wafer 120 is discussed above that any other suitable semiconductor material may be used, but may be a substantially monocrystalline Si wafer doped (n-type or p-type).

In either operation 203 for processes 200A and 200B or operation 206 for process 200C, as shown in FIG. 11, the exfoliation layer 122 is formed of an ion implantation surface 121i, that is, a manufactured donor surface 121 or Any layer formed on the manufactured donor surface 121 is formed by introducing into one or more ion implantation processes to form a weakened region below the manufactured donor surface 121 of the donor semiconductor wafer 120. Embodiments of the present invention are not particularly limited to the method of forming the exfoliation layer 122, but one suitable method is that at least the donor surface 121 of the donor semiconductor wafer 120 is introduced into a hydrogen ion implantation process. The formation of the release layer 122 in the semiconductor wafer 120 is indicated.

Implantation energy can be adjusted using conventional techniques to achieve the approximate thickness of release layer 122. For example, hydrogen ion implantation can be used even though other ions or multiple ions thereof, such as boron + hydrogen, helium + hydrogen, or other ions known in the literature on exfoliation can be used. That is, other known or later developed technologies suitable for forming the release layer 122 may be employed without departing from the spirit or scope of the present invention.

Depending on the parameters of the PV SOI structure 100, the number and thickness of the layers on top of the donor surface 121 produced, and the potential use of any intermediate manufacturing step, such as CMP or FA, the release layer 122 is possible and / or Or preferably thick or thin. If various design constraints are necessary for the exfoliation layer 122 to be thicker than desired, for example, for use in the microelectronics art, known mass removal methods, such as CMP or polishing, may operate. It can be used to reduce the thickness of layer 122 after peeling off. However, using a scalpel process adds time and cost to the overall manufacturing process and may not be necessary in the PVS 100. For example, at change 100A, the PVSF 102 layer will not need to be thin or thick, preferably PVSF 102 is thick enough to serve as a stable basis for later finishing processes, It is to reduce the material and thus the cost.

The opposite problem may further occur in the PV structure 100. In other words, the release layer becomes too thin. At variations 100B and 100C, thicker Si layers are preferred for PVS 100, since thicker Si layers will absorb more light and increase its efficiency. Preferably the energy required to form the thick release layer will exceed the available device parameters, so that additional Si will be epitaxially grown or deposited after the release layer 122 is formed. The additional Si may be added to the release layer 122 before or after being transferred to the glass substrate 101. If added, the Si addition will be part of the formation of the partially completed PVS 124, but if added, the Si addition will be part of the finishing process. Similarly, the semiconductor layer will be added to PVS 100A after PVSF 102 and back contact layer 104 are located on substrate 101.

In either operation 204 for processes 200A and 200B, or action 207 for process 200C, as also shown in FIG. 12, ion implantation surface 121i, ie, the manufactured donor surface 121 and the manufactured Any layer formed on the donor surface 121 and on the donor semiconductor wafer 120 may be processed, for example, to reduce the hydrogen ion concentration at the ion implantation surface 121i. For example, the donor semiconductor wafer 120 may be washed and washed, and the bonding surface 126 of the release layer 122 may be introduced to relaxed oxidation. The relaxed oxidation treatment includes treatment with oxygen plasma, ozone treatment, hydrogen peroxide, hydrogen peroxide and ammonia, hydrogen peroxide and acid or a combination of these processes. During this treatment, hydrogen-terminated surface groups are oxidized to hydroxyl groups, which in turn are expected to make the surface of the bonding surface 126 hydrophilic. Such treatment will be carried out at room temperature in the case of oxygen plasma and at temperatures of 25 to 150 ° C. for ammonia or acid treatment.

Operations 205 shown in FIGS. 8 and 9, and also FIGS. 13 and 14, include forming partially completed PVS 124 on the donor semiconductor wafer 120. The partially completed PVS 124 may be formed after the release layer 122 is formed as in process 200B or before the release layer 122 is formed as in process 200C. After both the release layer 122 and the partially completed PVS 124 are formed, however, the release layer 122 substantially forms part of the partially completed PVS 124. The exposed surface of the partially completed PVS 124 will be a bonding surface 126 for bonding to the glass insulating substrate 101, in operation 208.

Referring to Figures 13 and 14 (sometimes referred to at once as Figures 13-14), the donor semiconductor wafer 120 may be treated as part of the formation of a partially completed PVS 124. 13-14 show that a release layer 122 has already been formed on the manufactured donor surface 121 of the donor semiconductor wafer 120 at the additional processing required to form the partially completed PVS 124. Doing. Many different operations can be taken to form the partially completed PVS 124. For example, the partially completed PVS 124 may have the back contact layer 104 added as shown in FIG. 13, as in change 100B, or the addition of conductive window layer 110, as in change 110B, or As shown in FIG. 14, this may include the use of an intermediary doping step.

FIG. 13 illustrates the addition of either the back contact layer 104 as in variation 100B or the conductive window layer 110 as in variation 100C, in accordance with one or more embodiments of the present invention. At a high level, these two processes are similar enough to be shown using one block diagram. For example, a simplified deposition process such as CVD or PECVD is shown, but it is meant that the diagram can represent any possible process, such as epitaxy and mesotax. Each of the back contact 104 or conductive window layer 110 is bonded to the partially completed PVS 124 and the glass substrate 101 as long as the bipolar bonding process of operation 208 exhibits a better effect in this continuous process. Previously, rather than being deposited directly on the glass substrate 101, it is desirable to deposit on the partially completed PVS 124. Another advantage of depositing one of these on partially completed PVS 124 is the process limitations required to deposit such a layer directly on glass substrate 101 as long as it is attached to donor semiconductor wafer 120. May be mitigating, which may be more sensitive to extreme conditions.

14 shows the ion implantation surface 121i of the release layer 122 to be doped to form a subsurface n-p junction 128. Depending on whether a change 100B or 100C is required, for example, semiconductor layers 106 and 108 may be fabricated from doped Si boules that receive opposite doping on their surface. In an exemplary embodiment of variation 100B, the n-type doped donor semiconductor wafer 120 may be doped with a p-type dopant on its surface to form a subsurface n-p junction. Conversely, in an exemplary embodiment of variation 100C, the p-type doped donor semiconductor wafer 120 may be doped with an n-type dopant on its surface to form a subsurface n-p junction.

In operations 208 of FIGS. 7-9 and 15, the glass substrate 101 may be bonded with the bonding surface 126 of the release layer 122 / PVSF 102 / partially completed PVS 124. Suitable bonding processes are disclosed in US patent application 2004/0229444, which is incorporated herein by reference in its entirety. This process portion is known as bipolar bonding, electrolysis, and the formation of bonding as an electrolysis method, and / or bipolar bonding by electrolysis is discussed below. In an anodic bonding / electrolysis process, suitable surface cleaning may be performed on the glass substrate 101 (and bonding surface 26 / peel layer 122). Thereafter, the intermediate structure is contacted directly or indirectly to achieve the arrangement shown schematically in FIGS. 15-16.

Before or after the contact, the structure comprising the donor semiconductor wafer 120, the exfoliation layer 122 / PVSF 102 / partially completed PVS 124, and the glass substrate 101 have different temperature gradients. Heated under). The glass substrate 101 will be heated to a higher temperature than the donor semiconductor wafer 120 and the exfoliation layer 122 / PVSF 102 / partially completed PVS 124. As one example, the temperature difference between the glass substrate 101 and the donor semiconductor wafer 120 (and the exfoliation layer 122 / PVSF 102 / partially completed PVS 124) is such that the difference is about 100 to It may be as high as 150 ℃, but at least 1 ℃. This temperature difference is desirable for glass having a coefficient of thermal expansion that matches the donor semiconductor wafer 120 (eg, matched for CTE of silicon). This is because the separation layer 122 is later separated from the donor semiconductor wafer 120 due to thermal stress. The glass substrate 101 and the donor semiconductor wafer 120 may have a temperature within about 150 ° C., which is a strain point of the glass substrate 101.

When the temperature difference between the glass substrate 101 and the donor semiconductor wafer 120 is stabilized, mechanical pressure is applied to the intermediate assembly. The pressure range can be between about 1 and about 50 psi. Higher application of pressure, for example a pressure of 100 psi or more, will result in the breaking of the glass substrate 101. Suitable pressures will be determined in terms of manufacturing parameters, for example in terms of the materials used and their thicknesses.

A voltage is then applied across the intermediate assembly, for example with the donor semiconductor wafer 120 at the positive electrode and the glass substrate 101 at the negative electrode. Application of the voltage potential causes the alkali or alkaline earth ions in the glass substrate 101 to move further from the semiconductor / glass interface to the glass substrate 101. This achieves two functions: (i) an interface free of alkali or alkaline earth ions is formed; In addition, (ii) the glass substrate 101 becomes very reactive and strongly bonds with the release layer 122 of the donor semiconductor wafer 120.

In operations 210 of FIGS. 7-9 and 15, after the intermediate assembly remains under the conditions for a period of time (eg, about 1 hour or less), the voltage is removed and the intermediate assembly is allowed to cool to room temperature. . The donor semiconductor wafer 120 and the glass substrate 101 are then separated, which is a relatively thin release layer 122 / PVSF 102 / partially completed formed of the semiconductor material of the donor semiconductor wafer 120 to be bonded. Any peeling process may be included unless it is not already completely to obtain the glass substrate 101 with the PVS 124. The separation will be accomplished by fracture of the ion implantation region due to thermal stress. Instead, or in addition, mechanical stresses, such as waterjet or laser cutting, or chemical etching, may be used to facilitate such separation.

Referring to Fig. 16, the ion migration region 103 mentioned in Figs. 4-6 is shown in more detail. The detailed structure is any one of the PVSF 102 in FIG. 4, the back contact 104 in FIG. 5, and the conductive window layer 110 in FIG. 6, for the glass substrate 101 and the release layer 122. At the interface between the layers thereon it is particularly associated with an anodic bond region. The bonding process (operation 208) transforms the interface between the exfoliation layer 122 and the glass substrate 101 to the interface region 300. The interface region 300 preferably includes a hybrid region 160 and a depletion region 230. The interface region 300 may also include one or more cation-up regions around the distal edge of the depletion region 230.

The hybrid region 160 is based on the enhanced oxygen concentration for thickness T 160. For example, when bonding the conductive window layer 110, this hybrid region 160 can be enhanced by stoichiometric oxygen depleted compositions starting to promote oxygen transport from the glass substrate 101. This thickness will be specified in terms of the reference concentration to oxygen at the reference surface 170 within the release layer 122 / PVSF 102 / partially completed PVS 124. The reference surface 170 is substantially parallel to the bonding surface between the glass substrate 101 and the release layer 122 / PVSF 102 / partially completed PVS 124 and separated from the surface by a distance DS1. do. Using the reference surface 170 and thickness T 160 of the hybrid region 160 will generally satisfy the following relationship.

T160≤200nm,

Where T160 is the distance between the bonding surface 126 and the surface, (i) the surface substantially parallel to the bonding surface 126, and (ii) the surface furthest from the bonding surface 126 that satisfies the following relationship:

CO (x) -CO / Ref≥50percent, 0≤x≤T160,

Where CO (x) is the concentration of oxygen as a function of the distance x from the bonding surface 126, CO / Ref is the concentration of oxygen on the reference surface 170, and CO (x) and CO / Ref are atoms It is expressed as a percentage.

In general, the T160 will be substantially smaller than 200 nanometers. For example, in the order of about 50 nanometers to about 100 meters. It should be noted that CO / Ref will generally be zero and thus the relationship will most likely be modified to:

CO (x) ≧ 50 percent, 0 ≦ x ≦ T160.

With respect to the depletion region 230, the oxidized glass or oxidized glass-ceramic substrate 101 moves in the direction of the applied electric field, ie away from the bonding surface 126 and at least moving to the glass substrate 101. Some cation is preferably included. Alkali ions, such as Li ⁺¹ , Na ⁺¹ , and / or K ⁺¹ are more than other kinds of cations, for example alkaline-earth ions, in which they are commonly incorporated in oxidized glass and oxidized glass-ceramics. Since it generally has a high mobility rate, it is a cation suitable for this purpose.

However, oxide glass and oxide glass-ceramic having cations other than alkali ions, for example, oxide glass and oxide glass-ceramic having only alkaline-earth ions, can be used in the realization of the present invention. The concentrations of alkali and alkaline-earth ions vary over a very wide range and representative concentrations are between 0.1 and 40% by weight on an oxide basis. Preferred concentrations of alkali and alkaline-earth ions are from 0.1 to 10% by weight on an oxide basis for alkali ions and 0-25% by weight on an oxide basis for alkaline-earth ions.

The electric field applied in the bonding step (operation 208) further moves the cations to the glass substrate 101 forming the depletion region 230. The formation of the depletion region 230 is particularly desirable when the oxide glass and the oxide glass-ceramic contain alkali ions, since such ions are known to interfere with the operation of the semiconductor device. Alkali-earth ions, such as Mg ⁺² , Ca ⁺² , Sr ⁺² , and / or Ba ^{+2, may} also interfere with the operation of the semiconductor device, so that the depletion region preferably reduces the concentration of such ions. Do.

It has been found that once formed the depletion region 230 is even stable for the time when the PV structure 100 is heated to a temperature which is comparable or even elevated to some degree higher than that used in the bonding process. Depletion regions 230 formed at elevated temperatures are particularly stable at normal operating and formation temperatures of PV structures. This consideration confirms that alkali and alkaline-earth ions will not be diffused back from the oxide glass and oxide glass-ceramic 101 to the semiconductor material 104 during the use or further processing of the device, which is a It is an important advantage derived from using an electric field as part.

In selecting operating parameters to achieve strong bonding, the operating parameters required to achieve a depletion region 230 of desired width and preferably reduced cation concentration for all cations under consideration are readily available to those skilled in the art from this disclosure. Can decide. If provided, the depletion region 230 corresponds to the technical features of the PV structure 100 fabricated in connection with one or more embodiments of the invention.

As shown in FIG. 17, after separation, the resulting structure will comprise a glass substrate 101 and a release layer 122 of semiconductor material bonded thereto. Immediately after exfoliation, the cleaved surface 123 of the SOI structure may have excessive surface stiffness 123A (shown schematically in FIG. 17), and implantation damage (eg, hydrogen ions and amorphous silicon layers) of the silicon layer. Based on the formation of?

In operations 212 in FIGS. 7-9 and 18, the donor semiconductor wafer 120, PVSF 102 and / or partially completed PVS 124 may be introduced into one or more finishing process (s) 130. . The finishing process 130 may include, for example, one or more subprocesses. For example, finishing process 130 may include various scribing steps required to form topography of PVS variations 100B and 100C. Such scribing steps are well known in the art and may be performed in conjunction with, or before or after other finishing processes 130.

Another finishing step 130 may include increasing the semiconductor thickness of the release layer 122. For change 100A, the semiconductor material may be added, for example, before mesoscopic growth of back contact layer 104. In certain embodiments, the final combined thickness of semiconductor layers 106 and 108 should be, for example, greater than or equal to 10 microns (ie, 10000 nm) and less than or equal to about 30 microns. Thus, a moderately thick release layer 122 must be formed and enlarged with an additional semiconductor layer 122 (eg, a silicon layer) until the desired thickness is formed.

Augmentation with an additional Si layer 132 may also include a doping step. Historically, the amorphous silicon layer belongs to about 50 to 150 nm in thickness, and depending on the implantation energy and implant time, the thickness of the release layer 122 belongs to about 500 nm. However, with respect to the microelectronic SOI structure, a thinner release layer 122 can be formed for the PVSF 102 with the thinner amorphous silicon layer required and also with more semiconductor material added in the frying finishing process. .

According to operation 212, the cleaved surface 123 may be introduced into post-cleaving processing, which may include introducing the cleaved surface 123 into a polishing or annealing process to reduce the rigidity 123A. Can be. Further, in order to achieve an exemplary embodiment of variation 100B, the finishing process may include an application for conductive window layer 110, such as, for example, deposition of indium tin oxide. Conversely, in order to achieve an exemplary embodiment of variation 100C, the finishing process is deposited by back contact layer 104, a conductive metal-based or metal-oxide based layer, such as LPE, CVD, or PECVD. Application of the prepared aluminum-based film. As discussed above, the back contact layer 104 may be formed by epitaxial or mesogenic growth, such as in the case of nickel silicide.

To some extent, less finished processing is required so that partially completed PVS 124 has more of the characteristics of the intended finished product. In contrast, the formation of PVSF 102 on insulating substrate 101 alone distinguishes the substrate 101-PVSF 102 combination and photovoltaic structure from any other semiconductor-on-insulator structure of US application 2004/0229444. If not, some PVS-specific finishing process is required. However, having substantially single crystals as the photovoltaic structure foundation 102 is to relax the parameters within operating, appear useful from being chosen, and expand the scope of selection in the process for finishing.

In particular, the formation of PVSF 102 or partially completed PVS 124 allows greater flexibility prior to the formation of multi-junction PVS devices. For example, manufacturers of PVSF 102 of crystal-Si exploit different specific heat capacities in which crystal Si versus (Vs) GaAs, Ge, and GaInP2 form various multiple junction layers of GaAs, Ge, and GaInP2. something to do. Optionally, as in the preferred embodiment described in FIG. 21, PVSF 102 may comprise Ge, or GaAs, or PCPVS 124 may comprise a doped Ge / GaAs layer.

Alternative embodiments of the present invention will be described with reference to the SiOG process described above and will be described in more detail. For example, the result of separating the release layer 122 from the donor semiconductor wafer 120 forms a first cleaved surface of the donor semiconductor wafer 120 and a second cleaved surface 123 of the release layer 122. As described above, the finishing process 130 is applied to the second cleaved surface 123 of the release layer 122. Additionally or alternatively, the finishing process 130 may, for example, apply a polishing process to the first cleaved surface of the donor semiconductor wafer 120 (using one or more of the techniques described above).

Yet another embodiment of the present invention may include a donor semiconductor wafer 120 and an epitaxial semiconductor layer disposed on the substantially single crystal donor semiconductor wafer 120 and the donor semiconductor wafer 120. do. (Details of epitaxially grown semiconductor layers in a SOI context are disclosed in co-pending US patent application Ser. No. 11 / 159,889, filed June 23, 2005, the entire disclosure of which is incorporated herein by reference. Thus, the exfoliation layer 122 may be formed substantially from the epitaxial semiconductor layer (also may include a portion of the single crystal donor semiconductor material from the wafer 120). Thus, the finishing process described above may be applied to the cleaved surface 123 of the exfoliation layer 122 formed from the epitaxial semiconductor material and / or the combination of the epitaxial semiconductor material and the single crystal semiconductor material.

One or more photovoltaic cell forming processes according to the present invention may also be automated within a system for the formation of a photovoltaic structure 100. The system may include a PVS handling assembly, which processes the PV structure 100 and photovoltaic process assembly for processing. Photovoltaic process assemblies may include various subsystems, for example, fabrication or finishing systems and transfer or bonding systems used in the manufacture of PV structures 100 processed by PV semiconductor-on-insulator handling assemblies.

For example, once the release layer 122 is prepared, either PVSF 102 or partially completed PVS 124 can be included, and the handling assembly can be fabricated within the PVS process assembly such that bipolar bonding occurs. The PV structure 100 can be transferred and positioned as needed. Within the PVS process assembly, additional transfer and positioning of the PVS 124 or partially completed PVS 102, substrate 101, which is bonded or partially completed, is performed by the additional operations 210 and 212 of the peeling and finishing steps, respectively. Get up.

Referring to FIG. 19, a simplified multijunction change 100D of PVS 100 is shown in accordance with one or more embodiments. Multi-junction PVS 100D may be generally similar to the PVS of FIG. 3, but with important exceptions, such as replacement of glass substrate 101 to crystal-GE wafer substrates, a crystalline Ge film exfoliated on top of the glass substrate. Have The p-type germanium or GaAs wafer has a thickness of 500 microns and a resistance of 0.01-0.04 Ohm-Cm, and hydrogen can be implanted in a dose of 100 Kev and 8 x 10 16. The wafer can then be cleaned by chemical means and introduced into an oxygen plasma treatment to oxidize its surface groups. In the subsequent cleaning step, the GaAs wafer may be inserted into a deposition chamber and coated with a doped or undoped Ge film layer, the thickness of which depends on the device design. Deposition of germanium on GaAs wafers may be accomplished by a variety of techniques including plasma enhanced chemical vapor deposition, ion beam assisted sputter deposition, evaporation or chemical vapor epitaxy. Doping (p-type) the Ge layer can be accomplished with As or P. Alkali-aluminoborosilicate glass wafers are thermally matched with germanium and have a thickness of 1 mm, which can be washed with standard cleaning techniques, for example, washing with detergent and distilled water followed by washing with dilute acid. The two wafers are then contacted and placed in a bonding system. A voltage of 1000 V is applied to the wafer and applied to the glass and germanium wafers or Ge-coated GaAs wafers for 20 minutes at temperatures of 450C and 400C, respectively, before removal of the applied voltage. The germanium thin film or GaAs / Ge multilayer bonded to the glass can be separated from the mother wafer, which has a very strong bond with the glass. Thus, in Fig. 19, reference numerals have the following meanings:

101: glass substrate;

104: doped Ge film as back contact layer;

105: GaAs tunnel junction;

106: p-type GaAs;

108: n-type GaAs or GaInP;

107: AlGaAs tunnel junction:

110: conductive window layer.

Glass wafers with germanium or GaAs / Ge films may optionally be polished and then annealed or heated to remove damaged germanium or GaAs top and good surface layers. Such a wafer may be used as a substrate for growing an epitaxial structure to form a solar cell. Examples of such materials may include GaAs, GaInP / GaAs, GaxInyP / Gac, IndAs / Ge and other materials known in the art. Various processes may be used for depositing the epitaxial film, including closed space vapor transport (CVST), metallo-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) and other methods known in the art. A surface passivating window layer, for example a wide bandgap epilayer of AlGaAs, InGaP or ZnSe, is employed in combination with other encapsulation or passivation layers, and surface treatment of the cell Can be used to complete.

Ohmic contacts will be applied in a variety of structures depending on the device design, but basically the current flow formed from one contact to the next is applied to the completed electronic circuit, and the two guided from the device once the circuit is completed. The electrodes of are coupled with a load. In that way, the back contact layer need not be the outermost layer with respect to the semiconductor layer as shown in FIG. For example, the back contact 104 may be located on the semiconductor layer 106, rather than on the bottom, if appropriately separated to form a suitable circuit and electrical flow structure.

Although described in accordance with certain embodiments in the present invention, these embodiments are to be understood as merely illustrative of the principles or applications of the present invention. Accordingly, it should be understood that numerous modifications may be made to the described embodiments, and that the invention may be varied without departing from the spirit and scope of the invention as defined in the appended claims.

For the purpose of illustrating various aspects of the invention, like numerals refer to like elements and are shown in a simplified form, which is preferably provided, but the invention is not limited to the precise arrangements or components shown, but is claimed Rather, it should be understood as by what is described in. The drawings are not to scale, and the viewpoints of the drawings are not to scale with each other.

1, 2 and 3 are block diagrams illustrating single-junction, double-junction and triple-junction photovoltaic structures, respectively.

4, 5 and 6 are block diagrams illustrating photovoltaic structures according to one or more embodiments of the invention, respectively.

7, 8 and 9 are flow diagrams illustrating process steps that may be performed to produce photovoltaic SOI structures, respectively, according to one or more embodiments of the present invention.

10-18 are block diagrams illustrating structures close to the medium and the finished product, respectively, formed using a process according to one or more embodiments of the present invention.

19 is a simplified illustration of a multi-junction photovoltaic structure in accordance with one or more embodiments of the present invention.

Claims (66)

Insulator structure; Release layer; And An entirety of the release layer and most of the conductive layer for the insulator structure; And A bond for bonding the insulator structure, the conductive layer, and the release layer, And the release layer comprises a substantially single crystal release layer of a substantially single crystal donor semiconductor wafer. The method of claim 1, wherein the release layer is silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP) And a single crystal material selected from indium phosphide (InP). 3. The photovoltaic device of claim 1 or 2, wherein the bond that couples the insulator structure, the conductive layer, and the release layer is a bipolar bond comprising an interface region. The photovoltaic device of claim 3, wherein the interface region comprises a hybrid region and a depletion region. The method according to any one of claims 1 to 4, wherein the device, A first ion migration zone in the insulator; And And a second ion transport zone across the conductive layer and the exfoliation layer. The photovoltaic device of claim 1, wherein the conductive layer comprises a metal-based material or a metal-oxide based material. The photovoltaic device of claim 1, wherein the exfoliation layer comprises a doped semiconductor layer and the conducting layer comprises a back contact layer or a conducting window layer. . The photovoltaic device of claim 7, wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor bonding layer having regions doped with n-type and p-type. . The method of claim 7, wherein the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium or silicide; Also And the conductive window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes. The device of claim 1, wherein the device comprises a plurality of photovoltaic device layers formed in or on the release layer and located distal to the insulation substrate. A photovoltaic device further comprising. The photovoltaic device of claim 10, wherein the plurality of photovoltaic device layers comprises one or more semiconductor layers, one or more conductive layers, and one or more passivating layers. The photovoltaic device of claim 10, wherein at least one of the plurality of photovoltaic device layers comprises an epitaxially grown crystal layer. The photovoltaic device of claim 1, further comprising an additional photovoltaic layer integral to the release layer and proximate to the insulating substrate. The method according to any one of claims 1 to 13, Insulation structure; A peeling layer adjacent the insulating structure; A bipolar bond bonding the insulating structure and the release layer; And Located at the distal end of the insulating structure and includes a plurality of photovoltaic device layers in or on the release layer, And the release layer comprises a substantially single crystal release layer that is substantially a single crystal donor semiconductor wafer. The apparatus of claim 14, wherein the device comprises: a first ion migration zone in the insulator; And a second ion migration zone in the exfoliation layer. The photovoltaic device of claim 14, wherein the bipolar bond comprises a boundary region. The photovoltaic device of claim 16, wherein the boundary region comprises a hybrid region and a depletion region. The photovoltaic device of claim 14, wherein the plurality of photovoltaic device layers comprise a semiconductor layer and a conductive layer. 19. The photovoltaic device of claim 18, wherein the plurality of photovoltaic device layers further comprises one or more semiconductor layers, one or more conductive layers, and one or more passivation layers. The photovoltaic device of claim 18, wherein the conductive layer comprises a metal-based material or a metal-oxide based material. The photovoltaic device of claim 14, wherein the plurality of photovoltaic device layers comprises a doped semiconductor layer, a back contact layer, and a conductive window layer. The semiconductor device of claim 21, wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having regions doped with n-type and p-type. Photovoltaic device. The method of claim 21, wherein the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or silicide; Also And the conductive window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes. The photovoltaic device of claim 14, wherein at least one of the plurality of photovoltaic device layers comprises an epitaxially grown crystal layer. Forming a release layer having a conductive layer on the donor semiconductor wafer; And Moving the release layer to an insulating substrate. The method of claim 25, wherein the method is Introducing the donor semiconductor wafer into an ion implantation process to form a release layer of the donor semiconductor wafer; Bonding the release layer to the insulating substrate; And Separating the exfoliation layer from the donor semiconductor wafer to expose one or more cleaved surfaces. 27. The method of claim 26, wherein the method introduces the at least one cleaved surface into a plurality of finishing processes. 29. The method of claim 27, wherein said at least one cleaved surface comprises a first cleaved surface of said donor semiconductor wafer and a second cleaved surface of said release layer. 29. The method of claim 28, wherein said plurality of finishing steps are applied to at least a second cleaved surface of said release layer. 29. The method of claim 28, wherein the plurality of finishing processes are applied to at least one first cleaved surface of the donor semiconductor wafer. 29. The method of claim 27, wherein the plurality of finishing processes comprise scribing, creating a back contact layer, conducting window layer forming, polishing, annealing, Photovoltaic structure, characterized in that it is selected from the group consisting of cleaning, doping, forming a passivation layer, forming an encapsulating layer, and adding additional semiconductor material. Formation method. The method of claim 26, wherein the combining step, Heating at least one of the insulating substrate and the donor semiconductor wafer; Directly or indirectly contacting the insulating substrate with a release layer of the donor semiconductor wafer; Pressing the insulating substrate and the release layer together; And Applying a voltage potential across the insulated substrate and the donor semiconductor wafer to induce coupling. 33. The method of any one of claims 25 to 32, wherein the donor semiconductor wafer comprises a substantially single crystal donor semiconductor wafer comprising silicon, germanium, or gallium arsenide. The donor semiconductor wafer of claim 25, wherein the donor semiconductor wafer comprises silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), germanium (Ge), gallium arsenide ( GaAs), gallium phosphide (GaP), and indium phosphide (InP). 33. The method of any of claims 25 to 32, wherein the donor semiconductor wafer comprises a substantially single crystal donor semiconductor wafer, and wherein the separated release layer is formed substantially from the single crystal donor semiconductor wafer material. Formation method of photovoltaic structure. The donor semiconductor wafer of claim 25, wherein the donor semiconductor wafer comprises a donor semiconductor wafer and an epitaxial semiconductor layer disposed on the donor semiconductor wafer, wherein the separated release layer is substantially separated from the epitaxial semiconductor layer. Forming method of photovoltaic structure, characterized in that formed in. 33. The method of any one of claims 25 to 32, wherein forming the exfoliation layer with the conductive layer comprises epitaxy, mesotax, exfoliation, vapor transport, vapor deposition, ion A method of forming a photovoltaic structure comprising at least one of ion implantation and oxidation. 33. The method of any of claims 25-32, wherein the conductive layer comprises a metal-based material or a metal-oxide based material. 33. The method of any one of claims 25 to 32, wherein the exfoliation layer comprises a doped semiconductor layer and the conducting layer comprises a back contact layer or a conducting window layer. 33. The semiconductor device of any of claims 25 to 32 wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having regions doped with n- and p-types. Method for forming a photovoltaic structure, characterized in that. The method of claim 39, wherein the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or silicide; Also Wherein the conductive window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes. 42. The method of any one of claims 25 to 41, wherein the photovoltaic structure is a single-coupled photovoltaic structure or a multi-coupled photovoltaic structure. 42. The photovoltaic system of any one of claims 25 to 41, wherein the method further comprises introducing the release layer into at least one finishing process prior to moving the release layer to the insulating substrate. Method of forming the structure. 45. The method of claim 43, wherein said at least one finishing process forms at least one additional photovoltaic device layer prior to moving said release layer to said insulating substrate. The method of claim 25, wherein the method is Introducing a donor semiconductor wafer into an ion implantation process to form a release layer on the donor semiconductor wafer; Forming a bipolar bond between the release layer and the insulating substrate by electrolysis; Separating the exfoliation layer from the donor semiconductor wafer to expose one or more cleaved surfaces; And And forming a plurality of photovoltaic structure layers adjacent said release layer and located at distal ends of said insulating layer. 46. The method of claim 45, further comprising introducing the one or more cleaved surfaces to a plurality of finishing processes, wherein forming the plurality of photovoltaic structure layers comprises one or more finishing processes. Method for forming a photovoltaic structure, characterized in that. 47. The method of claim 46, wherein said at least one cleaved surface comprises a first cleaved surface of said donor semiconductor wafer and a second cleaved surface of said release layer. 48. The method of claim 47, wherein said plurality of finishing steps are applied to at least a second cleaved surface of said release layer. 48. The method of claim 47, wherein said plurality of finishing processes are applied to at least a first cleaved surface of said donor semiconductor wafer. 47. The method of claim 46, wherein the plurality of finishing processes comprise scribing, back contact forming, conducting window forming, polishing, annealing, cleaning, doping, forming a passivation layer, encapsulation. A method of forming a photovoltaic structure, characterized in that it is selected from the group consisting of a layer forming step and an additional step of additional semiconductor material. The method of claim 45, wherein the forming of the bipolar bond by electrolysis, Heating at least one of the insulating substrate and the donor semiconductor wafer; Directly or indirectly contacting the insulating substrate with a release layer of the donor semiconductor wafer; Pressing the insulating substrate and the release layer against each other; And And applying a voltage potential across the insulating substrate and the donor semiconductor wafer to induce a bipolar bond. 46. The method of claim 45, wherein the donor semiconductor wafer comprises a substantially single crystal donor semiconductor wafer comprising silicon, germanium, or gallium arsenide. The method of claim 45, wherein the donor semiconductor wafer comprises silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP). ), And indium phosphide (InP). 46. The method of claim 45, wherein the donor semiconductor wafer comprises a substantially single crystal donor semiconductor wafer, and wherein the separated release layer is formed substantially from the single crystal donor semiconductor wafer material. 46. The photovoltaic of claim 45, wherein the donor semiconductor wafer comprises a donor semiconductor wafer and an epitaxial semiconductor layer located on the donor semiconductor wafer, wherein the separated release layer is formed from the epitaxial semiconductor layer. Method of forming the structure. 46. The method of claim 45, wherein forming the plurality of photovoltaic structure layers A method of forming a photovoltaic structure comprising at least one of epitaxy, mesotax, exfoliation, vapor transport, vapor deposition, ion implantation and oxidation. 46. The method of claim 45, wherein said plurality of photovoltaic structure layers comprises a semiconductor layer and a conductive layer.  The method of claim 33, wherein the conductive layer comprises a metal based material or a metal-oxide material. 46. The method of claim 45, wherein the plurality of photovoltaic structure layers comprises a doped semiconductor layer, a back contact layer and a conductive window layer. 36. The semiconductor device of claim 35 wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having regions doped with n-type and p-type. Formation method of photovoltaic structure. The method of claim 35, wherein the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or silicide; Also Wherein the conductive window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes. 46. The method of claim 45, wherein the photovoltaic structure comprises a single-junction photovoltaic structure or a multi-junction photovoltaic structure. Photovoltaic structure handling assembly, and photovoltaic structure processing assembly, The photovoltaic structural process assembly includes a fabrication system and a transport system, the fabrication system fabricates a release layer processed by the photovoltaic structure handling assembly, and the transport system transfers the release layer to an insulating substrate. A system for forming a photovoltaic structure. 64. The system of claim 63, wherein each release layer includes a conductive layer prior to being transferred to the insulating substrate. 65. The method of claim 63 or 64, wherein the system further comprises a bonding system, the bonding system configured to form a bipolar bond between the insulating substrate and the exfoliation layer by electrolysis. system. 66. The method of any one of claims 63 to 65, wherein the system further comprises a finishing system, the finishing system comprising a scribing step, a back contact layer forming step, a conductive window layer forming step, a polishing step, an anneal For carrying out at least one finishing process selected from the group consisting of a step, a cleaning step, a doping step, a passivation layer formation step, an encapsulation layer formation step and an additional semiconductor material addition step. system.

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