CN101467245A

CN101467245A - Thin film photovoltaic structure and fabrication

Info

Publication number: CN101467245A
Application number: CNA2007800200487A
Authority: CN
Inventors: D·F·道森一埃利; K·P·加德卡尔; R·M·沃尔顿
Original assignee: Corning Inc
Current assignee: Corning Inc
Priority date: 2006-05-31
Filing date: 2007-05-24
Publication date: 2009-06-24

Abstract

Novel photovoltaic structures comprising an insulator structure bonded to an exfoliation layer, preferably of a substantially single-crystal donor semiconductor wafer, and at least one photovoltaic device layer, such as a conductive layer, and systems and methods of production of a photovoltaic device, comprising creating on a donor semiconductor wafer an exfoliation layer and transferring the exfoliation layer to an insulator substrate.

Description

Film photovoltaic structure and manufacturing thereof

Technical field

The present invention relates to prepare system, method and the product of film photovoltaic structure, preferably have and be the film of monocrystalline substantially, and utilize improved technology, specifically comprise: the photovoltaic structure that the base portion or the part of photovoltaic structure are finished is transferred to insulator substrate, and its anodic bonding is arrived this insulator substrate.

Background technology

Photovoltaic structure (PVS) is with the special shape of photon conversion for the semiconductor structure of electricity.Essentially, this device need be realized two functions: photogenerated electric charge carrier in light absorbent (electronics and hole), and the conductive contact that charge carrier separation extremely will be transmitted electric current.This conversion is called as photovoltaic (PV) effect, and is used for solar cell, and it becomes electric energy with transform light energy, and is called as photovoltaic about the research field of solar cell.Some PVS is semiconductor (SOI) structure on the insulator.

With reference to figure 1,2 and 3, block diagram illustrates unijunction, binode and three knot photovoltaic structures respectively.Reference numeral among these figure has following implication: the A101:Ge substrate; A103/105:1.4eV GaAs battery; A107: grid contact; The A201:Ge substrate; A203:1.4eV GaAs battery; A207:AlGaLnP or AlGaAs tunnel junction; A209/211:1.9eV InGaP battery; A213: grid contact; A301:0.7eV Ge battery and substrate; A313/315:1.9eV InGaP unit; And A317: grid contact.Shown germanium substrate is a monocrystalline Ge wafer.Although efficient separately produces the bigger of efficient along with the increase of knot and increases than having improved in the past few years 1%-3.5%, and each additional knot increases about 4.5%.Benefit that should additional knot is because PVS device absorbing light and convert thereof into electricity and utilize the ability of more available light on different band gap.

The current needs mechanical strength is big, large tracts of land, cheap solar cell.Solar cell based on GaAs is an approach that improves conversion efficiency and improve outdoor reliability.The band gap of GaAs is 1.42eV, and it is near the optimal value (1.5eV) of the band-gap energy of solar energy converting.Different with silion cell, the GaAs battery is relatively not too responsive for heat.GaAs and alloy thereof are its designs that adapts to wide region as another significant advantage of PV battery material.The most significant be utilize on the body Ge monocrystal substrate GaAs or such as GaInP ₂Other film high efficiency multijunction solar cells with GaInAs and so on based on the III-V material.Surpass 37% based on the certified peak efficiency of GaAs multijunction solar cell.Germanium substrate is used to these batteries, because the spacing of lattice of GaAs and Ge and thermal expansion are closely mated.

At present, study the substrate that the cost that comprises glass and ceramic alumina is lower than silicon metal, be used for III-V compound semiconductor solar cell application.In an example, the vitreous silica and the ceramic alumina that apply with thick Ge film are used as the alternative substrate that Ge applies, and are used for high-performance GaAs/InGaP solar cell.Germanium film (2-5 micron) is deposited on the polycrystal alumina (p-Al of thermal expansion matching ₂O ₃) on.Cover the Ge film with various metals and oxidation film subsequently, utilize rapid thermal treatment crystallization again then.The average crystal grain size that obtains is greater than 1mm.Utilize the CSVT technology at these big crystal grain (〉 1mm) epitaxial loayer of growth GaAs on thin (～2 μ m) Ge layer.The someone advises the starting point of these GaAs/Ge/ ceramic structures as the tandem junction device.

Make the III-V semiconductor thin-film solar cell be located immediately at the advantage on glass of covering, be that it has reduced the weight of structure and has reduced the cost of integrated technique.In fact this solar cell can adopt solar radiation to incide the structure of the glass substrate side of covering.

The researcher after deliberation the polycrystal membrane that is deposited on the glass substrate be used for space solar cell.Crystal mass has limited the III-V Solar cell performance that has polycrystal film.Promptly the said structure on low-cost glass substrate all can not obtain having high efficiency (〉 30%) the GaAs battery.Therefore, need to overcome the relevant problem of prior art, based on the technology and the product of low cost and transparent glass substrate.

From the semiconductor microelectronics field and for the ease of explaining that following discussion is sometimes according to the semiconductor on the insulator (SOI) structure.Soi structure to this particular type carries out reference, so that explain the present invention, but does not plan and should not explained and explain the present invention by any way.Use abbreviation SOI with the semiconductor structure on the indication insulator in this article, this structure generally comprises but is not limited to silicon structure on the insulator such as silicon on glass (SiOG) structure.Similarly, abbreviation SiOG is used to indicate semiconductor structure on glass, and this structure generally comprises but is not limited to silicon structure on glass.Term SiOG also will comprise the semiconductor structure on the glass-ceramic, and this structure includes but not limited to the silicon structure on the glass-ceramic.Abbreviation SOI comprises the SiOG structure.

The variety of way of obtaining the soi structure wafer comprises (1) epitaxially grown silicon (Si) on lattice matched substrate; (2) silicon single crystal wafer is joined to the SiO that grown on it ₂On another silicon wafer of oxide layer, then for example monocrystalline silicon layer of 0.05 to 0.3 micron (50-300nm) is polished or be etched to top wafer; And (3) ion injection method, its intermediate ion (such as hydrogen or oxonium ion) is injected into, to form the top at silicon wafer under the situation about injecting at oxonium ion is the buried oxide layer of Si, or is used for another Si wafer is engaged with oxide skin(coating) from the thin Si layer of a silicon wafer separation (peeling off) under the situation that hydrogen ion injects.

Also can after thin silicon films is peeled off from the silicon materials wafer, chemico-mechanical polishing (CMP) be used for treatment S OI structure.Yet disadvantageously, CMP technology can not removed material equably on the surface of thin silicon films in polishing process.For semiconductor film, general surface heterogeneity (standard deviation/mean removal thickness) is in the scope of 3-5%.The silicon film thickness that takes out is big more, and the variation of thickness is correspondingly big more.

With the microelectronic applications contrast of soi structure, photovoltaic structure more can be tolerated this defective, although this defective can influence the performance of photovoltaic cell unfriendly.Though this dressing technique as CMP can be improved surface characteristic, the defective admissibility of photovoltaic structure can make its cost be suppressed.Therefore, expectation combines the advantage of soi structure manufacturing progress with the requirement of photovoltaic structure manufacturing, and the defective relevant with soi structure manufacturing progress minimized.

Summary of the invention

According to one or more execution modes of the present invention, the system, the method and apparatus that form photovoltaic device comprise: construct peel ply and it is transferred to insulator structure.Peel ply can be constructed by donor semiconductor wafer.Donor semiconductor wafer and strippable coating can preferably include and be the semi-conducting material of monocrystalline substantially.Peel ply can preferably include one or more photovoltaic device layers, as the conductive layer of constructing before being transferred to insulator substrate.Shifting peel ply can preferably include: form anodic bonding by electrolysis between peel ply and insulator substrate, utilize thermal and mechanical stress then, peel ply is separated from donor semiconductor wafer.One or more photovoltaic device layers also can be after peel ply be transferred to insulator substrate, within the peel ply, on or above structure.Can carry out one or more finishing processing before or after shifting peel ply, the execution of finishing processing can construct the photovoltaic device layer.

According to one or more execution modes of the present invention, the system, the method and apparatus that form the photovoltaic semiconductor-on-insulator structure comprise: structure photovoltaic structure base portion on donor semiconductor wafer, the photovoltaic structure base portion is transferred to insulator substrate, and on described PV base portion, deposits a plurality of photovoltaic structure layers.Described transfer can comprise: photovoltaic structure base portion anodic bonding is arrived insulator structure, and the photovoltaic structure base portion is separated from donor semiconductor wafer.

According to one or more execution modes of the present invention, the system, the method and apparatus that form the photovoltaic semiconductor-on-insulator structure comprise: form the photovoltaic cell that part is finished on donor semiconductor wafer, and the photovoltaic structure that this part is finished is transferred to insulator substrate.Described transfer can comprise: the photovoltaic cell anodic bonding agent that part is finished joins insulator structure to, and the photovoltaic cell that part is finished separates from donor semiconductor wafer.

According to one or more execution modes of the present invention, the system, the method and apparatus that form photovoltaic device comprise: donor semiconductor wafer is carried out ion inject processing, to form peel ply in donor semiconductor wafer; Join peel ply to described insulator substrate; Separate peel ply from donor semiconductor wafer, this peel ply serves as the photovoltaic structure base portion; And on the photovoltaic structure base portion structure a plurality of photovoltaic structure layers.

According to one or more execution modes of the present invention, the system, the method and apparatus that form photovoltaic device comprise: donor semiconductor wafer is carried out ion inject processing, to construct peel ply in donor semiconductor wafer; The photovoltaic cell that the structure part is finished on peel ply; Join peel ply to insulator substrate; Peel ply with photovoltaic cell of partly finishing is separated from donor semiconductor wafer, thereby expose at least one face that dissociates; And at least one face that dissociates repaired processing.

According to one or more execution modes of the present invention, the system, the method and apparatus that form photovoltaic device comprise: the photovoltaic cell that the structure part is finished on donor semiconductor wafer; Ion is carried out on the preparation alms giver surface of the photovoltaic cell finished of part and donor semiconductor wafer inject and handle, in donor semiconductor wafer, to form peel ply; Join peel ply to insulator substrate; Peel ply with photovoltaic cell of partly finishing is separated from donor semiconductor wafer, thereby expose at least one face that dissociates; And at least one face that dissociates repaired processing.

In one or execution mode, the step of joint can comprise: at least one in heating insulator substrate and the donor semiconductor wafer; Insulator substrate is directly or indirectly contacted with the peel ply of donor semiconductor wafer; And on insulator substrate and donor semiconductor wafer, apply voltage potential to induce joint.The temperature of insulator substrate and semiconductor wafer can be lifted in about 150 ℃ scope of strain point (strain point) of insulator substrate.The temperature of insulator substrate and semiconductor wafer can be lifted to different levels.The voltage potential at insulator substrate and semiconductor wafer two ends can be between about 100 to 10000 volts.Insulator body substrate, peel ply and donor semiconductor wafer by cooling engages can induce stress, and the feasible ion defects that occurs in the border of qualification peel ply in the donor semiconductor wafer substantially of breaking is got along.Ion defects causes peel ply to be got along in ion defects with respect to the heat of wafer on every side and coefficient of thermal expansion differences dissociating, form the semiconductive thin film that joins insulator to.

At least one face that dissociates can comprise first of donor semiconductor wafer second of face and the peel ply face that dissociates that dissociates.For first face that dissociates that is associated with donor semiconductor wafer, finishing processing can comprise that the preparation donor semiconductor wafer is to utilize again.For second face that dissociates that is associated with peel ply, finishing processing can comprise finishes the photovoltaic cell that part is finished.

According to one or more preferred implementations of the present invention, new solar cell can be monocrystalline Ge, Si or the GaAs film on clear glass or the glass ceramic baseplate.Under the situation based on the battery of GaAs, as attendant advantages, germanium layer can be present between substrate and the monocrystalline GaAs layer.Can mix to germanium layer, so that with the bottom (be back side contact layer) of substrate as multijunction solar cell.Glass or glass ceramic baseplate can expand, with Ge, Si, GaAs or Ge/GaAs coupling.Via the anodic bonding technology of describing among the U.S. Patent application No.2004/0229444, can obtain strong bonding Si, Ge, GaAs or Ge/GaAs single crystal membrane layer on glass or glass ceramic baseplate.

This technology at first comprises the injection of hydrogen or the hydrogen and the helium of Ge, Si or GaAs wafer, and under the situation of GaAs, also deposting germanium films on the surface of GaAs wafer subsequently.The GaAs that Ge, Si or Ge cover is engaged to glass substrate then, separates the membrane structure of Ge, Si, GaAs or Ge/GaAs subsequently.Thus obtained SOG structure can be polished, damages the district and expose the second best in quality single-crystal semiconductor layer to remove.Then can be with the epitaxially grown template of this SOG structure, to form needed solar cell as a plurality of layers of Si, Ge, GaAs, GaInP2, GaInAs etc. subsequently.Glass also has sufficiently high strain point except that mating with the semiconductor layer expansion, to bear the subsequent deposition condition.

Typical photovoltaic cell structure comprises p type-inherence-n type (p-i-n), metal-insulator semiconductor (MIS), so-called " series connection " junction battery, multijunction cell and complicated p-n sandwich construction, but the invention is not restricted to these structures.In one skilled in the relevant art's the limit of power, can be according to the product performance of expectation, the photovoltaic cell that the structure part is finished on donor semiconductor wafer is such as unijunction and many knots.Similarly, consider the length of penetration of suitable ion in semi-conducting material, the photovoltaic electricity that part is finished causes constructed still structure after the ion injection before ion injects, also be the judgement in the limit of power of those of ordinary skill.

Notice that donor semiconductor wafer can be the part of such structure: it comprises and be the donor semiconductor wafer of monocrystalline substantially, and chooses wantonly and comprise the epitaxial semiconductor layer that is arranged on the donor semiconductor wafer.Peel ply (for example, the layer that joins insulator substrate to and separate from alms giver's semiconductor structure) can be formed by the single-crystal donor semiconductor wafer material thus substantially.Perhaps, peel ply can be formed by epitaxial semiconductor layer (also can comprise some single-crystal donor semiconductor wafer material) substantially.

Reading detailed technical descriptioon and, can understand the advantage of one or more embodiment of the present invention admirably with after existing SOI technology is compared.Yet main advantage comprises: photovoltaic structure changes, thinner silicon fiml, have the more uniform silicon fiml of high-crystal quality; Higher manufacture; The fabrication yield that improves; The pollution that reduces and the usability of large substrates.These advantages combine naturally, can reduce cost.

Because complicated photovoltaic structure can be made by the high-temperature process on donor semiconductor wafer, photovoltaic structure (PVS) just can change within the scope of the invention.Resulting high-performance PVS can be transferred to low-cost glass substrate then, and with the deposition of remainder layer with finish required any of circuit and graphically finish.

The present invention allows only to use the semiconductor (for the about 10-30 micron of Si, for the direct gap semiconductor 1-3 micron such as GaAs) of desired thickness.With will thicker silicon fiml transfer to the insulator substrate (very difficult) that will polish subsequently and compare to remove perished surface for this control of very thin film, in the method for description of the invention, remove few material, thin silicon films can directly be shifted, subsequently deposition or growth additional thickness.

Expect very much uniform films.In addition, because remove few material in the method,, the silicon film thickness uniformity determines so being injected by ion.Demonstrate in some embodiments very even, the about 1nm of standard deviation.On the contrary, polishing generally causes the removal amount deviation of 5% thickness.

Along with requiring to continue to increase, higher output is crucial.Yet the processing time of the polishing technology relevant with making SiOG is about dozens of minutes, and stove annealing can be several hours.Utilize more uniform film, photovoltaic cell has just reduced the needs of polishing and furnace annealing.

Reduce for waste and cost, it is very important to improve fabrication yield.By avoiding scroll saw saw area loss, can significantly reduce waste of material.Equally, Ang Gui donor semiconductor wafer can be polished and recycling repeatedly.By using film, material consumption is same significantly to be reduced.If avoid the polishing of soi structure, estimate that total fabrication yield will improve.If polishing has low step rate of finished products, this is especially correct, as expection.Owing to the crystallization property of film, the expectation process window wants big, expects that therefore rate of finished products is high.

Because the sensitive natur of SOI, pollutant can influence performance unfriendly, so wish very much to reduce to pollute.Expect these, avoid having reduced contamination of heavy with the needs that reduce bed thickness with the abrasive slurry polishing.In addition, avoid the needs of furnace annealing also to avoid the contamination that may during very normal thermal anneal process, take place.In that this is an important consideration aspect the efficient of photovoltaic device.

This method has suitable retractility for large tracts of land.When the user increased the requirement of substrate size, this applicable retractility had been expanded life of product potentially.Solar panel is very big usually, so that the use of free space maximization, so that photovoltaic cell becomes is big more, couples together to construct the needed photovoltaic cell of big solar panel just few more.On the contrary, for bigger substrate size, surface finish and furnace annealing become increasingly difficult.

Particularly, the major advantage of preferred implementation of the present invention comprises: 1) compare with other the more expensive semiconductor substrate described in the prior (such as the silicon that is used for Ge layer and subsequently GaAs growth of previous use) or the ceramic substrate of thermal mismatching, use low-cost, as to expand coupling glass or glass ceramic baseplate; 2) have the monocrystalline template layer of Si, Ge or multilayer GaAs/Ge on glass substrate, it is used as the template of structure lattice match, defective semiconductor layer seldom, is used for high efficiency solar cell, and is different with the polycrystalline template of using in the prior art; 3) transparency of substrate can have the flexibility in the module manufacturing.

When understanding description of the invention in conjunction with the accompanying drawings, others, feature, advantage etc. will become apparent for those skilled in the art.

Description of drawings

For each side of the present invention is described, at present preferred mode has been shown in the accompanying drawing of reduced form, wherein identical Reference numeral is represented components identical.Yet, should be appreciated that accurate arrangement mode and the means shown in the invention is not restricted to are only limited by the claim of publishing on the contrary.Each accompanying drawing is not pro rata, and the each side of each accompanying drawing relative to each other neither be pro rata.

Fig. 1,2 and 3 is block diagrams that the photovoltaic structure of unijunction, binode and three knots is shown respectively.

Fig. 4,5 and 6 is the block diagrams that illustrate separately according to the photovoltaic structure of one or more execution modes of the present invention.

Fig. 7,8 and 9 is flow charts that method step is shown, and described step is used for making the photovoltaic soi structure of one or more execution modes of the present invention.

Figure 10-the 18th illustrates intermediate structure that the method for utilizing the one or more execution modes of the present invention forms and near the block diagram of final structure.

Figure 19 shows the simplification of one or more preferred implementations of the present invention and ties photovoltaic structure more.

Embodiment

Unless otherwise noted, otherwise all numerals such as the value of percentage by weight, size and some physical property of those expression compositions of in specification and claims, using all should be understood that all to modify in all cases by term " approximately ".Be also to be understood that the accurate numerical value that uses constitutes other execution mode of the present invention in specification and claims.The inventor has endeavoured to ensure the accuracy of the numerical value that discloses among the embodiment.Yet the numerical value of any measurement can comprise some error that is produced by the standard deviation that exists in the corresponding measuring technique inherently.

For " crystalline semiconductor materials ", its expression material can be fully crystallization or be crystallization basically, wherein have or do not have deliberately or accidental defective and/or the dopant of introducing.Therefore it should comprise: (i) be used to form precursor material, this material of the material with semiconducting behavior as semiconductor or non-semiconductor, and (ii) forms by the precursor material that for example mixes, as semi-conductive material.Crystalline semiconductor materials can be monocrystalline or polycrystalline.Certainly, semi-conducting material comprises or defective some inside intrinsic or that deliberately add or the surface usually at least, such as lattice defect or grain boundary.Term " being crystallization basically " reflects that also some dopant can twist or otherwise influence the crystal structure of semi-conducting material.

With reference to figure 4,5 and 6, sometimes they are collectively referred to as Fig. 4-6, wherein show

PVS distortion

100A, 100B and 100C respectively according to the photovoltaic soi structure 100 of one or more execution modes of the present invention.Photovoltaic soi structure 100 can be called PV soi structure 100 or abbreviate PVS100 as.With reference to the accompanying drawings, soi structure 100 is illustrated as the SiOG structure.SiOG structure 100 can comprise insulator substrate 101, photovoltaic structure base portion 102 (Fig. 4), ion migration area 103, back side contact layer 104, p type semiconductor layer 106, n type semiconductor layer 108 and the conductive window layer of being made by glass 110.SiOG structure 100 combines with photovoltaic device has suitable purposes.

Conductive window layer 110 is the conductive material layers that serve as ohmic contact.The conductive window layer can be translucent, transparent or semi-transparent.A kind of exemplary materials can be a tin indium oxide, and this material generally is that the reactive sputtering by the In-Sn target forms in oxidizing atmosphere.The replacement material of tin indium oxide can comprise for example aluminium-doped zinc oxide, boron doping zinc-oxide or or even carbon nano-tube.Tin indium oxide (ITO or tin-doped indium oxide) is indium oxide (III) (In ₂O ₃) and tin oxide (IV) (SnO ₂) mixture, generally can be 90% In ₂O ₃, 10%SnO ₂(percentage by weight).It is transparent and colourless under the situation of thin layer.Under the situation of body form, it is that little Huang is to grey.The principal character of tin indium oxide is the combination of conductivity and light transmission.Yet, in the film deposition process, need to reach one and trade off, because the electric charge carrier of high concentration will increase the conductivity of material, but reduce its transparency.Modal is by electron beam evaporation, physical vapour deposition (PVD) or a series of sputtering technology, with the thin film deposition of tin indium oxide from the teeth outwards.

It is the form of monocrystal material basically that the semi-conducting material of

layer

106 and 108 can make.Used term " basically " semi-conducting material is comprised usually at least or some inside of intrinsic or intentional interpolation or the fact of blemish are taken into account at 106,108 o'clock describing layer, these defectives are lattice defect or grain boundary for example.This term reflects also that basically some dopant can twist or otherwise influence the fact of the crystal structure of semi-conducting material.Particularly, p type semiconductor layer 106 comprises p type dopant, and n type semiconductor layer 108 comprises n type dopant.Note that at the most electron hole pairs of be hopeful to be formed under the situation of p type layer 106 that p type layer 106 is all thick than n type layer 108.

For the purpose of discussing, suppose that semiconductor layer 106,108 is formed by silicon, unless otherwise indicated.Yet, should understand the semiconductor that semi-conducting material can be based on silicon, or the semiconductor of any other type, such as the semiconductor of kinds such as III-V, III-IV.These examples of material comprise: silicon (Si), Germanium-doped silicon (SiGe), carborundum (SiC), germanium (Ge), GaAs (GaAs), gallium phosphide (GaP) and indium phosphide (InP).

Back side contact layer 104 can be a conductive layer, such as based on conducting metal or based on metal oxide the layer.Back side contact layer is an ohmic contact, i.e. zone on such semiconductor device, and it is made and makes that current-voltage (I-V) curve of device is linear and symmetrical.Can the hot robustness when contacting select back side contact material with Si.For example, back side contact layer 104 can be based on the film of aluminium or silicide, and such as titanium disilicide, two tungsten silicides or nickle silicide, its example is discussed hereinafter.Silicide-polysilicon combination has than the better electrical property of independent polysilicon, but and does not melt in following process.

Back side contact layer 104 can for example be constructed by the deposition such as LPE, CVD, PECVD.Also can use Nei Yanfa (Mesotaxy) or epitaxy.Yet epitaxy is the growth of coupling phase on substrate surface, and Nei Yanfa is the growth of crystallography coupling phase under the surface of host crystal.In the method, ion is injected in the material with sufficiently high energy and dosage, with structure one deck second phase, and the control temperature makes the crystal structure of target not be destroyed.But the crystal orientation of design level is to mate with target, even accurate crystal structure may be mutually far short of what is expected with lattice constant.For example, after nickel ion is injected into silicon wafer, the nickel silicide layer of can growing, the wherein crystal orientation of silicide and silicon coupling.

The peel plies 122 that Fig. 7-9 and 11 discusses can comprise constitute the back side contact 104 extension or in prolong layer with and on the situation of semiconductor layer under, use epitaxy or Nei Yanfa to form back side contact layer 104 and can be considered to structure 100A and Fig. 5 and the structure 100B of Fig. 6 description and the notion interface between the 100C that Fig. 4 describes.Yet semiconductor layer just can serve as photovoltaic structure base portion (PVSF) 102 separately, in Fig. 4, the combination of semiconductor layer and back side contact layer 104 can be regarded as the PVS124 that Fig. 8 and 13 parts of introducing are finished.Therefore, utilize epitaxy or Nei Yanfa or ion to inject before in anodic bonding (step 208) and form back side contact layer 104, just formed the PVS 124 that the part that is transferred to substrate 101 is finished, as among method 200B and the 200C, adopt Nei Yanfa and epitaxy to form back side contact layer 104 in peel separation (step 210) back then but shift PVSF 102, then follow method 200A.Equally, back side contact layer 104 can form by a large amount of doping PVSF 102 after peel separation.This a large amount of doping generally can be implemented by ion implantation.

In addition, if after peel separation (step 210), back side contact layer 104 is deposited on the top of PVSF 102, then can obtain being out of shape the PVS 100 of 100A.Perhaps, if before or after Nei Yanfa, PVSF 102 is doped to the p N-type semiconductor N, and, then can obtain being similar to the PVS 100 of distortion 100A or 100B by Nei Yanfa formation back side contact layer 104.If the degree of depth of the interior epitaxial growth of back side contact layer 104 is in the middle part of PVSF 102, then the layer of PVSF102 can remain under the back side contact layer 104, as distortion 100A.If the degree of depth of the interior epitaxial growth of back side contact layer 104 reaches the composition surface 126 of PVSF 102, then seldom to there not being PVSF layer 102 can remain under the back side contact layer 104, as among the distortion 100B.

Conductive layer is formed on the epitaxial loayer 122 or under the situation wherein at conductive layer, no matter by formation such as epitaxy, Nei Yanfa, ion injection, doping, gas phase transmission, vapour depositions, will become integral body with peel ply 122.If joining before the insulator substrate 101 conductive layer at peel ply 122 is formed on the peel ply 122 or wherein, then when peel ply 122 joins on the substrate 101, conductive layer will be close to insulator substrate 101.In other words, conductive layer is formed on peel ply 122 near a side of insulator substrate, makes that for example resulting conductive layer can be between insulator substrate and epitaxial loayer.If peel ply 122 at first joins insulator substrate 101 to, conductive layer is formed on the peel ply 122 or wherein thereafter, and then conductive layer will be on the relative side of peel ply 122 and insulator substrate 101 or near it, thus away from insulator substrate 101.Equally, after peel ply joins insulator substrate 101 to, be formed among the peel ply 122 on or above any photovoltaic device layer, all will be away from insulator substrate 101.

As will going through with reference to figure 15-17, ion migration area 103 is formed on insulator substrate 101 and joins on the either side of the anodic bonding agent between the layer of insulator substrate 101; Promptly at the PVS base portion 102 of distortion among the 100A; Back side contact 104 among the distortion 100B; Or the conductive window layer 110 among the distortion 100C.Ion migration area 103 obtains from the described anodic bonding method of Figure 15.There are not these ion migration areas 103 in the photovoltaic structure of prior art.

Compare with distortion 100B among Fig. 6 with Fig. 5, the distortion 100A among Fig. 4 comprises PV structural base 102.When peel ply is transferred to insulator substrate 101 without any extra play, photovoltaic structure base portion 102 can appear, and this is equivalent to the PVS 124 (PCPVS) that part is finished.In essence, can think that peel ply 122 becomes PVSF 102 after joining insulator substrate 101 to.So, PVSF 102 preferably can comprise the basic semiconductor layer of monocrystalline that is, because it comes from Fig. 7 and 10 donor wafer of introducing 120.

---to be glass substrate 101 here---can be formed by oxide glass or oxide glass-pottery insulator substrate 101.Although do not need, embodiment described herein can comprise that strain point is shown as oxide glass or the glass ceramics less than 1000 ℃.As conventional in the glass technology for making, strain point is that the viscosity of glass or glass-ceramic is 10 ^14.6Pool (10 ^13.6Pa.s) temperature.As between oxide glass and oxide glass-ceramics, glass can have the simpler advantage of manufacturing, makes it use wider and more cheap thus.

As an example, glass substrate 101 can be made of the glass substrate that comprises alkaline earth ion, as by the 1737th flint glass F and Eagle 2000 ^TMThe substrate of making, the both is provided by the healthy and free from worry Corning Incorporated in USA New York.These glass materials have other to be used, and concrete is for example to be used for the production LCD.

The thickness of glass substrate can be at about 0.1mm to about 10mm scope, as at about 0.5mm extremely in the scope of about 3mm.For some soi structure, what for example need is the insulating barrier of thickness more than or equal to about 1 micron (being 0.001mm or 1000nm), with the parasitic capacitance effect of avoiding producing when the soi structure of the standard with silicon/silicon dioxide/silicon structure is worked under high frequency.In the past, this thickness is difficult to realize.According to the present invention, can realize easily that more than or equal to about 1 micron glass substrate 101 thickness of insulating layer is greater than 1 micron soi structure by used thickness simply.The lower thickness limit of glass substrate 101 can be about 1 micron, i.e. 1000nm.

Generally speaking, glass substrate 101 should be enough thick with supporting semiconductor layer 106,108 in the joint technology step and the processing procedure of subsequently photovoltaic SiOG structure 100 being carried out.Although the thickness to glass substrate 101 does not have theoretical upper limit, but it may be disadvantageous surpassing the required or final photovoltaic SiOG of supporting functions structure 100 desired thickness, because the thickness of glass substrate 101 is big more, finish in forming photovoltaic SiOG structure 100 that some processing step will be more difficult at least.

Oxide glass or oxide glass-ceramics substrate 101 can be based on silica.Therefore, SiO in oxide glass or the oxide glass-ceramics ₂Molar percentage can be greater than 30 moles of %, and can be greater than 40 moles of %.Under the situation of glass ceramics, crystalline phase can be other known in mullite, cordierite, anorthite, spinelle or glass ceramics field crystalline phase.Non-glass and glass ceramics based on silica can be used in the enforcement of one or more embodiment of the present invention, but because its higher cost and/or relatively poor performance characteristics, general advantage is less.

Similarly, use,, may need not to be based on the glass substrate of oxide for example for the soi structure that adopts non-silicon-based semiconductor material for some, nonoxide glass for example, but generally do not have an advantage because its cost is higher.As discussed in detail below, in one or more embodiments, glass or glass ceramic baseplate are designed to be complementary with the thermal coefficient of expansion (CTE) of one or more semi-conducting materials (for example, silicon, the germanium etc.) layer that directly or indirectly is engaged in this (for example possible 102,104,106,108 or 110).The CTE coupling has been guaranteed mechanical property desired during the thermal cycle of depositing operation.

For photovoltaic application, glass or glass ceramics 101 can be transparent in visible light, nearly UV and/or IR wave-length coverage, and for example glass or glass ceramics 101 can be transparent in 350nm to 2 micron wave length scope.Because transparent or translucent at least, glass is important in distortion 100C especially, wherein light entered insulator substrate 101 before arriving all the other PV structure 100C.Yet, light does not enter insulator substrate 101 in distortion 100A and 100B, so insulator substrate 101 whether be translucent be what it doesn't matter to a great extent, let alone transparent situation, in this case, selecting insulator substrate 101 based on other standard especially CTE, is not only its cost.

Although glass substrate 101 can be made up of single glassy layer or glass-ceramic layer, can use stepped construction if necessary.When using stepped construction, the most approaching layer that is engaged in this in stacked (for example 102,104 or 110) can have the performance about the substrate 101 be made up of single glass or glass ceramics of this paper discussion.Layer away from knitting layer also can have these performances, but can have loose performance, because they and knitting layer direct interaction not.Under the situation of back, when no longer satisfying the proprietary performance of glass substrate 101, think that glass substrate 101 has finished.

With reference to figure 7,8 and 9, they are collectively referred to as Fig. 7-9 sometimes, show being implemented so that make the processing step of PV structure 100 according to one or more execution modes of the present invention.In Fig. 7, describe technology 200A, in Fig. 8, describe technology 200B and in Fig. 9, describe technology 200C.Each action (step) in these block diagrams has following implication:

202: the surface of preparation donor semiconductor wafer;

203: donor semiconductor wafer is carried out ion inject processing;

204: donor semiconductor wafer is carried out mild oxidation;

205: the photovoltaic structure that the structure part is finished;

206: PVS and donor wafer that part is finished are carried out ion injection processing;

207: the photovoltaic structure that part is finished carries out mild oxidation;

208: between photovoltaic structure (or photovoltaic of partly finishing) base portion and glass, form anodic bonding;

210: glassy layer/PVSF/ peel ply is separated from donor semiconductor wafer; And

212: donor semiconductor wafer and/or PVS base portion are repaired processing.

Figure 10-18 be illustrated in the centre that forms when implementing Fig. 7,8 and 9 technology and near final structure.In Figure 10, arrow indication surface preparation manipulation.In Figure 11, according to some embodiment of the present invention, ion beam (injection hydrogen ion) and total direction thereof that the arrow indication is injected into.In Figure 12, according to some embodiment of the present invention, the arrow indication is O in the surfacing step of peel ply for example ₂Plasma or other material or operation and general direction thereof.In Figure 13, the arrow indication is used to form material and/or operation and total deposition direction thereof of back side contact layer and/or conductive window in certain embodiments of the present invention.In Figure 14, arrow indication be used to mix material (such as dopant) and/or operation (doping process) and total direction thereof of each layer.

In the action 202 of Fig. 7-10, as the preparation alms giver surface 121 for preparing donor semiconductor wafer 120 by polishing, cleaning etc., be suitable for joining to manufacturing the back the PVS layer relatively flat and prepare alms giver surface 121 uniformly.The preparation alms giver surface 121 will form PV structural base 102 or semiconductor layer 106,108 below.For purposes of discussion, semiconductor wafer 120 can be the Si wafer of monocrystalline through mix (n type or p type) substantially, although as discussed abovely use any other suitable semi-conducting material.

In the action 206 of the action 203 of

technology

200A and 200B or technology 200C, also shown in Figure 11,---random layer of structure on the alms giver surface 121 that promptly prepares or the alms giver surface 121 of preparation---carries out one or more ions and injects processing by ion being injected surperficial 121i, so that, construct peel ply 122 at the preparation alms giver surface of donor semiconductor wafer 120 121 times structures weakening region.Although embodiments of the invention are not limited to the ad hoc approach of any formation peel ply 122, but a kind of suitable method indication can be carried out hydrogen ion to the preparation alms giver surface 121 of donor semiconductor wafer 120 and inject processing, so that the generation of beginning peel ply 122 in donor semiconductor wafer 120 at least.

Can use conventional technology to regulate and inject energy, to realize the approximate thickness of epitaxial loayer 122.As an example, but adopt hydrogen ion to inject, although can adopt other ion or different kinds of ions, such as boron+hydrogen, helium+hydrogen or peel off other known in field ion.In addition, can under the situation that does not deviate from the spirit and scope of the present invention, adopt other technology known or that develop afterwards that forms peel ply 122 that is applicable to.

Depend on the number of plies on the top on alms giver surface 121 of parameter, preparation of PV soi structure 100 and bed thickness and any intermediate preparation step that may use,, can make the peel ply 122 of required thin and thick and/or thin and thick rationally such as CMP or FA.If various design limit require epitaxial loayer 122 thicker than desired, such as using in microelectronics, the known quality removal method such as CMP or polishing can be used to peel off the thickness that layer 122 is reduced in the back in action 210.Yet service quality is removed time and the cost that step has increased total manufacturing process, and is unnecessary for PVS 100.For example, in distortion 100A, do not need 102 layers of PVSF thin or thick, preferably, PVSF 102 is enough thick in to serve as stable base portion, is used for finishing processing after a while, but thin again to save material and money.

More opposite problem may take place for PV structure 100, promptly peel ply may be too

thin.In distortion

100B and 100C, PVS 100 needs thick silicon layer, because thicker silicon layer will absorb more light and increase its efficient.The required ability of thick peel ply of structure expectation may surpass available device parameter, therefore can deposit or the epitaxial growth additional silicon after structure epitaxial loayer 122.Can before or after being transferred to glass substrate 101, epitaxial loayer 122 add additional Si to epitaxial loayer 122.If add before, then Si adds a part that becomes the PVS124 that the structure part finishes, and if after add, then Si adds a part that becomes the finishing processing.Similarly, can contact 104 with the back side at PVSF 102 and add semiconductor layer to PVS 100A after on substrate 101.

In the action 207 of the action 204 of

technology

200A and 200B or technology 200C, also shown in Figure 12, the ion that can handle on the donor semiconductor wafer 120 injects surperficial 121i---i.e. and any layer of structure on the alms giver surface 121 of preparation and the alms giver surface 121 of preparation, inject hydrogen ion concentration on the surperficial 121i so that reduce ion for example.For example, can wash or clean donor semiconductor wafer 120, and the composition surface 126 of peel ply 122 is carried out mild oxidation.Mild oxidation treatments can be included in processing, ozone treatment in the oxygen plasma, utilizes hydrogen peroxide, hydrogen peroxide and ammoniacal liquor, hydrogen peroxide and the processing of acid or the combination of these technologies.Expection during these are handled, is that terminal surface group is oxidized to hydroxyl with hydrogen, it so that make the surface hydrophilic on composition surface 126.The processing of oxygen plasma be can at room temperature carry out, and ammonia or acid treatment under the temperature between 25-150 ℃, carried out.

Fig. 8 and 9 action 205 are included in the PVS 124 that the structure part is finished on the donor semiconductor wafer 120 also shown in Figure 13 and 14.The PVS 120 that this part is finished constructs after can being shown in structure peel ply 122 as technology 200B, perhaps is shown in structure peel ply 122 structure before as technology 200C.After both, peel ply has constituted PVS 124 parts of partly finishing naturally at PVS that structure peel ply 122 and part are finished 124.The exposed surface of the PVS 124 that part is finished will become the composition surface 126 that joins glass insulation structure base board 101 in action 208 to.

With reference to Figure 13 and 14, sometimes they are collectively referred to as Figure 13-14, donor semiconductor wafer 120 can be treated to a part of constructing the PVS 124 that partly finishes.Figure 13-14 is illustrated in when taking other step in PVS 124 structures of partly finishing, the epitaxial loayer 122 that forms on the preparation alms giver surface 121 of donor semiconductor wafer 120.In the PVS 124 that the structure part is finished, can take a lot of different actions.For example, the structure of the PVS 124 that part is finished can comprise as shown in figure 13, adds conductive window layer 110 among the 100B as interpolation back side contact layer 104 among the distortion 100B or as being out of shape, or uses middle doping step as shown in figure 14.

Figure 13 illustrates according to one or more execution modes of the present invention, adds as the back side contact layer 104 of distortion 100B or as being out of shape the conductive window layer 110 of 100C.To a great extent, these two technologies are enough similar, to such an extent as to an available block diagram is described.Although described the depositing operation of simplifying, such as CVD or PECVD, this figure also is intended to represent any possible technology, such as epitaxy discussed above and Nei Yanfa.Preferably, within the scope of the invention, the anodic bonding method of action 208 seems better effects if in this process, before the PVS and glass substrate 101 that finishes in the bonding part, back side contact 104 or conductive window layer 110 are deposited on respectively on the PVS 124 that partly finishes, rather than directly are deposited on the glass substrate 101.In on being attached to donor semiconductor wafer 120 with they one of another advantage of being deposited on the PVS 124 that finishes of part be to reduce these layers directly are deposited on process technology limit required on the glass substrate 101, these process technology limit are more responsive for extreme condition.

The ion that Figure 14 illustrates the peel ply 122 that is doped injects surperficial 121i, constitutes sub-surface n-p knot 128.Whether need be out of

shape

100B or 100C, for example, semiconductor layer 106,108 can be made by the doping Si crystal block that receives the phase contra-doping on its surface if depending on.In the exemplary embodiment of distortion 100B, can use p type dopant Doped n-type doping alms giver semiconductor layer 120 in its surface, constitute sub-surface n-p knot.On the contrary, in the exemplary embodiment of distortion 100C, can use n type dopant doped p type doping alms giver semiconductor layer 120 in its surface, constitute sub-surface n-p knot.

Action 208 places in Fig. 7-9 and 15 can join glass substrate 101 to peel ply 122/PVSF

The composition surface 126 of the PVS 124 that 102/ part is finished.Described a kind of suitable joint technology in No. the 2004/0229444th, U.S. Patent application, its whole contents is incorporated herein by reference.This process of part below is discussed, is called as anodic bonding, electrolysis, forms anodic bonding by means of the joint of electrolysis and/or by electrolysis.In anodic bonding/electrolysis process, can carry out the suitable cleaning surfaces of glass substrate 101 (and composition surface 126/ epitaxial loayer 122 is if also it's not true).Afterwards, intermediate structure is directly or indirectly contacted, with the arrangement that obtains to schematically show among Figure 15-16.

Before or after contact, heating comprises the PVS 124 that donor semiconductor wafer 120, epitaxial loayer 122/PVSF 102/ part are finished and the structure of glass substrate 101 under the differential temperature gradient.Glass substrate 101 can be heated to the high temperature of finishing than donor semiconductor wafer 120 and peel ply 122/PVSF 102/ part of PVS124.As an example, the temperature difference between glass substrate 101 and the donor semiconductor wafer 120 (and peel ply 122/PVSF 102/ part finish PVS 124) is at least 1 ℃, although should difference can be up to about 100 ℃ to about 150 ℃.For the glass of the CTE coupling of thermal coefficient of expansion (CTE) and donor semiconductor wafer 120 (as with the CTE coupling of silicon) speech needs this temperature difference, the thermal stress because this helps after a while peel ply 122 and from semiconductor wafer 120 separation.Can make glass substrate 101 and donor semiconductor wafer 120 place temperature in about 150 ℃ of the strain point of glass substrate 101.

In case the temperature difference between glass substrate 101 and the donor semiconductor wafer 120 is stabilized, and just mechanical pressure is applied to intermediate module.Pressure limit can be between about 1 to about 50psi.Apply the destruction that pressure that big pressure for example surpasses 100psi can cause glass substrate 101.Can as material and the thickness thereof that uses, determine suitable pressure according to Fabrication parameter.

Next, applying voltage on intermediate module, for example, is anode with donor semiconductor wafer 120, and is negative electrode with glass substrate 101.The apply alkalescence or the alkaline earth ion that cause in the glass substrate 101 of voltage potential leave from semiconductor/glass interface, enter glass substrate 101.This has realized two functions: (i) structure alkali or alkaline earth ion free interface; And (ii) glass substrate 101 becomes very active, and firmly join on the peel ply 122 of donor semiconductor wafer 120.

Action 210 in Fig. 7-9 and 15 keeps intermediate module a period of time (for example, about 1 hour or shorter) afterwards in the above conditions, removes voltage, and makes the intermediate module cool to room temperature.Separate donor semiconductor wafer 120 and glass substrate 101 then, this step can not comprise that also certain peels off if they also have complete freedom, to obtain the glass substrate 101 that has the PVS 124 that relatively thin peel ply 122/PVSF 102/ part that the semi-conducting material by the alms giver's semiconductor layer 120 that is engaged in this forms finishes.This separation can realize via the fragmentation of the ion implanted region that causes owing to thermal stress.Selectively or in addition, mechanical stress or the chemical etching such as water spray or laser cutting quality can be used for promoting to separate.

With reference to Figure 16, illustrate in greater detail the ion migration area of mentioning with reference to figure 4-6 103.This CONSTRUCTED SPECIFICATION especially is subordinated to glass substrate 101 and the anodic bonding district at the interface between thereon the floor just, back side contact 104 among PVSF 102, Fig. 5 among Fig. 4 of peel ply 122 or the conductive window layer 110 among Fig. 6.Joint technology (action 208) converts the interface between peel ply 122 and the glass substrate 101 to boundary zone 300.Boundary zone 300 preferably includes hybrid region 160 and loss district 230.Boundary zone 300 also can be included near the one or more cation accumulation regions of distal edge in loss district 230.

Hybrid region 160 has the oxygen concentration thickness T 160 of enhancing.When engaging conductive window layer 110, for example, can begin by the component that on Chemical Measurement, is depleted with oxygen, so that strengthen the transmission of oxygen, strengthen this hybrid region 160 from glass substrate.This thickness can limit according to the benchmark concentration of the datum level 170 place's oxygen among the PVS 124 that finishes in peel ply 122/PVSF 102/ part.Datum level 170 is substantially parallel with the composition surface between the PVS 124 that glass substrate 101 and peel ply 122/PVSF 102/ part are finished, and separates with this face with distance D S1.Utilize datum level 170, the thickness of hybrid region 160 generally satisfies following relation:

T160≤200nm，

Wherein T160 is composition surface 126 and with the distance between following: (i) be basically parallel to the surface on composition surface 126 and (ii); 126 farthest the faces from the composition surface, it satisfies following relation:

CO(x)-CO/Ref≥50％，0≤x≤T160，

Wherein CO (x) is an oxygen concentration with the function that changes apart from x on distance composition surface 126, and CO/Ref is the concentration at above datum level 170 place's oxygen, and CO (x) and CO/Ref are by atomic percent.

Generally, T160 will be fully less than 200 nanometers, for example about 50 to the order of magnitude of about 100 nanometers.It should be noted that CO/Ref is generally 0, make above-mentioned relation in most of the cases be reduced to:

CO(x)≥50％，0≤x≤T160。

Relevant with loss district 230, oxide is peeled off or oxide stripped ceramic substrate 101 preferably includes at least cation that some moves along the direction of an electric field that applies, promptly away from composition surface 126 and enter stripping group plate 101.Basic ion, for example Li ^{+ 1}, Na ^{+ 1}And/or K ^{+ 1}Ion is the suitable cation that is used for this purpose, because they generally have the mobility that is higher than the cation (for example alkaline earth ion) that is usually included in other type in oxide glass or the oxide glass-ceramics.

Yet, in enforcement of the present invention, can use the cationic, oxidized thing glass and the oxide glass-ceramics that have except that basic ion, for example only have the oxide glass and the oxide glass-ceramics of alkaline earth ion.The concentration of basic ion and alkaline earth ion can change in wide region, and representative concentration is between 0.1 and the 40wt% that press oxygen calculating.Preferred alkali and alkaline earth ion concentration under the situation of basic ion be calculate by oxygen 0.1 to 10wt% and be the 0-25wt% that calculates by oxygen under the situation at alkaline earth ion.

The electric field that applies in engagement step (action 208) makes cation (cation) further move to glass substrate 101, forms loss district 230.Special expectation forms loss district 230 when oxide glass or oxide glass-ceramics comprise basic ion, because the operation of known this ion interference semiconductor device.Alkaline earth ion is Mg for example ^{+ 2}, Ca ^{+ 2}, Sr ^{+ 2}And/or Ba ^{+ 2}Also can disturb the operation of semiconductor device, so the loss district also preferably has the ion that these concentration reduce.

The loss district 230 that has been found that previous formation is stable in time, though with PV structure 100 be heated to joint technology in the suitable even high temperature that be higher than the temperature of using in the joint technology in a way of temperature that uses, also be stable.Owing at high temperature form, loss district 230 is especially stable under the normal running of PV structure and formation temperature.These Considerations guarantee that basic ion and alkaline earth ion are using or can not get back to semi-conducting material 104 from oxide glass or oxide glass-ceramics 101 diffusions during further device is handled, and this is the important benefit from using electric field to obtain as the part of joint technology.

Realize strong bond as selection manipulation parameter, obtain the required operating parameter in such loss district 230, that is: this loss district has desired width and the cation concn that has desired reduction for all relevant cations, can easily be determined from the present invention is open by those skilled in the art.When existing, loss district 230 is the property features according to the PV structure 100 of one or more execution modes manufacturings according to the present invention.

As shown in figure 17, after separation, resulting structure can comprise glass substrate 101 and be engaged in the peel ply 122 of this semi-conducting material.Just the face that dissociates 123 of the soi structure after peeling off can demonstrate excessive surface roughness 123A (illustrating abstractively) in Figure 17, silicon layer thickness that may be excessive (for microelectronic applications more may) and silicon layer such as damaging (for example, because the formation of hydrogen ion and decrystallized silicon layer).

Action 212 in Fig. 7-9 and 18 can be carried out one or more finishing structures 130 to the PVS 124 that donor semiconductor wafer 120, PVSF 102 and/or part are finished.This finishing structure 130 can comprise for example one or more son processing.For example, finishing processing 130 can comprise the various scribing processing of the form of structure PVS distortion 100B and 100C.This scribing step that is known in the art can be before other finishing processing 130, afterwards or with it in conjunction with finishing.

Another kind of finishing processing 130 can comprise the semiconductor thickness that increases peel ply 122.Under the situation of distortion 100A, for example add semi-conducting material before the interior epitaxial growth of contact layer 104 overleaf.In certain embodiments,

expectation semiconductor layer

106 and 108 final combination thickness for example should be greater than 10 microns (that is, 10000nm) and less than about 30 microns.Therefore, should construct the peel ply 122 of suitable thickness, and increase it, up to constituting needed thickness with additional semiconductor layers 132 (for example Si).Increase with additional silicon layer 132 also can comprise the doping step.In the past, the thickness of decrystallized silicon layer is on the order of magnitude of about 50-150nm, and according to injecting energy and injection length, the thickness of peel ply 122 is on the order of magnitude of about 500nm.Yet, as the microelectronics soi structure, for PVSF 102, can construct thin peel ply 122, and amorphous si-layer is also by attenuate necessarily, and in finishing processing, adds more semi-conducting material.

Also according to action 212, processings of dissociating after can carrying out the face 123 that dissociates, but it can comprise the face 123 that dissociates is polished annealing in process with reduction roughness 123A.In addition, in order to realize being out of shape the exemplary embodiment of 100B, finishing is handled and can be comprised application conductive window layer 110, as the deposition tin indium oxide.On the contrary, in order to realize being out of shape the exemplary embodiment of 100C, finishing processing can comprise use back side contact layer 104, based on conducting metal or based on the layer of metal oxide, such as film based on aluminium by LPE, CVD or PECVD deposition.As discussed above, back side contact layer 104 also can form by epitaxial growth or the interior epitaxial growth such as nickle silicide.

With regard to the feature of final products that the PVS 124 that finishes of part has more expections, it is essential that less finishing is handled.On the contrary, on insulator substrate 101, form PVSF 102 structures separately, substrate 101-PVSF 102 combination as photovoltaic structure can not be different from the semiconductor structure on any other insulator of No. the 2004/0229444th, U.S. Patent application, in this case, the proprietary finishing processing of several PVS is essential.Yet, add man-hour repairing, basic single crystalline layer as photovoltaic structure base portion 102, has been relaxed and is used for operating parameter and expanded the available options that is used to select and result's scope.

Particularly, the formation of PVSF 102 or the PVS 124 that finishes of part allows that greater flexibility is arranged when the advanced many knot PVS device of structure.For example, the PVSF of crystal Si goes up and makes up, and the producer can adopt the crystal Si of different specific heats to GaAs, Ge and GaInP ₂, to construct various GaAs, Ge and GaInP ₂Many knots layer.Selectively, as described in the preferred embodiment of Figure 21, PVSF 102 can comprise Ge or GaAs, and perhaps PCPVS 124 can comprise the Ge/GaAs layer through mixing.

Referring now to above-mentioned SiOG technology and further details optional embodiment of the present invention is described.For example, separate peel plies 122 from donor semiconductor wafer 120 and can produce first of donor semiconductor wafer 120 second of face and peel ply 122 face 123 that dissociates that dissociates.As previously discussed, finishing can be handled 130 and put on second of peel ply 122 face 123 that dissociates.Additionally or selectively, can (utilize above-mentioned one or more technology) and will repair and handle 130 and put on first of donor semiconductor wafer 120 face that dissociates, as polishing.

In another embodiment of the present invention, donor semiconductor wafer 120 can be the part of donor structure, comprises substantially being the donor semiconductor wafer 120 of monocrystalline, and is arranged on the epitaxial semiconductor layer on the donor semiconductor wafer 120.(can in examining No. the 11/159th, 889, U.S. Patent application, waiting jointly of submitting on June 23rd, 2005 find the details of epitaxially grown semiconductor layer under the SOI situation.) so peel ply 122 can form (and also can comprise some single-crystal donor semi-conducting material) by epitaxial semiconductor layer basically from wafer 120.Therefore, above-mentioned finishing can be handled the peel ply that is combined to form 122 that put on basically by epitaxial semiconductor material and/or epitaxial semiconductor material and the single-crystal semiconductor material face 123 that dissociates.

In addition, but photovoltaic cell building method automation in the system that is used to form photovoltaic structure 100 of one or more execution modes of the present invention.This system can comprise: the PVS processing components, and it is handled the PV structure and is used for processing; And photovoltaic processing assembly.The photovoltaic processing assembly can comprise various subsystems, such as preparation or conditioning system and transfer or mating system, is used to prepare by the handled PV structure 100 of the processing components of PV semiconductor-on-insulator.

For example, when preparation comprised the peel ply 122 of the PV structure 124 that PVSF 102 or part are finished, processing components can be transmitted in the PVS processing components and locate the PV structure 100 that need finish and take place to allow anodic bonding.In the PVS processing components, join the further transmission of structure 101 of PVSF 102 or the PVS 124 that finishes of part and the

action

210 and 212 of peeling off and repair that the location can allow to add to and take place respectively.

With reference to Figure 19,, described the simplification of PVS 100 and tied distortion 100D more according to one or more preferred implementations.Many knot PVS 100D can be similar to the PVS of Fig. 3, but have great difference, and such as replacing crystal Ge wafer substrate with glass substrate 101, the crystal Ge film of peeling off simultaneously is at the top of glass substrate.Can be 8 x 10 at 100Kev, dosage ¹⁶Condition under hydrogen is injected thickness is that 500 microns, resistivity are the p type germanium or the GaAs wafer of 0.01-0.04 ohm-cm.Carry out oxygen plasma treatment so that the oxidized surface group then by the chemical devices clean wafer, and to it.After clean, mix or the covering of unadulterated Ge film with GaAs wafer insertion settling chamber and with one deck, its thickness depends on designs.The deposition of germanium can utilize various technology to finish on the GaAs wafer, comprises plasma enhanced chemical vapor deposition, Assisted by Ion Beam sputtering sedimentation, evaporation or chemical gaseous phase extension.The doping of Ge layer (p type) can utilize As or P to realize.Then, cleaning thermal coefficient of expansion with the standard washing technology is alkali-aluminium borosilicate glass wafer of 1mm with germanium coupling and thickness, as cleaning agent and distilled water afterwards by the diluted acid clean surface.Make these two wafers contact and place it in the mating system then.Can be at 450C and 400C---be respectively the temperature of the GaAs wafer that covers of glass and germanium wafer or Ge, apply the voltage of 1000V at the two ends of wafer, kept 20 minutes in cooling with before removing the voltage that applies.Joining the germanium of glass or the film of GaAs/Ge sandwich construction to can separate from the parent wafer, realizes the strong bond with glass simultaneously.Therefore in Figure 19, Reference numeral can have following implication:

101: glass substrate;

104: the Ge film through mixing is as back side contact layer;

The 105:GaAs tunnel junction;

106:p type GaAs;

108:n type GaAs or GaInP;

The 107:AlGaAs tunnel junction;

110: the conductive window layer.

Can polish, anneal or repair the optional chip glass that has germanium or GaAs/Ge film then, to remove impaired germanium or GaAs top layer and good quality laminar surface.This wafer can be used as the substrate epitaxial structure of growing, so that constitute solar cell.Examples of material can comprise GaAs, GaInP/GaAs, Ga _XInyP/Gac, In _dAs/Ge and other materials as known in the art.Various technologies deposit epitaxial film be can be used for, CVST (transmission of enclosure space gas phase), MOCVD (metal-organic chemical vapour deposition (CVD)), MBE (molecular beam epitaxy) and other known technology comprised.Can adopt some surface passivation Window layer such as the broad-band gap epitaxial loayer of AlGaAs, InGaP or ZnSe and other to seal or passivation layer, and surface treatment is used to finish battery.

Can ohmic contact be used for various structures according to designs, flow to next contact point from a contact point,, when two electrodes of drawing from device are coupled with load, just finish circuit to allow complete circuit but basic requirement is the electric current that is produced.So, as shown in Figure 6, not needing back side contact layer is outermost layer with respect to semiconductor layer.For example, if suitably separate to form suitable circuit and electric current structure, then back side contact 104 can be positioned at the top, rather than semiconductor layer 106 below.

Although described the present invention herein, should be appreciated that these execution modes only are the explanations to principle of the present invention and application with reference to specific implementations.Therefore should be appreciated that and to carry out numerous modifications and can design other arrangement illustrated embodiment, and do not deviate from the spirit and scope of the present invention that are defined by the following claims.

Claims

1. photovoltaic device, it comprises:

Insulator structure;

Peel ply; And

Be integral and be close to the conductive layer of described insulator structure with described peel ply; And

Join described insulator structure on described conductive layer and the described peel ply cement,

Wherein, described peel ply comprises the peel ply of basic monocrystalline of the donor semiconductor wafer of basic monocrystalline.

2. photovoltaic device as claimed in claim 1, it is characterized in that described peel ply is based on being selected from down the monocrystal material of organizing: the silicon (SiGe) of silicon (Si), doped germanium, carborundum (SiC), germanium (Ge), GaAs (GaAs), gallium phosphide (GaP) and indium phosphide (InP).

3. photovoltaic device as claimed in claim 1 or 2 is characterized in that, the cement that described insulator structure is joined on described conductive layer and the described peel ply is the anodic bonding agent that comprises the boundary zone.

4. photovoltaic device as claimed in claim 3 is characterized in that, described boundary zone comprises hybrid region and loss district.

5. as each the described photovoltaic device in the above claim, it is characterized in that, also comprise:

The first ion migration area in described insulator; And

Pass the second ion migration area of described conductive layer and described peel ply.

6. as each the described photovoltaic device in the above claim, it is characterized in that described conductive layer comprises based on the material of metal with based on the material of metal oxide.

7. as each the described photovoltaic device in the above claim, it is characterized in that described peel ply comprises the semiconductor layer of doping, described conductive layer comprises back side contact layer or conductive window layer.

8. photovoltaic device as claimed in claim 7 is characterized in that, the semiconductor layer of described doping comprises n type semiconductor layer, p type semiconductor layer or has the n type and the semiconductor of p type doped region joint layer.

9. photovoltaic device as claimed in claim 7 is characterized in that:

Described back side contact layer comprises aluminium, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium or silicide; And

Described conductive window layer comprises the indium oxide of doped tin, the zinc oxide of adulterated al, the zinc oxide or the carbon nano-tube of doped with boron.

10. as each the described photovoltaic device in the above claim, it is characterized in that, it also comprise be configured among the described peel ply or on and away from a plurality of photovoltaic device layers of described insulator substrate.

11. photovoltaic device as claimed in claim 10 is characterized in that, described a plurality of photovoltaic device layers comprise at least one semiconductor layer, at least one conductive layer and at least one passivation layer.

12. photovoltaic device as claimed in claim 10 is characterized in that, at least one in described a plurality of photovoltaic device layers comprises epitaxially grown crystal layer.

13. photovoltaic device as claimed in claim 1 is characterized in that, also comprises with described peel ply all-in-one-piece and is close at least one additional photovoltaic device layer of described insulator substrate.

14. each the described photovoltaic device as in the above claim is characterized in that, comprising:

Insulator structure;

Be close to the peel ply of described insulator structure;

With described insulator structure and the articulate anodic bonding agent of described peel ply; And

Away from described insulator substrate and among the described peel ply or on a plurality of photovoltaic device layers;

15. photovoltaic device as claimed in claim 14 is characterized in that, also comprises:

The first ion migration area in described insulator; And

The second ion migration area in described peel ply.

16., it is characterized in that described anodic bonding agent comprises the boundary zone as claim 14 or 15 described photovoltaic devices.

17. photovoltaic device as claimed in claim 16 is characterized in that, described boundary zone comprises hybrid region and loss district.

18. each the described photovoltaic device as in the claim 14 to 17 is characterized in that, described a plurality of photovoltaic device layers comprise semiconductor layer and conductive layer.

19. photovoltaic device as claimed in claim 18 is characterized in that, described a plurality of photovoltaic device layers also comprise at least more than one semiconductor layer, at least more than one conductive layer and at least one passivation layer.

20. photovoltaic device as claimed in claim 18 is characterized in that, described conductive layer comprises based on the material of metal or based on the material of metal oxide.

21. photovoltaic device as claimed in claim 14 is characterized in that, described a plurality of photovoltaic device layers comprise semiconductor layer, back side contact layer and the conductive window layer of doping.

22. photovoltaic device as claimed in claim 21 is characterized in that, the semiconductor layer of described doping comprises n type semiconductor layer, p type semiconductor layer or has the n type and the semiconductor of p type doped region joint layer.

23. photovoltaic device as claimed in claim 21 is characterized in that:

24. photovoltaic device as claimed in claim 14 is characterized in that, at least one in described a plurality of photovoltaic device layers comprises epitaxially grown crystal layer.

25. a method that forms photovoltaic structure, described method comprises:

Structure has the peel ply of conductive layer on donor semiconductor wafer; And

Described peel ply is transferred to insulator substrate.

26. method as claimed in claim 25 is characterized in that, also comprises:

Described donor semiconductor wafer is carried out ion implantation technology, to construct the peel ply of described donor semiconductor wafer;

Described peel ply is joined on the described insulator substrate; And

Separate described peel ply from described donor semiconductor wafer, thereby expose at least one face that dissociates.

27. method as claimed in claim 26 is characterized in that, also comprises described at least one face that dissociates is carried out multiple finishing processing.

28. method as claimed in claim 27 is characterized in that, described at least one face that dissociates comprises first of described donor semiconductor wafer second of face and the described peel ply face that dissociates that dissociates.

29. method as claimed in claim 28 is characterized in that, second of the described at least peel ply face that dissociates is applied described multiple finishing processing.

30. method as claimed in claim 28 is characterized in that, first of the described at least donor semiconductor wafer face that dissociates is applied described multiple finishing processing.

31. method as claimed in claim 27, it is characterized in that described multiple finishing processing is selected from down group: scribing, structure back side contact layer, structure conductive window layer, polishing, annealing, cleaning, doping, structure passivation layer, structure encapsulated layer and the additional semi-conducting material of increase.

32. method as claimed in claim 26 is characterized in that, described engagement step comprises:

Heat at least one in described insulator substrate and the described donor semiconductor wafer;

Described insulator substrate is directly or indirectly contacted with the peel ply of described donor semiconductor wafer;

With described insulator substrate and described peeling laminated being in the same place; And

On described insulator substrate and described donor semiconductor wafer, apply voltage potential to induce joint.

33. each the described method as in the claim 25 to 32 is characterized in that described donor semiconductor wafer comprises the donor semiconductor wafer of basic monocrystalline, comprises silicon, germanium or GaAs.

34. as each the described method in the claim 25 to 32, it is characterized in that described donor semiconductor wafer is selected from down group: the silicon (SiGe) of silicon (Si), doped germanium, carborundum (SiC), germanium (Ge), GaAs (GaAs), gallium phosphide (GaP) and indium phosphide (InP).

35. each the described method as in the claim 25 to 32 is characterized in that described donor semiconductor wafer comprises the donor semiconductor wafer of basic monocrystalline, the peel ply of described separation is formed by the donor semiconductor wafer material of described monocrystalline substantially.

36. as each the described method in the claim 25 to 32, it is characterized in that, described donor semiconductor wafer comprises donor semiconductor wafer and the epitaxial semiconductor layer that is arranged on the described donor semiconductor wafer, and the peel ply of described separation is formed by described epitaxial semiconductor layer substantially.

37. each the described method as in the claim 25 to 32 is characterized in that, the peel ply that structure has a described conductive layer comprises: epitaxy, Nei Yanfa, peel off, gas phase transmission, vapour deposition, ion injects and one or more of oxidation.

38. each the described method as in the claim 25 to 32 is characterized in that, described conductive layer comprises based on the material of metal or based on the material of metal oxide.

39. each the described method as in the claim 25 to 32 is characterized in that described peel ply comprises the semiconductor layer of doping, described conductive layer comprises back side contact layer and conductive window layer.

40. each the described method as in the claim 25 to 32 is characterized in that, the semiconductor layer of described doping comprises n type semiconductor layer, p type semiconductor layer or has the n type and the semiconductor of p type doped region joint layer.

41. method as claimed in claim 39 is characterized in that:

42. each the described method as in the claim 25 to 41 is characterized in that, described photovoltaic structure comprises single joint photovoltaic structure or engages photovoltaic structure more.

43. each the described method as in the claim 25 to 41 is characterized in that, also is included in described peel ply is transferred to before the described insulator substrate, and described peel ply is carried out at least a finishing processing.

44. method as claimed in claim 43 is characterized in that, before described peel ply was transferred to described insulated substrate, described at least a finishing processing produced at least one additional photovoltaic device layer.

45. the method as each the described formation photovoltaic structure in the claim 25 to 44 is characterized in that, described method comprises:

Donor semiconductor wafer is carried out ion implantation technology, on described donor semiconductor wafer, to construct peel ply;

Between described peel ply and described insulator substrate, form anodic bonding by electrolysis;

Separate described peel ply from described donor semiconductor wafer, thereby expose at least one face that dissociates; And

Construct the described peel ply of a plurality of next-door neighbours and away from the photovoltaic structure layer of described insulator substrate.

46. method as claimed in claim 45 is characterized in that, also comprises described at least one face that dissociates is carried out multiple finishing processing, wherein, constructs a plurality of photovoltaic structure layers and comprises at least a in the described multiple finishing processing.

47. method as claimed in claim 46 is characterized in that, described at least one face that dissociates comprises first of described donor semiconductor wafer second of face and the described peel ply face that dissociates that dissociates.

48. method as claimed in claim 47 is characterized in that, second of the described at least peel ply face that dissociates is applied multiple finishing processing.

49. method as claimed in claim 47 is characterized in that, described multiple finishing processing is applied to first of the described at least donor semiconductor wafer face that dissociates.

50. method as claimed in claim 46, it is characterized in that described multiple finishing processing is selected from down group: scribing, structure back side contact layer, structure conductive window layer, polishing, annealing, cleaning, doping, structure passivation layer, structure encapsulated layer and the additional semi-conducting material of increase.

51. method as claimed in claim 45 is characterized in that, described step by electrolysis formation anodic bonding comprises:

Described insulator substrate is directly or indirectly contacted with the described peel ply of described donor semiconductor wafer;

Applying voltage potential on described insulator substrate and described donor semiconductor wafer engages with inductive anode.

52. method as claimed in claim 45 is characterized in that, described donor semiconductor wafer comprises the donor semiconductor wafer of basic monocrystalline, comprises silicon, germanium or GaAs.

53. method as claimed in claim 45, it is characterized in that described donor semiconductor wafer is selected from down group: silicon (Si), Ge-doped silicon (SiGe), carborundum (SiC), germanium (Ge), GaAs (GaAs), gallium phosphide (GaP) and indium phosphide (InP).

54. method as claimed in claim 45 is characterized in that, described donor semiconductor wafer comprises the donor semiconductor wafer of basic monocrystalline, and the peel ply of described separation is formed by the donor semiconductor wafer material of described monocrystalline substantially.

55. method as claimed in claim 45, it is characterized in that, described donor semiconductor wafer comprises donor semiconductor wafer and the epitaxial semiconductor layer that is arranged on the described donor semiconductor wafer, and the peel ply of described separation is formed by described epitaxial semiconductor layer substantially.

56. method as claimed in claim 45 is characterized in that, constructs that a plurality of photovoltaic structure layers comprise epitaxy, Nei Yanfa, peel off, gas phase transmission, vapour deposition, ion injects and one or more of oxidation.

57. method as claimed in claim 45 is characterized in that, described a plurality of photovoltaic structure layers comprise semiconductor layer and conductive layer.

58. method as claimed in claim 33 is characterized in that, described conductive layer comprises based on the material of metal or based on the material of metal oxide.

59. method as claimed in claim 45 is characterized in that, described a plurality of photovoltaic structure layers comprise semiconductor layer, back side contact layer and the conductive window layer of doping.

60. method as claimed in claim 35 is characterized in that, the semiconductor layer of described doping comprises n type semiconductor layer, p type semiconductor layer or has the n type and the semiconductor of p type doped region joint layer.

61. method as claimed in claim 35 is characterized in that:

62. method as claimed in claim 45 is characterized in that, described photovoltaic structure comprises single joint photovoltaic structure or engages photovoltaic structure more.

63. a system that is used to form photovoltaic structure, described system comprises:

The photovoltaic structure processing components, and

The photovoltaic structure processing assembly,

Wherein, described photovoltaic structure processing assembly comprises preparation system and transfer system, and described preparation system preparation is by the handled peel ply of described photovoltaic structure processing components, and described transfer system is transferred to insulator substrate with described peel ply.

64., it is characterized in that each peel ply had conductive layer as the described system of claim 63 before being transferred to described insulated substrate.

65., it is characterized in that as claim 63 or 64 described systems, also comprise mating system, wherein, described mating system is configured to form anodic bonding by electrolysis between described insulated substrate and described peel ply.

66. as each the described system among the claim 63-65, it is characterized in that, also comprise conditioning system, wherein, described conditioning system is configured to carry out at least a finishing processing that is selected from down group: scribing, structure back side contact layer, structure conductive window layer, polishing, annealing, cleaning, doping, structure passivation layer, structure encapsulated layer and increase additional semi-conducting material.