TW200814341A - Thin film photovoltaic structure and fabrication - Google Patents

Abstract

Novel photovoltaic structures comprising an insulator structure bonded to an exfoliation layer, preferably of a substantially single-crystal donor semiconductor wafer, and at least one photovoltaic device layer, such as a conducive layer, and systems and methods of production of a photovoltaic device, comprising creating on a donor semiconductor wafer an exfoliation layer and transferring the exfoliation layer to an insulator substrate.

Description

200814341 IX. INSTRUCTIONS: [Inventives The invention relates to a manufacturing system, method and product for a thin film photovoltaic structure, which preferably has a single crystal film, and the use of the improved process comprises a special transfer of photovoltaic structure or partial completion The photovoltaic structure is bonded to the insulator substrate and the anode is bonded to the insulator substrate. [Prior Art] The φ structure (PVS) is a special type of semi-conductor that converts photons into current. Basically, the device needs to perform two functions: light-generating charge carriers (electrons and holes) in the absorbing light material, and separating the charge carriers to the conductive contacts that carry the current. This transformation is known as the photovoltaic (PV) effect and enables - for use in solar cells, which converts light energy into electrical energy, and the research field associated with solar cells is known as photovoltaic. Some pVS are semiconductor structures on insulators (SOI). Referring to Figures 1, 2 and 3, the block diagram shows the photovoltaic structure of the single junction, the double junction, the spring and the two junctions, respectively. In these figures the reference numbers have the following

• column meaning A101 Ge substrate; A103/105 1· 4eV GaAs battery; A107 gate, pole contact; A201 Ge-based fcA203 L4eV GaAs battery; A207 AlGaLnP or AlGaAs tunnel interface; Α209/2Π L9eV InGaP battery; A213 gate contact A301 0.7eV Ge battery and substrate; A305 GaAs tunneling junction; A307/309 L4eVGaAs battery; A311 tunneling junction; A313/315 1.9 eV InGaP battery; A317 gate contact. The Ge substrate shown is a single crystal germanium wafer. Although efficiency has increased by 1% to 5% per year over the past few years, the greater efficiency has increased from the junction, with each additional junction increasing by approximately 4.5%. The advantage of the external junction of the 200814341 is due to the ability of the pVS device to absorb light across different frequency bands and convert it into a current, which makes it possible to use a mechanically strong, large-area, less expensive solar cell. GaAs is the main method for improving conversion efficiency and improving outdoor reliability. GaAs has a band gap of 1.42 eV, which is close to the optimum value of the band gap energy of the solar cell conversion (1.5 eV). Unlike the Shi Xi battery, GaAs batteries are quite sensitive to heat. Another major advantage of gallium arsenide and its alloys as PV cell materials is the ability to make corrections for a wide range of designs. The most important is the high efficiency multi-junction solar cell, which can utilize GaAs film or other ΙΠ-V as the main material, such as GainP2 and GalnAs on the large fast Ge single crystal substrate. The highest verification efficiency of GaAs multi-junction solar cells is greater than 37%. Ge substrates are used in these batteries because GaAs and Ge match very well in lattice spacing and thermal expansion.

Substrates with a price lower than that of crystalline germanium containing glass and ceramic alumina have been studied as III-V compound semiconductor solar cell applications. In some examples, molten vermiculite coated with a thick Ge film and ceramic alumina are used as a coating substrate for epitaxially growing high performance GaAs/InGaP solar cells. The Ge film (micron) is deposited on a thermally expanded phase matching polycrystalline alumina (p-Al2〇3).

The Ge film subsequently covers different metal and oxide films and is subjected to rapid recrystallization by rapid thermal processing. An average particle size of greater than 1 leg can be achieved. The GaAs epitaxial layer was grown on these large (&gt;1 leg) thin (about 2 micrometers) Ge layers using GSVT technology. These Ga/As/Ge/ceramic structures have been proposed as tandem junction devices. 200814341 HI_V semiconductor thin film solar cells on cover glass are very beneficial for reducing the weight of the substrate and reducing the cost of the integrated process. The solar cell can in fact be constructed with incident solar radiation on the side of the cover glass substrate. Research has investigated the deposition of polycrystalline films on glass substrates for solar cell applications. The crystal quality limits the performance of the ΠΙ-ν solar cell with a single crystal film. As previously mentioned, there is no low cost structure on a glass substrate that has resulted in a GaAs cell with high efficiency (&gt; 30%). Thus, relying on low cost and processing of transparent glass and glass substrates and products as needed will overcome the related prior art problems. • As a microelectronic semiconductor drawing and for ease of presentation, the following is a description of the structure of a semiconductor on an insulator (SOI). The description of the particular form of the S0I structure will make the explanation of the invention easier and is not intended to be construed as limiting the scope of the invention. In this context, s〇I generally refers to a semiconductor-on-insulator structure, including a non-limiting structure on the insulator, such as a germanium-on-glass (Si〇G) structure. Similarly, the abbreviation for Si〇G is generally a semi-finished, and the body is formed on a glass containing an unrestricted dream structure on the glass. Along the sinking term, it is also expected that the semiconductor will be on the glass ceramic, including the unrestricted stone structure on the glass ceramic. The abbreviation S0I contains a Si〇G structure. Various methods for achieving the SOI structure include G) epitaxially growing Si on a lattice-matched substrate; (2) bonding the early crystal dream wafer to another dream wafer, and growing an Si 〇 2 oxide layer on the eve. Then polishing or engraving the upper wafer down to, for example, 0·05 to 3·3 μm (50-300 pass) layer of single crystal; and (3) ion implantation, in which ions (for example, hydrogen or oxygen ions) are implanted In the case of oxygen ion 200814341 implantation, for example, a buried oxide layer is formed in the case of being implanted, and the thin wafer layer is separated (epitaxial) from the germanium wafer as another Si wafer. The oxide layer is bonded. After the thin nightmare film is epitaxially grown from the Shixi material wafer, chemical mechanical polishing (CMP) can also be used to process the SOI structure. Unfortunately, Qip is unable to evenly remove material throughout the thin tantalum film surface during polishing. The general surface non-uniformity (standard deviation / average removal thickness) is in the range of 3 - 5% of the semiconductor film. As more enamel film thickness is removed, the film thickness changes relatively worse. Compared with SOI's consideration of electronic applications, the photovoltaic structure is more financially constrained, although this defect still negatively affects the photovoltaic structure and the nature of the pool. Although this modification technique such as CMP can improve the surface characteristics of the voltamate structural defect tolerance, the price is too high. Therefore, it is necessary to add the advantages of the manufacturing progress of the SOI structure to the specifications of the photovoltaic structure manufacturing, and at the same time minimize the disadvantages of the advanced technology of the related SOI structure manufacturing. SUMMARY OF THE INVENTION In accordance with one or more embodiments of the present invention, a system for forming a photovoltaic structure, the method and apparatus includes generating an epitaxy and transferring it to an insulator structure. The epitaxial layer can be produced from a donor semiconductor wafer. The donor semiconductor and the outer layer are preferentially composed of a single crystal semiconductor material. The external contact preferentially comprises one or more photovoltaic device layers, such as conductive layers, which are produced prior to transfer to the insulator. The transfer external seal preferentially includes formation by electrolysis and anodic bonding between the outer ride and the insulating layer filament, and the use of the thermomechanical stress to separate the outer county from the donor semiconductor. After the epitaxial layer is transferred to 200814341, the 'g edge base is reversed, one or more photovoltaic devices can also be produced in the outer county-赃fang. Before the treatment of He Wailin or Wei Keju, the surface of the photovoltaic device can be produced by modifying the process and modifying the process. According to the _-item or the rural item, the system, the method and the device for stealing the semiconductor on the insulator structure are transferred into the photovoltaic structure base __the semiconductor crystal mad transfer photovoltaic structure foundation to the insulator substrate, and a set of deposition A plurality of photovoltaic structures are based on ρν. The transfer can be φ including the photovoltaic structure, the anode is bonded to the insulator structure, and the photovoltaic structure is separated from the donor and semiconductor wafers. In an embodiment of the invention, a system for forming a photovoltaic semiconductor on an insulator, the method and apparatus include partially generating a photovoltaic cell on a semiconductor wafer, and transferring partially completing the photovoltaic junction age On the insulator substrate. The transfer includes a photovoltaic cell that partially bonds the photovoltaic cell to the insulator and the photovoltaic cell is separated from the donor semiconductor wafer. </ RTI> According to one or more embodiments of the present invention, a system, method and apparatus for forming a photovoltaic semiconductor structure comprises forming a plurality of photovoltaic cells on a partially completed donor semiconductor wafer, and transferring the portion to Insulator substrate. The transfer involves the partial bonding of the photovoltaic cell to the insulator structure and the photovoltaic cell completed by the separation of the donor semiconductor wafer. In accordance with one or more embodiments of the present invention, a system, method, and apparatus for forming a photovoltaic device includes: applying a donor semiconductor wafer to an ion implantation process to produce an epitaxial layer in a donor semiconductor wafer; bonding the epitaxial layer to The 200811341 edge body substrate; the epitaxial layer is separated by the donor semiconductor wafer, and the epitaxial layer is used as the tomb base of the photovoltaic structure; the summer generation produces two sets of multiple photovoltaic structures on the basis of the first voltaic structure. In accordance with one or more embodiments of the present invention, a system, method, and apparatus for forming a photovoltaic device includes: applying a donor semiconductor wafer to an ion implantation process to produce an epitaxial layer in a donor semiconductor wafer; bonding the epitaxial layer to An insulator substrate; generating a partially completed photovoltaic cell on the epitaxial layer; bonding the outer layer to the insulator paper separated by the donor semiconductor wafer and having a portion of the completed photovoltaic cell, thereby exposing at least one split a surface; and modifying at least one of the split surfaces. In accordance with one or more embodiments of the present invention, a system, method, and apparatus for forming a photovoltaic device includes: forming a partially completed photovoltaic cell on a donor semiconductor wafer; partially completing a photovoltaic cell and a donor semiconductor The surface of the wafer is also subjected to an ion implantation process to produce an epitaxial layer in the donor semiconductor wafer; the epitaxial layer is bonded to the insulator substrate; and the semiconductor wafer is separated by a portion of the semiconductor wafer. The layer is thus exposed to a surface that is less than one split; and at least one split surface is modified. In the item or the embodiment, the bonding step includes: heating at least one of the insulator substrate and the donor semiconductor wafer; causing the insulator substrate to directly or indirectly contact the outer layer of the donor semiconductor wafer; and applying a voltage to the insulator level and applying Both ends of the bulk semiconductor wafer are bonded to each other. The insulator level and the temperature of the donor semiconductor wafer can be increased to within 150C of the insulator hearing change point. The temperature of the insulator substrate and the donor semiconductor wafer can be increased to different values. The voltage across the insulator substrate and the donor semiconductor wafer is approximately 10 to 10,000 volts for 200814341. The stress is generated by cooling the bonded insulator, the epitaxial layer, and the donor semiconductor wafer, and the cake breaks in the ionic brittleness. The ion-deficient phase defines a boundary of the external seal in the donor semiconductor wafer. The different heating and ion-defective phases of the ion-defective phase and the peripheral wafer promote the purity of the epitaxial layer sub-defects. It produces a film of the body bonded to the insulator. At least one of the split surfaces includes a first split surface of the donor semiconductor wafer and a second split surface of the outer bet. Regarding the first split surface associated with the donor semiconductor wafer, the finishing process can include processing the donor semiconductor wafer for reuse. Regarding the second split surface associated with the epitaxial layer, the modification process may include completing a partially completed photovoltaic cell. According to one or more preferred embodiments of the present invention, the new solar cell is primarily a single crystal Ge, Si or GaAs film on a transparent glass or glass ceramic substrate. In the case of a GaAs-based battery, an advantage is that a layer can exist between the substrate and the single-crystal GaAs layer. The Ge layer can be doped to use the substrate _ as the underlayer of the multi-junction solar cell (ie, the backside contact layer). The glass or glass glazing substrate is swellable to match Ge, Si, GaAs or Ge/GaAs. The Ge, Si, GaAs or Ge/GaAs film strongly bonded single crystal layer can be formed on a glass or glass ceramic by an anodic bonding process as described in U.S. Patent Application Serial No. 2004/022944. The process begins with the implantation of hydrogen or hydrogen and helium into a Ge, Si or GaAs wafer, and in the case of GaAs, the tantalum film can be deposited on the surface of the GaAs wafer. The Ge, Si or Ge-coated GaAS wafer is then bonded to the glass substrate, followed by separation of the Ge, Si, GaAs or GaAs/Ge film structures. The resulting s〇G structure is polished to remove the damaged area and expose a good quality single crystal semiconductor layer. It is possible to use the S0G structure as a subsequent epitaxial growth multilayer—SivGe; also a template for your GalnAs to form a solar cell. In addition to the bulkability of the glass, the glass has a relatively high strain point sufficient to withstand subsequent deposition conditions. A typical photovoltaic cell structure includes a P-type-essential semiconductor-n-type (P+n), a metal-insulator-semiconductor (MIS), a so-called tandem junction cell, a multi-junction cell, and a composite pn multilayer structure, but the present invention It is not limited to these structures. Those skilled in the art of photovoltaics are able to produce partially completed photovoltaic cells on a donor semiconductor wafer in accordance with desired product characteristics such as single junctions and multiple junctions. Similarly, the formation of a partially completed photovoltaic cell prior to or after ion implantation can be determined by those skilled in the art, which takes into account the appropriate ion implantation depth in the semiconductor material. It is understood that the donor semiconductor wafer is part of the structure comprising the single crystal donor semiconductor wafer and optionally comprises an epitaxial semiconductor layer deposited on the donor semiconductor wafer. The epitaxial layer (e.g., bonded to the insulator substrate and the layer separated by the donor semiconductor structure) can be formed from a single crystal donor semiconductor wafer material. Alternatively, the epitaxial layer may be formed of an epitaxial semiconductor layer and may also comprise some single crystal donor semiconductor wafer material. The advantages of one or more embodiments of the present invention will be best understood from a review of the detailed description of the <RTIgt; Nonetheless, the main advantages include • photovoltaic structural changes; thinner tantalum films; more uniform tantalum films with higher quality; faster manufacturing yields; improved manufacturing yields; reduced contamination and expansion to large substrates. These advantages will naturally reduce costs. 200814341 When a complex photovoltaic structure is opened to the donor semiconductor wafer and soil via a high temperature process, the photovoltaic structure (pvs) can be varied. The resulting high performance PVS can be transferred to a low cost glass substrate and any patterning required to deposit the remaining layers and complete the wiring. The present invention allows the use of only the desired semiconductor thickness (about 10-30 microns for the case of a stone, and a direct band gap semiconductor such as GaAs for about 3 microns). In contrast to transferring a thicker tantalum film to an insulator substrate and then polishing to remove the damaged surface, it is very thin and thin, and a small amount of material is removed during the process described in the present invention. It allows the thin Shishi film to be transferred directly and then deposited or grown to an extra thickness. A uniform film is highly desirable. Due to the removal of a small amount of material during processing, the thickness of the film is determined by ion implantation. It is shown to be quite uniform in certain embodiments with a standard deviation of 1 nm. In contrast, polishing typically results in a deviation of 5% of the thickness of the film removed. Rapid production capacity is important as demand continues to increase. No, the polishing time for the manufacture of SiOG is about tens of minutes, and the high temperature furnace is required to take off for several hours. For more uniform films, the need for photovoltaic cell polishing or high-temperature furnace annealing will be reduced. Improving manufacturing production is also important for disposal and price reduction. Material waste can be significantly reduced by avoiding wire cut loss. Similarly, expensive donor semiconductor wafers can be polished and used multiple times. By using a film, the material consumption is likewise significantly reduced. If the polishing of the S〇i structure is avoided, the overall manufacturing yield is expected to improve. This improvement is expected to be particularly significant if the polishing process is a low throughput step. Due to the crystalline nature of the film, the processing window is expected to be large on page 13 200814341, and thus the yield is expected to be high. Due to the sensitive nature of SOI, contamination can negatively impact performance, so reducing pollution is highly desirable. In order to avoid the need to use abrasive slurry polishing to reduce the thickness of the layer, it will reduce the possibility of contamination. In addition, avoiding the need for temperature annealing and preventing the spread of contamination, which is required in the long-term thermal annealing treatment. It plays an important role in the scale of photovoltaic devices. The process can expand the amount of money. This expandability may extend the life of the product as the customer's wire size specification increases. Solar cells are usually large to achieve the maximum available space, so the larger the photovoltaic cell becomes, the less photovoltaic cells need to be connected to create a large solar cell. As a comparison, for the size of the processed large wire, the annealing of the wire throwing furnace will increase the difficulty. In particular, the main advantages of the preferred embodiment of the present invention include: i) the use of low-cost swell-matched glass or glass-ceramic substrates at a price comparable to other more expensive semiconductor boards (eg, previously described as a Ge layer and Subsequent GaAs growth) or prior art thermal expansion mismatched ceramic substrates; 2) single crystal Si, Ge layer or read GaAs/Ge on a hetero-substrate, which is used as a template to produce a lattice-dependent very low-defect semiconductor The layer is used as a high-efficiency solar cell, and the substrate is made of a transparent crystal substrate. (3) The transparency of the substrate allows the module to be manufactured with elasticity. Those skilled in the art will be able to clearly understand other items, features and advantages of the present invention with reference to the present invention. [Embodiment] Unless otherwise stated, the numerical values, dimensions, and weight percentages of the physical properties of the materials used in the manufacture of the book and the application of the smear are all expressed by the approximate width. People understand that in the specification and application of the patent model, the number of students has been tried to ensure the correctness of the number revealed by the sample towel. Any measured value can inherently contain a particular error due to the standard deviation produced in the respective measurement technique.

The so-called &quot;Chen fat conductor" material is completely crystalline or substantially crystalline, deliberately or non-intimately or accidentally added to the defect and / or dopant f. Therefore it contains (1) precursor material, semiconductor or non- The semiconductor germanium product material is formed as a semiconductor read material. The crystalline semiconductor material may be a single: germanium or a solar crystal material. Indeed, the semiconductive material usually contains at least some internal or surface defects or deliberately added, for example, a crystalline particle edge. Crystallization on the moonshell also reflects the specific dopant that can distort or affect the crystal structure of the semiconductor material. &quot; : H 4, 5 and 6 (Fig. 4-6), which respectively show the pvs change ugly, face and 100 of the photovoltaic S0I structure according to one embodiment of the present invention. The photovoltaic device S〇1 structure 100 can be represented as a Pv soi structure 100, or PVS W j. These structures can also be exemplified by the structure 1GG. 1 Surname structure 1〇〇 can include *Insulator grade 1〇1 made of glass, Photovoltaic 1Q2(® 4), Ion implantation region 103, Rear side fine layer 1〇4, Hi conductor layer contact, &amp; Form semiconductor layer Employed, and conductive Lang 110 1 (^ destructive 100 has the appropriate use related to photovoltaic knotting device. ',% of the layer 110 is a layer of conductive material as an ohmic contact. Conductive window page 15 200814341 layer is translucent, Or transparent. The exemplary material is an indium tin oxide material, which is usually formed by spraying a reactive smear in an oxidizing atmosphere. The indium tin oxide substitute may include, for example, an oxidized word of doping. Change the zinc oxide of the butterfly, or even the carbon nanotubes. Indium tin oxide GT 〇, or indium oxide substituted for tin) is indium (ΠI) oxide (I·) and tin (^ v) oxide (SnO〇, usually 90% by weight of In2〇s, 10% by weight of sn〇2. Its thin layer is transparent and colorless. In bulk form, it is pale yellow to gray. # Indium tin oxide The main characteristic is the combination of electrical and optical transparency. However, the film deposition process will be compromised, and the high concentration of charge carriers will improve the material. The conductivity is reduced, but the transparency is reduced. Thin film sub-beam evaporation of indium tin oxide, physical vapor deposition, or spray coating is deposited on the surface. Layer 106 and (10) semiconductor material may be substantially single crystal material. Form. The term "substantially" lies in the description of layers 106, 1 〇 8 considering that the semiconductor material usually contains at least some of the stencil defects _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Crystal structure field-form semiconductor layer two = p-form dopant, wherein the p_ form semiconductor layer (10) contains the n_ form. In all cases, the P' form layer (10) is thicker than the formal layer, "most of the requirements The hole pairing is formed in the ?-form layer employment.

For other purposes, it is assumed that the semiconductor layer 1〇6,108 is composed of Shixi, except that people know that the semiconductor material can be a turn-based semiconductor semiconductor-type turn-body, such as ΠΜ, IIMV, etc., and InP, materials. Examples include: Si, SiGe, Sic, Ge, GaAs'GaP Page 16 200814341 The rear side of the lining 104 can be used to decouple the ride, the scale is mainly metal or the layer of metal enamel. The back side contact layer is an ohmic contact, i.e., the area being processed on the semiconductor device, such that the current-voltage α-ν scale of the device is linear and symmetrical. The back roll support can be selected as a thermally stable female touch si. For example, the back side support layer 104 can be aluminum or a telluride, such as a bismuth, and the m case will be finer than the bottom. The combination of debris and polylithic compounds has a younger conductive chick and is superior to the individual town and _ will melt during subsequent processing. The backside contact layer i 〇 4 can be produced by &gt; chiral product such as LED, CVD or PECVD. It is also possible to use the internal extension (MeS0taxy) or the epitaxial method. The epitaxial method is to match the crystal phase to the surface of the filament, and the internal extension method is to grow the crystal phase to match the crystal phase to the sink crystal table. During this process, ions are implanted into the material at a relatively high energy, and the dose is applied to create a layer of the object, and the temperature is controlled to cause the target crystal structure to be destroyed. The crystal orientation of the layer can be machined to match the shoe, and even the exact crystal structure and lattice constant can be different. For example, after nickel ions are implanted into the germanium wafer, a layer of germanium oxide can be grown, wherein the crystals of the stone crystals are aligned with the crystallographic orientation of the stone. The use of an epitaxial or internal extension method to form the backside contact layer 104 is considered to be a conceptual interface between the structural planes of 10 and 6 in the structure 100A of FIG. 4, as long as it is shown in FIGS. 7-9 and the outer ride 122 contains epitaxy or Inner _, forming a back side contact 104, and a semiconductor layer thereon. Since the semiconductor layer can serve as the basis (pvsF) 1 〇 2 of the photovoltaic structure in Fig. 4, the semiconductor layer and the contact layer 1 〇 4 &amp; can be regarded as partially completing the Pvs 124, which are illustrated in Figs. Thus, the epitaxial or internal extension method or ion implantation 200814341 is used to form the partially completed PVS 丨 24 to form the back side 200 Β ^ 2000 - ^ ##^ before the anodic bonding (step 2 〇 8). After the extension process (step) of the subsequent process 200A, the PVSF 102 is transferred using epitaxial or internal extension or ion implantation and the back side contact layer 1〇4 is formed. Similarly, the back side contact layer 104 can be borrowed after the epitaxial separation. Formed by heavily doped PVSF 102. This heavy doping is usually carried out by ion implantation. In addition, if the backside contact layer 1〇4 is deposited on the PVSF 102 structure after epitaxial separation (step 21A), a change in PVS 1〇〇 will occur. The change can be made as described before or after the PVSF 102 internal extension method. When the p-form semiconductor and the back side contact layer 104 are formed by the internal extension method, a PVS 100 similar to the change 100A or 100B is produced. If the inner extension depth of the back side contact layer 1〇4 is in the middle of the PVSF 102, the -layer PVSF 102 may remain under the back side fine layer 104, such as the varying structure 100A. If the depth of the back side contact layer 1〇4 reaches the bonding surface 126 of the PVSF 102, a small amount or no pvsf 1〇2 layer remains under the back side contact layer 1〇4, as in the case of varying structures. Since the conductive layer is formed on or in the outer layer 122, whether formed by epitaxy, internal extension, ion implantation, doping, vapor phase transport, vapor deposition or the like, the conductive layer is integrally formed with the outer layer 126. If the conductive layer is formed on or in the external contact before the external member 122 is bonded to the insulating filament 101, the conductive layer is adjacent to the insulator substrate 1〇1 when the outer county 122 is bonded to the substrate 101. In other words, the conductive layer will form close to the outer riding edge, and the conductive layer formed by the epitaxial layer facing the insulator shank is between the insulator wire and the outer county. If the epitaxial layer 122 is first bonded to the insulator filament 1〇1 and the conductive layer is formed on or in the epitaxial layer, the conductive layer is on or near the side of the layer 122 of the 200814341 layer 122 and thus away from the insulator The insulator substrate 1 is similarly formed on the epitaxial layer, or above or above the epitaxial layer, the photovoltaic device layer will be away from the insulator substrate 101 after the epitaxial layer 122 has been bonded to the insulator substrate 1〇1. Referring to FIGS. 15-17 in more detail, the ion implantation region 103 is formed on either side of the insulator substrate 101 and the anodic bonding between the layers of the insulator substrate 101; the layer is the PVS substrate 102 in the variation structure 100A, In the variation structure 100B, it is the back side contact layer 1〇4; or in the variation structure 100A, it is the conductive window 11〇. The ion implantation region 103 is not present in the prior art photovoltaic structure. 0. In contrast to the variation structures 100B and 100C of Figs. 5 and 6, the variation structure 100A of Fig. 4 includes a PV structure foundation 102. When the epitaxial layer 122 is in the absence of any outer layer, transfer to the insulator substrate 101 to produce a partially completed pVS 124 (PCOVS) will result in a photovoltaic structure basis 1〇2. Basically, the epitaxial layer 122 can be regarded as becoming PVSF 102 by being bonded to the insulator substrate 101. Therefore, the PVSF_102 can be composed of a single crystal semiconductor layer, which is produced by the wafer 120 shown in FIGS. 7 and 1B. . The insulator substrate 101 of the present glass substrate can be formed of oxide glass or oxide glass ceramic. Although not required, the embodiments described herein may comprise oxide glass or glass Tauman with strain points exhibiting less than 10001. For example, in the traditional glass manufacturing industry, the strain point temperature is the temperature at which the glass or glass ceramics has a viscosity coefficient of 10,146 poise (10 ia6 Pa·s). Since glass has a relatively simple manufacturing advantage between oxide glass or oxide glass ceramics, glass is more widely used and cheaper. Page 19 200814341 For example, the glass substrate 101 may be formed of a glass substrate containing alkaline earth metal ions, for example, a substrate formed by our company's glass styling 1737 and Eagle 2000. Some glass materials have other uses, such as, for example, the manufacture of liquid crystal displays. The thickness of the glass substrate is in the range of 〇·1 mm to 10, for example, in the range of 〇·5 faces to 3 咖. For some SOI structures, the thickness is greater than or equal to μm (for example, an insulating layer of 〇 001 00 or 100 Ω is required to prevent parasitic capacitance effects' ¥ Standard SOI structure with Si/SiCfe/Si construction operating at high frequencies This effect will be produced. It has been difficult to achieve this thickness in the past. According to the present invention, an SOI structure having an insulating layer thickness of more than 1 μm can be achieved immediately by simply using a glass substrate 1〇1 having a thickness greater than or exclusively for 1 μm. The lower limit is about 1 micron, that is, 100om. The thickness of the glass substrate 101 should be sufficient to support the semiconductor layer 106, 108 整个 in the entire bonding process step and in the subsequent processing of the photovoltaic SiOG structure 100, although the thickness of the glass substrate is 1〇1 and Without the theoretical upper limit, it is not beneficial to exceed the thickness of the support function or the thickness required for the final photovoltaic Si〇G structure, because the larger the thickness of the filament 1()1, the more difficult it is to form in the formation of the photovoltaic SiOG structure. At least some of the processing steps. Oxide glass or oxide glass ceramics 1〇1 may be dominated by Shi Xishi. Thus, in oxide glass or oxide The percentage of Si&amp; molars in glass ceramics can be greater than 30% molar ratio and can be greater than the general molar ratio. In the case of glass ceramics, the crystalline phase can be mullite, cordierite, stone, spinel or other well known in the industry. Glass-ceramic crystalline phase. Non-stone-stone-based glass or glass can be used to practice one or more embodiments of the invention, but is generally less beneficial, page 20, 200814341 because of its higher price and/or Poor performance characteristics. - For two applications, such as SOI structures using non-mercite-based semiconductor materials, non-oxide based glass substrates such as non-oxide glass are required, but are generally not beneficial because of their The price is higher. As explained in more detail below, in one or more embodiments, the glass or glass ceramic substrate 101 is designed to thermally expand with one or more layers (mainly 1〇2, 1〇4, 106, 108 or 110, etc.) semiconductor material. The coefficients are matched (eg, Si, Ge, etc.) and the layer is bonded directly or indirectly to the substrate. The coefficients of thermal expansion match to ensure the mechanical properties required during the heating cycle of the deposition process. For photovoltaic applications, glass or glass-ceramic 101 is transparent in the visible, near-ultraviolet, and/or infrared wavelength range, such as glass or glass. Ceramic 101 is transparent in the 35 〇 nm to 2 μm wavelength range. It is important to have a transparent or at least translucent glass in the 100CL structure, where the light enters the insulator ship 1〇1 before reaching the rest of the PV structure. However, in the ugly surface of the change structure, the light does not enter the insulator 10 101, and thus it is irrelevant whether or not the insulator Wei 1〇1 is transparent. In this case, the selection of the insulator substrate 101 is determined according to other standards, in particular, depending on the price. ... Although the glass New 101 can be composed of a single glass or glass ceramic layer, a laminated structure can be used if necessary. When the laminate structure is the most, the laminate to which it is bonded (for example, with 104 or 110) has the characteristics of a glass substrate composed of glass or glass ceramics as described herein. The layers of the layer also have these characteristics, but may have a more moderate nature because they do not directly interact with the bonding layer. In the latter case, when the glass-based 200814341 plate 101 no longer satisfies certain characteristics, the glass substrate is considered to be unusable. Referring to Figures 7, 8 and 9, it is shown that a processing step is performed to fabricate a PV structure in accordance with one or more embodiments of the present invention. The process 2〇 is shown in the figure, the process lotus is shown in Figure 8, and the process 2GGC_ is shown in Figure 9. The respective roles (steps) in these module diagrams have the following meanings: 202: processing the surface of the donor semiconductor wafer; 203) applying the donor semiconductor wafer to the ion implantation process; 204: applying the donor semiconductor wafer Moderate oxidation; , 205: Partially completed photovoltaic structure; 206: Partially completed Pvs and donor wafers are ion implanted

207: partially completing the photovoltaic knotting and moderate oxidation; 208: forming an anodic bond between the photovoltaic structure (or partially completing photovoltaic) and the glass; 210: separating the glass layer from the donor semiconductor wafer/ PVSF/epitaxial layer; and 212. The trim semiconductor wafer and/or the pw base are subjected to a trimming process. Figures 10-18 show the intermediate and near-final structure that can be implemented in Figures 7'8 &amp; In Figure 10, the arrow shows the surface treatment =. In Figure 11, the arrows represent ion currents (e.g., hydrogen ions) implanted in a general orientation in accordance with one or more embodiments of the present invention. In Fig. 12, arrows are in accordance with a particular embodiment of the present invention in which the epitaxial layer is subjected to a trimming step &amp; electrical destruction or other material or operation and its general orientation. In Fig. 13, there is shown the formation of a backside contact layer and/or conductive material and/or operation, and a general deposition direction in a particular embodiment of the invention. In Figure 14, the arrow on page 22, 200814341 is doped with individual layer materials (such as dopants) and / or operation (replacement process), - from + and its: rn body free life. '... In step 202 of FIG. 7-10, the donor semiconductor wafer 12 is processed by polishing, cleaning, etc. to produce a relatively flat and uniform processing of the sample surface 121 suitable for use as a paste. Connected to pvs. The treated body surface 121 will form the PV structure base 1〇2 or the bottom side of the semiconductor layers 1〇6, 1〇8. For illustrative purposes, the semiconductor wafer 12 can be replaced with a (n-form or φ-form) single crystal germanium wafer, although any suitable semiconductor and body materials described above can be employed. The step 203 of the process 200A and 200B or the step of the process 2〇〇C step 206 is also shown in FIG. 11, and the epitaxial layer 122 is formed by implanting ions into the surface 121, ie, the processed donor surface 121 or any The treated layer on the body surface 12 is subjected to one or more ion implantation processes to create a weakened region beneath the treated donor surface 121 of the donor semiconductor wafer 120. Although embodiments of the present invention are not limited to any particular method of forming epitaxial layer 122, a suitable method requires that donor body surface 121 of donor semiconductor wafer 120 be subjected to a hydrogen ion implantation process to at least initiate An epitaxial layer 122 is created in the donor semiconductor wafer 120. The implant energy is adjusted using conventional techniques force π to achieve an appropriate thickness of the outer layer 122. For example, hydrogen ion implantation may be employed, although other ions or multiple ions thereof may be employed, such as boron + hydrogen, helium + hydrogen, or other ions known in the art. Any other technique known or suitable for forming epitaxial layer 122 may be employed without departing from the spirit and scope of the invention. Depending on the parameters of the PV SOI structure 100, the thickness and number of the upper layer of the 200814341 portion of the top surface of the processing body surface 121, and any intermediate processing steps possible such as CMP or FA, the appearance | - 22 can be manufactured as needed And 7 or I lack thickness. Further, as various design constraints require that the epitaxial layer 122 be thicker than desired, such as for use in microelectronics, a known method of mass removal, such as CMp or evacuation, may be used to reduce the layer 122 after epitaxy in step 210. thickness. However, using the mass 1 removal step will increase the overall manufacturing process time and expense.

And not necessary for pvs 1〇〇. For example, in the variation structure 1A, the PVSF φ 1 〇 2 layer does not need to be thin or thick, and the PVSF 102 is thick enough to be a follow-up surface, but as thin as possible to save material and thus reduce cost. ‘The opposite situation is more likely to occur in the PV structure 100, ie the epitaxial layer is too thin. A thick Si layer in varying structural planes and l〇〇c is desirable for pvs 1〇〇 because a thick Si layer will absorb more light and increase its efficiency. The energy required to produce the desired thickness of the epitaxial layer needs to exceed the parameters of the available device, and thus the deposition or epitaxial growth after the epitaxial layer 122 is formed. Additional Si is added before or after the epitaxial layer is transferred to the glass substrate IQ! &amp; can be added to the outer ride 122. If it is increased before, the addition of Si becomes part of the generation of 70%, but afterwards, the addition of Si becomes part of the finishing process. Likewise, the semiconductor layer is added to the PVS 100A after the PVSF 102 and the backside contact layer 1〇4 are on the substrate 101. At step 206 of process 2A and 200B or step 206 of process 2〇〇c, which is also shown in FIG. 11, ion implantation surface 121 is the treated body surface 121, and is formed in the treatment Any layer on the body surface 121 or on the donor semiconductor wafer can be treated to reduce, for example, the hydrogen ion concentration on the ion implantation surface 121i page 24 200814341. For example, the face wafer 丨 and the cleaning: the TO_122 ball joint surface is applied. Moderate oxidation can be included in the treatment of oxygen electropolymerization, odor, oxygen treatment, use of nitrogen peroxide, hydrogen peroxide and ammonia, hydrogen peroxide and acid treatment or a combination of these treatments. During the pre-age treatment, the terminal hydrogen surface is deuterated to a hydroxyl group, and 126 mcL of oxygen plasma can be carried out at a room temperature of 25_15 at a busy temperature.

Reason. Steps 2 and 5 of FIGS. 8 and 9 and also showing FIGS. 13 and 14 include: completing PVS 124 on the donor semiconductor crystal. The partially completed pvs 120 may be formed after the generation of the external processing 122 in the process 200B or before the generation of the external process 122 in the process 200C. After the outer ride 122 and the partial finish = PVS 124 are both generated, the portion of the finished portion 124 is actually formed. Part of the completed PVS modification of the exposed surface will be the bonding surface 126 to adhere to the glass insulator in step 2〇8. Referring to Figures 13 and 14, the donor semiconductor wafer 12 can be processed to produce a portion of 124. Figure 13_14 shows that further external contacts 122 are formed on the body surface 121 of the donor semiconductor ^20 processed domain when the step of generating portions is performed. There are many different steps in the process of generating a partial completion. For example, the partial finish rn m is included as shown by the paste 13 she said that the face towel is increased _ (10), or the conductive window layer 11 增加 is added in the change structure, or the intermediate doping step is used in FIG. . Figure 13 illustrates the addition of a conductive self-layer Π0 in a contact structure 1〇4 or in a varying structure jump in accordance with the present invention, or in a plurality of embodiments. The degree is similar to the high degree of research and development. Although the simplification of the deposition process is, for example, (10) or PECVD, the drawings are meant to represent any possible processing of the epitaxial and internal extensions as described above. Preferably, the back side fine or conductive window layer no is deposited separately on the PVS 124 instead of the direct-aged glass substrate, as long as the anodic bonding process in the series process towel step 2〇8 is good. . The advantage of depositing this layer on the partially completed PVS 124 while bonding to the donor-body wafer 120 will alleviate the limitations of the processing required to deposit these layers directly onto the glass filament 101, which is recorded for extreme conditions. • Figure 14 shows the deposition of epitaxial layer 122 ion implantation surface 121 i, resulting in

Surface η p junction 128. Depending on whether a change in structure 1 or i〇〇c is desired, the semiconductor layers 106, 108 may be fabricated from doped Si blocks that are subjected to opposing dopants on their surface. In a variant structure, an exemplary embodiment, the n-type doped donor semiconductor layer 120 can be p-type dopant mixed with its eccentric surface, thereby creating a subsurface n-p junction. Conversely, in the variant structure (10)C, the p-form doped donor semiconductor wafer 120 can be doped on its surface using an η-form dopant, thus creating an η-ρ junction. In steps 208 of Figures 7-9 and 15, the glass substrate 101 can be bonded to the epitaxial layer 122/PVSF 102/portion of the bonding surface 126 of the PVS 124. A suitable bonding process is described in U.S. Patent Application Publication No. 2004/0229444, the disclosure of which is incorporated herein by reference. Some of this process is known as 11⁄4 pole bonding, electrolysis, bonding by electrolysis, and/or anodic bonding by electrolysis to illustrate the bottom. During the anodic bonding/electrolysis process, the glass substrate 101 (and the bonding surface 126/epitaxial layer 122, if not completed) can be used to cure the surface of the stalk. Thus the intermediate structure causes a true or indirect contact to achieve the arrangement shown schematically in Figures 15-16. The structure formed by the donor semiconductor wafer 120, the epitaxial layer 122 / PVSF 102 / portion of the PVS 124 , and the glass substrate 101 is heated at different temperature gradients before or after the contact. The glass substrate 101 can be heated to a higher temperature and is souther than the donor semiconductor wafer 120 and the epitaxial layer; [22/PVSF 102/ partially completes the PVS 124. For example, the temperature difference between the glass substrate and the donor semiconductor wafer 120 (and the epitaxial layer 122/PVSF 102/partially completed pvs 124) is at least 1 ° C, although the difference can be as high as l 〇〇 ° c to i 5 〇 ° c. The temperature difference is desirable for a glass having a coefficient of thermal expansion that matches the donor semiconductor wafer 120 (matching the thermal expansion coefficient) because it will facilitate subsequent separation of the subsequent outer layer 122 from the semiconductor wafer 120. Due to thermal stress. The temperature of the glass substrate 101 and the donor semiconductor wafer 120 can be within 150 ° C of the strain point of the glass substrate 101. Once the temperature difference between the glass substrate 101 and the donor semiconductor wafer 120 is stable, the applied force σ is mechanically stressed to the intermediate assembly. The pressure is in the range of 1 to 5 〇 pSi. The appropriate pressure can be determined by manufacturing parameters such as the materials used and their thickness. Next, a voltage is applied to both ends of the intermediate member, for example, the donor semiconductor wafer 120 is a positive electrode and the glass substrate 101 is a negative electrode. The application of a voltage causes the alkali metal or alkaline earth metal ions in the glass plate 101 to move away from the semiconductor/glass interface and further into the glass substrate 101. This accomplishes two functions: (i) creating an interface free of alkali metal or alkaline earth metal ions; and (iii) glass substrate page 27, 200814341 101 becoming reactive and fine mailing to the donor semiconductor wafer 12〇 Private... ' ~ * j&quot;-~*--· — — — —»-TM-—. .~-,'·__ 1 丄 _ - Where, &quot; and 15 steps, the intermediate components remain in the above After the condition of the lower segment (for example, about hours or less), the voltage is removed and the intermediate component is cooled to room temperature. Then, the semiconductor wafer 120 and the glass substrate 101 are separated, and if they have not become completely independent, they may include some peeling to obtain the glass grade 101 having a relatively thin outer seal 122/PVSF 102/partially completed PVS 124, which is bonded by A semiconductor material of the donor semiconductor layer 12Q is formed thereon. Separation can be achieved by thermal stress causing the split ion implantation region. Mechanical stresses such as water column or laser cutting, or chemical chemistry can be varied or added to make separation easier. Referring to Figure 16, the ion implantation region 103 referred to in Figures 4-6 will show in more detail that the detailed portion of the ruthenium structure particularly belongs to the anodic adhesion region at the interface between the glass substrate 〇1 and the adjacent layer. 4 is a PVSF 102 of epitaxial layer 122, in FIG. 5 a back side contact layer 1〇4, or in FIG. 6 a conductive window layer 110. The bonding process (step) transfers the interface between the epitaxial layer 122 and the glass substrate to the interface region 3〇〇. The interface area 3 〇〇 preferentially includes a mixed area 160 and a depleted area 230. The interface region 3 〇〇 preferentially includes one or more positive ion accumulation regions near the distal edge of the depletion region. The mixing zone 160 is a thickness T160 that raises the oxygen concentration zone. When the conductive window layer 110B is bonded, the mixed region 16〇 is depleted of oxygen by the starting component stoichiometry to promote oxygen transfer from the glass substrate. The thickness can be defined by the epitaxial layer 122/PVSF 102/partially completing the oxygen reference concentration at interface 170 within PVS 124. The reference surface 170 is substantially parallel to the glass substrate 1〇1 and the epitaxial surface of the layer 122/PVSF 102/part of the PVS 124 and the separation distance from the surface is DSI. The thickness of the reference surface mixing region 郷- is used. T160 generally satisfies the following relationship: T160 0 0 nm, where T16 〇 is the viscosity = the distance between the surface 126 and the surface, the surface is: (i) substantially parallel to the bonding surface 126, And (ii) is the surface farthest from the bonding surface, which satisfies the following relationship: C0(x)-C0/REF fiber, which is measured, wherein (1) (1) is a gas C0 whose oxygen concentration is the distance X from the bonding surface 126. /Ref is the oxygen concentration above the reference plane φ, and C000 and C0/Ref are atomic percentages. Typically, T160 is substantially less than ηιη, for example about 50 to 1 〇〇. It is known that CO/Ref is usually zero, so the above relationship is simplified in most cases: CO(x)^50%, 〇Sx$T160. In connection with the depletion 230, the oxide glass or oxide glass ceramic substrate 101 preferentially contains at least some positive ions that move in the direction of the applied electric field, i.e., the far-hybrid surface 126 and the incoming filaments. Metal ions such as Li+1, Na+1, and/or Κ41 ions are suitable positive ions for this purpose, because they usually have higher mobility rates than those contained in oxide glass or oxide, glass The type of positive ions is, for example, a soil metal ion. However, the oxide glass or the oxide glass ceramic is different from the alkali metal ion material, and the oxygen-removing glass has only an alkaline earth metal ion, which can be used in the practice of the present invention. Alkali and Alkaline Earth Metal ion concentrations in the syllabary _ change, the dynasty concentration to oxidize «the benchmark between 0.1 and 鄕 weight ratio. The preferred ion concentration is based on the oxide, and the alkali metal ion is in the range of ! to (10) by weight, and the soil metal ion is in the range of 2 to 25% by weight. 〇 29th 200814341 Applying an electric field to the positive electrode (cation) in the bonding step (step 208) further enters the glass substrate 101 to form a depletion region 23〇. When the oxide glass or oxide glass ceramic contains an alkali metal ion, the formation of a depletion region 23 is particularly desirable because the ion is known to interfere with the operation of the semiconductor device. Alkaline earth metal ions such as Mg+2, Ca+2, Sr+2, and/or Ba+2 also interfere with the operation of the semiconductor device and thus the depleted regions also preferentially have these ions at reduced concentrations. It has been found that once the depleted region 230 is formed to be stable for a long period of time, even the PV structure is heated to a high temperature, as compared to or even somewhat higher than the temperature used in the bonding process. Formed at high temperatures, the depleted regions are particularly stable at pv structure operation and formation temperatures. These considerations ensure that the frit ceramic ions do not diffuse back into the semiconductor material 1/4 by the oxide glass or oxide glass ceramic during use or further processing of the device, which is the use of an electric field for partial processing. Important advantages. The operational parameters required to achieve the required width by the selection of operational parameters to achieve a strong adhesion and to reduce the positive ion concentration of all positive ions of interest can be immediately determined by those skilled in the art. When present, the depletion 11 domain is characterized by the fabrication of a PV structure in accordance with one or more embodiments of the present invention. As shown in Figure 17, after separation, the resulting structure can comprise a glass filament and an epitaxial layer 122 of semiconductor material bonded thereto. After epitaxy, the split surface 123 of the SOI structure exhibits an excessive surface _ (shown in Figure 17), excessive ruthenium thickness (possibly as a microelectronic application), and ruthenium formation damage (eg due to hydrogen ions) Causes and formation of amorphous page 30, 200814341 矽 layer). In step S2 of S圏f § and </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; Multiple times of processing. For example, the trimming process 130 can include a non-scribe step that is required to produce m different structural faces and a surface height of 100C. This scribing step, which is well known to the industry, can be done after the other trimming process, or at the same time. Another trimming process 130 can include expanding the semiconductor thickness of the epitaxial layer 122. In the case of varying structural planes, the semiconductor material can increase before the internal growth. The thickness of the termination of the semiconductor layer 1 and (10) should be greater than, for example, 1 〇 micrometer (ie, 1 café) and less than 30 micrometers. Thus, the appropriate thickness should be generated in addition to the county 122 and the increase in the thickness of the outer semiconductor layer 132 (e.g., Si) continues to achieve the desired thickness. The additional semiconductor layer 132 (e.g., Si) can also be modified to include inclusions. The thickness of the stone layer is about 50-150, and it depends on the planting, energy input and implantation time. The outer _(2) thickness is about 500. As the electronic SOI bond, the thinner outer layer _122 can be formed as a thinner amorphous austenite layer and must be thinner, adding more semiconductor materials and materials during the trimming process. At the same time, in accordance with step 212, the splitting surface 123 can be subjected to a subsequent splitting process which can include applying a splitting surface 123 to a polishing or annealing process to reduce the texture 123A. In addition to this, in order to achieve an exemplary embodiment of varying structural planes, the trimming process may include coating a conductive window layer u_ such as a deposited indium tin 200814341 oxide. Conversely, in order to achieve an exemplary embodiment of the varying structure 100C, the trimming process may include a coated back side contact layer 104 deposited by LPE, CVD or PECVD, a conductive metal-based or metal oxide-based layer, For example, an aluminum-based film. As previously explained, the backside contact layer 1〇4 is also formed by, for example, epitaxial or epitaxial growth of the nickel-plated nickel. Partial completion of PVS 124 is expected to have more characteristics of the final product to some extent, and a few finishing processes are necessary. By comparison, formed separately? φ 102 is incapable of distinguishing between the substrate 101-PVSF 102 on the insulator substrate 101 as a "photovoltaic structure" and superior to any other semiconductor on the insulator structure of the US Patent No. 2004/0229444, several PVS - specific trimming process is ' Required. However, during the continuation of the trimming process, the single crystal layer as the base of the voltaic structure 102 will relax some parameters within which the operation and expansion options will be selected and within the range of selected results. Completion of pvs 124 allows for greater flexibility to form progressively multi-junction pvs devices. For example, the construction of SiSF's PVSF 1〇2, the manufacturer is able to develop Si crystal pairs of different specific heat capacities such as ^ Ge, and GaIn 2 to produce a plurality of layers of GaAs, Ge, and Galnh. The selective cell is as shown in the preferred embodiment of FIG. 21, and the PVSF 1〇2 may include

Ge, or GaAs, or PCPVS 124 may comprise a doped Ge/GaAs layer. Other top views of the present invention are described in detail below for the previously mentioned Si〇G process. For example, separating the epitaxial layer 122 from the donor semiconductor crystal #12() results in a first split surface of the donor semiconductor wafer 12 and a second split surface of the outer contact 122. As previously explained, the trimming process 130 can be flipped over the second splitting surface 123 of the outer 126. In addition, the trimming process on page 32 of 200814341 can be applied to the first splitting surface of the donor semiconductor wafer i2, or the like, for example, the dragging light ______________ in the present invention In another embodiment, the donor semiconductor wafer 12A can be a partial wound &amp; body structure comprising a substantially single crystal donor semiconductor wafer 12, the outer semiconductor layer being disposed on the donor semiconductor wafer 120. (Extension of the semiconductor layer in the SOi. For a detailed description of the semiconductor layer, refer to the patent application No. 11/159889, filed on Jun. 23, 2005). Thus, the epitaxial layer 122 can be formed of an outer semiconductor layer (and can also comprise a single crystal donor semiconductor material from the wafer 120). Thus, the previously mentioned trimming process can be applied to the splitting surface 123 of the epitaxial layer 122, which is formed from an epitaxial semiconductor material and/or an epitaxial semiconductor material in combination with a single crystal semiconductor material. The photovoltaic cell generation process of one or more embodiments of the present invention can be automated in the 'ie photovoltaic system. The system can include a PM operation component that operates the PV structure as a process, and a photovoltaic process. The photovoltaic processing assembly comprises various subsystems, such as conditioning or trimming systems for manufacturing the pv_substrate 100, and transfer or bonding systems, which are operated by the PV semiconductor in an insulator operating component. - For example, when conditioning epitaxial Layer 122 B, which includes PVSF 102 or partially completed PV structure 124, the operational components are capable of transporting and positioning the pv structure 1 完成 required to complete the pvs process to allow anodic bonding to occur. Further positioning the substrate 1〇1, Bonding to PVSF 102 or Partially Composing PVS 124 In a PVS processing assembly, extension and finishing steps 210 and 212 can be separately referenced to FIG. 19, which shows a first embodiment in accordance with one or more embodiments of the present invention. Page 33 200814341 PVS 100D simplifies the multi-join variation structure i〇〇D. Multi-join PVS 100D is similar to the fVS of the diagram; but with some differences, such as glass-based 4 〇i • Replaces the crystalline Ge wafer substrate with an epitaxial crystalline Ge film on top of the glass substrate. The thickness is 500 μm and the resistance is 〇·〇1—〇·〇4 ohm cm p-form Ge or GaAs wafer can use 100KeV and dose Implanted with 8xl016 hydrogen ions. The wafer is then chemically cleaned and subjected to oxygen plasma treatment to oxidize the surface groups. After cleaning, the GaAs wafer can be inserted into the deposition bath and coated with a doped or undoped Ge film. The thickness is determined by the design of the device. Ge deposition on GaAs wafers can be achieved in different ways, including plasma lift chemical vapor deposition, ion beam assisted spray deposition, evaporation or chemical vapor deposition epitaxy. The p-form) Ge layer can be achieved by using As or P. The thermal expansion of the metal silicate silicate glass wafer is matched with Ge and the thickness of the coffee can be cleaned by standard cleaning techniques such as using detergent and distilled water followed by dilute acid. Cleaning is performed. Two wafers are brought into contact and placed in the bonding system. A voltage of 1000 V is applied to both ends of the wafer for 2 minutes, and the temperature of the glass and the germanium wafer are divided. At 450 ° C and 400 ° C, the voltage is then cooled and removed. The multilayer GaAs/Ge or Ge film bonded to the glass can be separated by the mother wafer, which can achieve very strong adhesion to the glass. Thus, in Figure 19, The reference number represents the following meaning: 104 doped Ge film as backside contact layer; 1〇5 GaAs tunneling junction; 106邛-form 0^3; 108 11-form 0-3 or 〇3111?; 107 4168 八3 Tunneling interface; 110 conductive window layer. The glass wafer with Ge or GaAs/Ge film is then selectively polished, annealed or recovered to remove the damaged Ge or GaAS top layer and the surface of the good quality layer. The wafer can be used as a substrate to grow an epitaxial structure to form a solar cell of page 34 200814341. Examples of materials include GaAs, GalnP/GaAs, GaJnyP/Gac, materials well known in the art. Various processes can be used to deposit epitaxial films, including CVST (closed space vapor transport) M0CVD (organometallic chemical vapor deposition), germanium (molecular beam epitaxy), and other methods known in the art. A wide area of the passivation window layer such as A1GaAs, InGap or ZnSe can be used as well as other encapsulation or purification layers and surface treatments can be used to complete the cell. • Ohmic contacts can be used in different configurations depending on the device design, but the main specification is that the current will be generated from one contact to the next to complete the line. Once the line is completed, the two electrode leads of the device will be connected. To negative - load, as shown in Figure 6. For example, the backside contact 104 can rest on the top of the semiconductor layer 〇6 rather than underneath, provided that proper separation will result in proper line and current construction. Although the invention has been described with respect to specific embodiments, it is understood that these embodiments are only As a principle and application of the invention. It is to be understood that the various embodiments of the present invention can be varied and designed in other ways without departing from the spirit and scope of the invention as defined by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to enumerate the various elements in the present invention, the same numerals represent the same elements, and the drawings show the form of the preferred simplification, and it is understood that the present invention will not be read and combined by the reading. The invention is only subject to the proposed transfer. The sheds are mixed with each other, and the components are not proportional to each other. The first, second and third figures are module diagrams showing the single page of the 200814341 junction, the double junction, and the two junction photovoltaic knots. And a sixth diagram is a block diagram showing photovoltaics in accordance with one or more embodiments of the present invention, respectively. Seventh, eighth and ninth are flow diagrams for fabricating a photovoltaic structure in accordance with one or more embodiments of the present invention. Tenth through eighteenth are flow diagrams showing the formation of an intermediate and near-final photovoltaic structure using a process in accordance with one or more embodiments of the present invention. The nineteenth diagram shows the use of a simplified multi-junction photovoltaic structure in accordance with one or more embodiments of the present invention. Description of the numerical symbols of the components of the drawings:

Ge substrate A101; 1.4eV GaAs battery Α103/105; gate contact A107; Ge substrate A201; 1.4eV GaAs battery A203; AlGaLnP or AlGaAs pass-through surface A2〇7; L9eV InGaP battery A209/211; gate contact A213; 0· 7eV Ge battery and substrate A301; GaAs pass-through surface A305; 1· 4eV GaAs battery A307/309; tunneling junction A311; 1. 9eV InGaP battery A313/315; gate contact A317; photovoltaic SOI structure 100 PVS variation l〇〇A, l〇〇B, l〇〇C; insulator substrate 101; photovoltaic structure base 102; ion implantation region 1〇3; back contact layer 104; GaAs tunnel junction 105; - Form semiconductor layer 101; AlGaAs tunnel junction 107; n-form semiconductor layer 108; conductive window layer 110; donor wafer 120; treated donor surface 121; ion implantation surface i21i; epitaxial layer 122; 123; surface roughness 123A; partially completed PVS 124; bonding surface 126; subsurface η-p junction 128; depletion region 130; semiconductor layer 132; mixed region page 36 200814341 160; interface ι7 〇; 2〇〇A 2〇〇b, 2〇〇c; treating the surface of the donor semiconductor wafer _ 2〇2; applying the donor semiconductor wafer to the ion implantation treatment = 203; The conductor wafer is subjected to a moderate oxidation shame to produce a partial structure 2〇5; the part of the completed pvs and the donor wafer is applied to the process 2〇6; the partially completed photovoltaic knotted lion is moderately oxidized 207; Forming (or partially completing photovoltaic) forming an anodic bond between the base and the glass; separating the glass layer from the donor semiconductor wafer / • PVSF/epitaxial layer 21Q; applying the body-transferred wafer and/or PVS foundation – Entire treatment 212; depletion area 23G; interface area outline.

Page 37

Claims (1)

200814341 X. Patent application scope: 1· rr kind of volt-red device, which contains ·'................ * ' ^ V**-1 .. . · ' ♦ insulator structure; epitaxial layer; conductive layer and the epitaxial layer are formed integrally and adjacent to the insulator structure; and connection, bonding the insulator structure to the conductive layer and the epitaxial layer, wherein the epitaxial layer is a single crystal semiconductor wafer The crystal epitaxial layer is composed of. 2. The photovoltaic device according to the scope of the patent application, wherein the epitaxial layer is mainly a single crystal material selected from the group consisting of Si, Ge-doped Si (SiGe), Sic, Ge, Ga^, &amp; P, and InP. Out. 3. The photovoltaic device according to claim 1 or 2, wherein the connection is made by bonding the insulator structure to the conductive layer and the epitaxial layer is the interface region. 4. The photovoltaic device according to item 3 of the patent application scope, wherein the interface region comprises a mixed region and a depleted region. 5. The photovoltaic device of any of the preceding claims, further comprising: a first ion implantation region in the insulator; and a first ion implantation region spanning the conductive layer and the epitaxial layer. 6. A photovoltaic device according to any of the preceding claims, wherein the conductive layer is made of a metal-based material or a metal oxide-based material. 7. A photovoltaic device according to any of the preceding claims, wherein the epitaxial layer is comprised of a doped semiconductor layer and the conductive layer is comprised of a backside contact layer or a conductive window layer. Page 38 200814341 8. The photovoltaic device according to claim 7 of the patent application, wherein the doped semiconductor wide semiconductor layer, the ρ_form semiconductor layer, or the true: semiconductor junction having a p-type and a Ρ-form doped region Floor. 9. The photovoltaic device according to claim 7, wherein the back contact layer is composed of Al, Ti, M, W, In, Mo, Au, Pt, Pd, Ga, Sn, Sb, Ag, Ge or Telluride. And the conductive window layer is composed of tin-doped indium oxide, doped with zinc oxide of Ilu, doped with zinc oxide or carbon nanotubes. The photovoltaic device according to any one of the preceding claims, further comprising a plurality of photovoltaic device layers formed in or on the epitaxial layer and away from the 〇11. The photovoltaic device, wherein the plurality of photovoltaic devices comprises at least one semiconductor layer, at least one conductive layer, and at least one passivation layer. 12. A photovoltaic device according to claim 10, wherein the plurality of photovoltaic devices comprises an epitaxially grown crystalline layer. 13. The photovoltaic device according to claim 1 of the patent application, further comprising at least one layer of the increased photovoltaic device layer integrally formed with the epitaxial layer and adjacent to the insulator level. The photovoltaic device according to any one of the preceding claims, comprising: an insulator structure; an epitaxial layer adjacent to the insulator structure; an anodic bonding, a bonded insulator structure and an epitaxial layer; and page 39, 200814341 and in object I -. . which is based on the single crystal of the single crystal donor semiconductor wafer = the photovoltaic shock according to the scope of the patent application of the 14th item is further inserted into the step - ion implantation region in the insulator; the second ion implant The input area is in the epitaxial layer. 16. Photovoltaic bonding according to item 1 or item 15 of the patent application area is determined by the interface area. : The person according to the patent application scope (4) of the photovoltaic device, wherein the interface area contains mixed _ and ambiguous areas. 18. Photovoltaic according to any one of claims 1 to 17, wherein the plurality of photovoltaic layers comprise a semiconductor layer and a conductive layer. 19. The photovoltaic device according to claim 18, wherein the photovoltaic device layer comprises at least one or more semiconductor layers, at least one multilayer conductive layer, and at least one purification layer. ^ 20. The photovoltaic device according to claim 18, wherein the conductive layer comprises a metal-based material or a metal oxide-based material. The photovoltaic device according to claim 14, wherein the multi-layer photovoltaic device layer comprises a doped semiconductor layer, a back side contact layer and a germanium window layer. The invention relates to a photovoltaic device according to claim 21, wherein the semiconductor layer to be mixed comprises an n-type semiconductor layer, a P-type semiconductor layer, or a semiconductor having n-doped and P-type doped regions. Conjoining layer. Page 40 200814341 23· Photovoltaic device according to claim 21, wherein Φ ΑΓ, T1, Ni, W, In, Mo, Au, Pt, Pd, Ga, Sn; Sb Ag, Ge or ### The conductive window layer is composed of tin-doped indium oxide, doped aluminum oxidized, or pulverized zinc oxide or carbon nanotube. 24. Photovoltaic clothing according to claim 21 of the patent application, wherein at least one of the plurality of photovoltaic devices is composed of an epitaxially grown crystalline layer. 25. A method of forming a photovoltaic structure, the method comprising: creating an outer surface on a donor semiconductor wafer having a conductive layer; and transferring the epitaxial layer to the insulator substrate. 26. According to the method of claim 25 of the patent scope, which further comprises: modifying the donor semiconductor _ sub-planting to treat the outer layer of the ferroconductor wafer; + bonding the epitaxial layer to the insulator substrate; The epitaxial layer is separated by the donor semiconductor wafer, thereby exposing at least the cracked surface. 27. According to the method of claim 26, the method further includes at least one-filament surface to carry out the test. 28. According to the method of claim _27, where $ = the first branch of the wafer - the first: 29 · at least according to the scope of the patent application, the process is applied to at least the outer rim; == 30. According to the scope of patent application 帛 28 items ^ °, Fang go, /, a group of multiple dressings, page 41 200814341 process at least applied to the body of the body wafer - split surface ceremony according to the application _ 27 The method of the item, wherein a plurality of the main processes of the trimming process are successively touched by the paper to generate the semiconductor material outside the annealing of the conductive grade thief. 32. According to the method of claim 26, wherein the bonding step comprises: and the conductor film of the conductor ;. ^ outside the body wafer; the insulator and the outer ride are pressed together and applied to the insulator and the ends of the donor semiconductor wafer to produce adhesion 33. According to any of the scope of claims 25 to 32 The method consists of a single crystal donor semiconductor wafer consisting of tantalum, niobium, or tantalum arsenide. 34. The method according to any one of claims 25 to 32, wherein the wafer is purchased by Sl's, Shen, Yi, Mi, GaP, and 1 counter. The bulk semiconductor wafer comprises a single crystal donor semiconductor 7 method in which the yoke is an i - 曰 曰曰 曰曰 ,, and the separation delamination layer is formed from the early 曰曰 曰曰 semiconductor wafer material. 36. According to the patent application, the 25th to 3rd semiconductor wafers comprise a single crystal donor semiconductor wafer and the intermediate application == conductor wafer, and the separation of the ^__ page 42 200814341 37. According to any of the patent applications 25 to 32 - Item 'shengsheng has a special electric layer--the epitaxial layer contains one or more 曰, ^ Fang, where vapor phase transport, vapor deposition, ion implantation, and oxidation 38. According to the patent application fines 25 to 32 any. The electrical layer contains metal as the main read material or metal oxide as the main guide. 39. According to the patent application _ 25 to 32 any - talent. Φ = Na's semi-conducting layer contains the back side connection = the outer 40. According to the patent application range No. 25 to 32, any one of the semi-guided riding ridges - guide 軏 辑 Hi Hi Hi Hi Hi Hi Hi η η η a semiconductor junction layer of a form doped region. Ό, 41. According to the method of claim 39, wherein the θ rear contact layer is composed of Al, Ti, Ni, W, In, M (Uu; pt, pd, Ga Ag, Ge or Shi Xi compound) And, b, conductive, consisting of tin-doped indium oxide, aluminum-doped zinc oxide, doped with zinc oxide or carbon nanotubes. 〃, boron 42. According to any patent application Nos. 25-41 : The structure is composed of single-joint first voltaic structure or multi-junction photovoltaic knotting _: first 43. According to t, please refer to any of the patent scopes 25 to 41 for the conversion of the material after the insulation crane is reversed. Applying at least one finishing process. 曰 44 44. According to the method of claim 43, wherein at least one of the repair processes produces at least one photovoltaic device layer with 200814341 before transferring to the insulator 。. Forming a method of any one of the optical structures of claim 25, wherein the method comprises: applying an ion implantation process to the donor semiconductor wafer; and forming an anode bonded by electrolysis Between the insulation and the body. The bulk wafer separates the epitaxial layer, thereby exposing at least one split surface; and forming a plurality of photovoltaic structures adjacent to the outer county and the hetero-insulator substrate. 46. According to the method of claim 45, further including At least one of the plurality of filaments, wherein the plurality of photovoltaic structures comprises at least one type of trimming 47. According to the method of claim 46, at least one of the facets comprises a _th axis (9) The second split surface of the county sand and the outer ride. 48' According to the method of claim 47, wherein a plurality of trimming processes are applied to at least the second split surface of the epitaxial layer. The plurality of trimming processes of the group-group are applied to at least the first splitting surface of the conductor wafer. 5〇. According to the method of claim 46, wherein the plurality of trimming processes are made of paper, Produce a lion, polish, anneal the raw passivation layer 'to create an encapsulation layer' and add additional semiconductor material to be selected. 200814341 Mode shape 51. According to the patent application The 45-step anodic bonding step comprises: illuminating at least one insulator substrate and donor semiconductor by electrolysis: insulator grounding or indirect switching: semiconductor wafer together; and semiconductor wafer ends to produce yang Tight the insulator substrate to the epitaxial layer - at A voltage is applied to the insulator substrate to adhere to the donor electrode. 52. The method according to claim 45, wherein the donor semiconductor is composed of an early-crystal donor semiconductor wafer, the donor semiconductor wafer being composed of a stone or a arsenide. 53. According to the method of the 45th patent range, it is selected by si, inspection, Sic, Ge, GaAs, GaP, * Inp. (4) A wafer 54. The method of claim 45, wherein the donor transfer wafer comprises a single crystal donor semiconductor wafer, and the separation is formed by a single crystal semiconductor wafer material. 55. The method of claim 45, wherein the donor semiconductor wafer comprises a single crystal donor semiconductor wafer and the epitaxial semiconductor layer is on the donor semiconductor wafer, and the separation extension layer is formed of an epitaxial semiconductor layer. See the method of claim 45, wherein the epitaxial layer having the conductive layer comprises one or more of a remote crystal, epitaxy, internal extension, vapor phase transport, vapor deposition, ion implantation, and oxidation. The method according to claim 45, wherein a plurality of photovoltaic layers comprise a semiconductor layer and a conductive layer. Page 45 200814341 58. According to the method of applying for patents, item 33, for the main material of Erke or metal secrets: Zhong (4) Baohu 59. According to the method of applying for patents, item 45, one of the layers Contains the material of the lion and the purchase of the gamma and '60. According to the method of claim 35 of the patent application &lt; Saki, the semiconductor junction layer of her form doped region. P 61. According to the method of claim 35, wherein the contact layer is composed of A1, Ti, Ni, w, In, M (Uu; pt, pd, Ga, Sn, sb, Ag, Ge or bismuth) And the conductive window layer is composed of tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide or carbon nanotubes. • According to the method of claim 45, wherein the photovoltaic structure is composed of The single-junction photovoltaic structure or the rural wire volt structure constitutes 63. - a system for forming a photovoltaic structure, the system comprises: a photovoltaic structure operation component, and a photovoltaic structure processing component; wherein the photovoltaic structure treatment The assembly includes a conditioning system and a transfer system, wherein the young system is conditioned by the photovoltaic structure operating component and the transfer system to transfer the epitaxial layer to the insulator substrate. 64. The system according to claim 63, wherein before transferring the insulator substrate Each epitaxial layer has a conductive layer. 65. The system according to claim 63 or 64, further comprising a bonding system, wherein the bonding system structure is formed by electrolysis Extremely sticky page 46 200814341 is connected between the insulator substrate and the epitaxial layer. The paper-silver according to any one of the patent scopes 63 to 65 further includes a finishing system, wherein the finishing system is implemented at least, The finishing process is performed by scribing, creating a backside contact layer, creating a conductive window layer, polishing, annealing, cleaning, creating a passivation layer, creating an encapsulation layer, and adding additional semiconductor material to be selected. Page 47