CN107134433A - 制作半导体装置的方法 - Google Patents

制作半导体装置的方法 Download PDF

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CN107134433A
CN107134433A CN201611108890.3A CN201611108890A CN107134433A CN 107134433 A CN107134433 A CN 107134433A CN 201611108890 A CN201611108890 A CN 201611108890A CN 107134433 A CN107134433 A CN 107134433A
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fin
semiconductor
semiconductor fin
area
substrate
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种包括以下步骤的制作半导体装置的方法。提供具有第一区域及第二区域的衬底。将衬底图案化，以在衬底中形成沟槽以及在沟槽之间形成半导体鳍，其中半导体鳍包括分布于第一区域中的第一半导体鳍及分布于第二区域中的第二半导体鳍。在第一区域中执行第一鳍切割工艺，以移除第一半导体鳍的部分。在执行第一鳍切割工艺之后，在沟槽中形成绝缘体。在第二区域中执行第二鳍切割工艺以移除第二半导体鳍的部分，直至在第二区域中在绝缘体之间形成凹部为止。形成栅极堆叠结构以局部地覆盖第一半导体鳍、第二半导体鳍及绝缘体。

Description

制作半导体装置的方法
技术领域
本发明的实施例涉及一种制作半导体装置的方法。
背景技术
随着半导体装置的大小不断缩减，已开发出三维多栅极结构(例如鳍型场效晶体管(fin-type field effect transistor，FinFET))以取代平面的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)装置。鳍型场效晶体管的结构特征为从衬底的表面直立延伸的硅系鳍(silicon-based fin)，且包裹于由半导体鳍形成的导通沟道周围的栅极进一步提供对沟道的更好的电性控制。
在制作鳍型场效晶体管期间，通过後进行的鳍切割工艺(fin cut last process)将半导体鳍图案化以移除半导体鳍的不需要的部分，且在鳍切割工艺之后，接着形成浅沟槽隔离(shallow trench isolation，STI)及栅极堆叠结构。在鳍切割工艺期间，形成图案化光刻胶层以局部地覆盖半导体鳍且对半导体鳍的不需要的部分进行刻蚀。由于在鳍切割工艺中使用的图案化光刻胶层形成于衬底之上，且因而图案化光刻胶层可能厚度不足以保护被覆盖的半导体鳍，特别是分布于半导体装置的密集区域(例如，核心区域)中的半导体鳍，因此，在鳍切割工艺期间会出现鳍损坏现象且鳍切割工艺的稳定性会劣化。
发明内容
根据本发明的某些实施例，提供一种包括以下步骤的制作半导体装置的方法。提供具有第一区域及第二区域的衬底。将衬底图案化以在衬底中形成多个沟槽及在沟槽之间形成多个半导体鳍，其中半导体鳍包括分布于第一区域中的多个第一半导体鳍及分布于第二区域中的多个第二半导体鳍。在第一区域中执行第一鳍切割工艺，以移除第一半导体鳍的部分。在执行第一鳍切割工艺之后，在沟槽中形成多个绝缘体。在第二区域中执行第二鳍切割工艺以移除第二半导体鳍的部分，直至在第二区域中在绝缘体之间形成多个凹部为止。形成栅极堆叠结构，以局部地覆盖第一半导体鳍、第二半导体鳍及绝缘体。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1说明用以说明根据本发明某些实施例的制作半导体装置的方法的流程图。
图2A至图2L是根据本发明某些实施例的制作分布于半导体装置的密集区域中的鳍型场效晶体管的方法的立体图。
图3A至图3L是根据本发明某些实施例的制作分布于半导体装置的密集区域中的鳍型场效晶体管的方法的剖视图。
图4A至图4L是根据本发明某些实施例的制作分布于半导体装置的输入/输出(I/O)区域中的鳍型场效晶体管的方法的立体图。
图5A至图5L是根据本发明某些实施例的制作分布于半导体装置的输入/输出区域中的鳍型场效晶体管的方法的剖视图。
图6及图7示意性地说明图2G及图3G的修改形式。
图8及图9示意性地说明图2H及图3H的修改形式。
[符号的说明]
100：衬底
100a：半导体衬底
102a：保护层
102a’：图案化保护层
102b：硬掩模层
102b’：图案化硬掩模层
104：图案化光刻胶层
106：沟槽
108A：第一半导体鳍
108A’：第一半导体部分
108B：第二半导体鳍
108B’：第二半导体部分
110：介电层
110a：绝缘体
111：凹部
112：栅极介电层
114：拟栅极条
116：间隔壁
118：图案化介电层
122：栅极
C：空腔
CS、CS’：曲面
D：深度
D1、D2：长度方向
DS：介电结构
GS：栅极堆叠结构
H：高度差
PR1：第一图案化光刻胶层
PR2：第二图案化光刻胶层
S：间距
S10、S20、S30、S40、S50、S60：步骤
T1、T2：顶表面
V：孔洞
W：宽度
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成于第二特征之上或第二特征上可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复参考编号及/或字母。这种重复是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的定向外还囊括装置在使用或操作中的不同定向。设备可具有其他定向(旋转90度或处于其他定向)且本文中所用的空间相对性描述语可同样相应地进行解释。
本发明的实施例阐述鳍型场效晶体管的示例性制作工艺。在本发明的某些实施例中可在块状硅(bulk silicon)衬底上形成鳍型场效晶体管。再者，在其他实施例中，可在绝缘体上硅(silicon-on-insulator，SOI)衬底或绝缘体上锗(germanium-on-insulator，GOI)衬底上形成鳍型场效晶体管。此外，根据实施例，衬底可包括其他导电层或其他半导体元件(例如晶体管、二极管等)。实施例在本上下文中不受限制。
图1说明用以说明根据本发明某些实施例的制作半导体装置的方法的流程图。参照图1，方法至少包括步骤S10、步骤S20、步骤S30、步骤S40、步骤S50及步骤S60。首先，在步骤S10中，提供具有至少一个第一区域(例如，一或多个输入/输出区域)及至少一个第二区域(例如，一或多个密集区域)的衬底。接着，在步骤S20中，将衬底图案化以在衬底中形成多个沟槽及在沟槽之间形成多个半导体鳍，其中半导体鳍包括分布于第一区域中的多个第一半导体鳍及分布于第二区域中的多个第二半导体鳍。接着，在步骤S30中，在第一区域中执行第一鳍切割工艺，以移除第一半导体鳍的部分。在步骤S40中，在执行第一鳍切割工艺之后，在沟槽中形成多个绝缘体。在步骤S50中，在第二区域中执行第二鳍切割工艺，以移除第二半导体鳍的部分，直至在第二区域中在绝缘体之间形成多个凹部为止。之后，在步骤S60中，形成栅极堆叠结构以局部地覆盖第一半导体鳍、第二半导体鳍及绝缘体。在某些实施例中，上述密集区域是具有高电路集成或布局密度的区域而上述输入/输出区域是具有低电路集成或布局密度的区域。
结合图1、图2A至图2L、图3A至图3L、图4A至图4L及图5A至图5L来阐述包括鳍型场效晶体管的半导体装置的制作。图2A至图2L是根据本发明某些实施例的制作分布于半导体装置的密集区域中的鳍型场效晶体管的方法的立体图；图3A至图3L是根据本发明某些实施例的制作分布于半导体装置的密集区域中的鳍型场效晶体管的方法的剖视图；图4A至图4L是根据本发明某些实施例的制作分布于半导体装置的输入/输出区域中的鳍型场效晶体管的方法的立体图；且图5A至图5L是根据本发明某些实施例的制作分布于半导体装置的输入/输出区域中的鳍型场效晶体管的方法的剖视图。
在图1中的步骤S10中且如图2A、图3A、图4A及图5A中所示，提供具有至少一个第一区域(例如，一或多个输入/输出区域)及至少一个第二区域(例如，一或多个密集区域)的衬底100。衬底100的第一区域在图4A及图5A中示出，而衬底100的第二区域在图2A及图3A中示出。
在一个实施例中，衬底100包括晶体硅衬底(例如，晶片(wafer))。根据设计要求(例如，p型衬底或n型衬底)，衬底100可包括各种掺杂区。在某些实施例中，掺杂区可被掺杂以p型掺杂剂或n型掺杂剂。举例来说，掺杂区可被掺杂以p型掺杂剂，例如硼或BF2；n型掺杂剂，例如磷或砷及/或其组合。掺杂区可被配置用于n型鳍型场效晶体管或作为另外一种选择被配置用于p型鳍型场效晶体管。在某些替代实施例中，衬底100可由下列制成：某些其他合适的元素半导体，例如金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗、磷化镓砷或磷化镓铟。
在图1中的步骤S20中且如图2A至图2B、图3A至图3B、图4A至图4B及图5A至图5B中所示，在衬底100的第一区域及第二区域上依序形成保护层102a及硬掩模层102b。保护层102a可为例如通过热氧化(thermal oxidation)工艺形成的氧化硅薄膜。保护层102a可充当衬底100与硬掩模层102b之间的粘着层。保护层102a也可充当用于刻蚀硬掩模层102b的刻蚀终止层。在至少一个实施例中，硬掩模层102b是例如通过低压化学气相沉积(low-pressure chemical vapor deposition，LPCVD)或等离子体增强型化学气相沉积(plasmaenhanced chemical vapor deposition，PECVD)等形成的氮化硅层。在硬掩模层102b上形成具有预定图案的图案化光刻胶层104。
如图2B、图3B、图4B及图5B中所示，依序刻蚀未被图案化光刻胶层104覆盖的硬掩模层102b及保护层102a，以形成图案化硬掩模层102b’及图案化保护层102a’，进而暴露出下面的衬底100。利用图案化硬掩模层102b’、图案化保护层102a’及图案化光刻胶层104作为掩模，暴露出衬底100的部分并刻蚀衬底100的部分以获得半导体衬底100a，半导体衬底100a具有沟槽106、分布于第一区域中的多个第一半导体鳍108A(图4B至图5B中所示)以及分布于第二区域中的多个第二半导体鳍108B(图2B至图3B中所示)。举例来说，第一半导体鳍108A与第二半导体鳍108B实质上彼此平行。图4B至图5B中所示的第一半导体鳍108A的数目以及图2B至图3B中所示的第二半导体鳍108B的数目仅用于说明。在某些替代实施例中，至少一个半导体鳍108A、108B(例如，一个、两个、三个或超过四个)可根据实际设计要求而形成。在形成沟槽106之后，第一半导体鳍108A及第二半导体鳍108B被图案化硬掩模层102b’、图案化保护层102a’及图案化光刻胶层104覆盖。两个邻近的沟槽106以间距S间隔开。举例来说，位于两个相邻的沟槽106之间的间距S可小于约30纳米。换句话说，第一区域中的两个相邻的沟槽106被第一半导体鳍108A中的一者间隔开而第二区域中的两个相邻的沟槽106被第二半导体鳍108B间隔开。第一半导体鳍108A的宽度及第二半导体鳍108B的宽度与间距S实质上相同。
在某些实施例中，沟槽106的宽度W介于约20纳米至约48纳米的范围内。举例来说，第一半导体鳍108A的高度及第二半导体鳍108B的高度以及沟槽106的深度D介于约40纳米至约70纳米的范围内。在形成沟槽106、第一半导体鳍108A及第二半导体鳍108B之后，移除图案化光刻胶层104。在一个实施例中，可执行清洗工艺来移除半导体衬底100a的天然氧化物(native oxide)，半导体衬底100a具有形成于其上的第一半导体鳍108A及第二半导体鳍108B。可利用稀释的氢氟(diluted hydrofluoric，DHF)酸或其他合适的清洗溶液来执行清洗工艺。
在图1中的步骤S30中且如图2B至图2C、图3B至图3C、图4B至图4C及图5B至图5C中所示，在形成沟槽106、第一半导体鳍108A及第二半导体鳍108B之后，在第一区域中执行第一鳍切割工艺以移除第一半导体鳍108A的不需要的部分。举例来说，通过光刻工艺及刻蚀工艺来执行第一鳍切割工艺。第一鳍切割工艺的详细描述如下。
在半导体衬底100a上形成第一图案化光刻胶层PR1，进而使第一区域中的第一半导体鳍108A被第一图案化光刻胶层PR1局部地覆盖。第一图案化光刻胶层PR1进一步覆盖第二区域中的第二半导体鳍108B。接着，移除未被第一图案化光刻胶层PR1覆盖的第一半导体鳍108A的部分，进而使得在半导体衬底100a上形成或存留多个第一半导体部分108A’。举例来说，通过刻蚀工艺移除未被第一图案化光刻胶层PR1覆盖的第一半导体鳍108A的部分。在某些替代实施例中，可通过恰当的工艺控制完全地移除未被第一图案化光刻胶层PR1覆盖的第一半导体鳍108A的部分。换句话说，视需要在半导体衬底100a上形成第一半导体部分108A’。在第一鳍切割工艺期间，第二半导体鳍108B被第一图案化光刻胶层PR1保护。在移除第一半导体鳍108A的不需要的部分之后，移除第一图案化光刻胶层PR1。
在图1中的步骤S40中且如图2C至图2D、图3C至图3D、图4C至图4D及图5C至图5D中所示，在执行第一鳍切割工艺之后，接着在半导体衬底100a之上形成介电层110。介电层110填充沟槽106并覆盖第一半导体部分108A’、第一半导体鳍108A及第二半导体鳍108B。除第一半导体部分108A’、第一半导体鳍108A及第二半导体鳍108B之外，介电层110进一步覆盖图案化保护层102a’及图案化硬掩模层102b’。介电层110可包含氧化硅、氮化硅、氮氧化硅、旋涂(spin-on)介电材料或低介电系数介电材料。可通过高密度等离子化学气相沉积(high-density-plasma chemical vapor deposition，HDP-CVD)、次大气压化学气相沉积(sub-atmospheric CVD，SACVD)或通过旋涂来形成介电层110。在某些替代实施例中，介电层110是由化学气相沉积(chemical vapor deposition，CVD)工艺及固化工艺形成的流动(flowable)介电层。
在图1中的步骤S40中且如图2D至图2E、图3D至图3E、图4D至图4E及图5D至图5E中所示，举例来说，执行例如化学机械抛光(chemical mechanical polish，CMP)工艺等平坦化工艺来移除介电层110的位于沟槽106外的部分、图案化硬掩模层102b’及图案化保护层102a’，直至暴露出第一半导体鳍108A及第二半导体鳍108B的顶表面T2为止。如图2E、3E、4E及图5E中所示，在对介电层110进行抛光之后，经抛光的介电层110的顶表面与第一半导体鳍108A及第二半导体鳍108B的顶表面T2实质上对准或共平面。
在图1中的步骤S40中且如图2E至图2F、图3E至图3F、图4E至图4F及图5E至图5F中所示，在移除沟槽106外的介电层110之后，沟槽106中的其余介电层110通过刻蚀工艺被局部地移除，进而使得在沟槽106中形成绝缘体110a(例如，浅沟槽隔离结构)且绝缘体110a局部地覆盖第一半导体鳍108A及第二半导体鳍108B的侧壁。在某些实施例中，刻蚀工艺可为使用氢氟酸(hydrofluoric acid，HF)的湿刻蚀(wet etching)工艺或干刻蚀(dryetching)工艺。
如图2F、图3F、图4F及图5F中所示，绝缘体110a的顶表面T1低于第一半导体鳍108A及第二半导体鳍108B的顶表面T2。第一半导体鳍108A及第二半导体鳍108B从绝缘体110a的顶表面T1突出。举例来说，第一半导体鳍108A及第二半导体鳍108B的顶表面T2与绝缘体110a的顶表面T1之间的高度差H(即，鳍高度)介于约15纳米至约50纳米的范围内。此外，如图4F及图5F中所示，第一半导体部分108A’被绝缘体110a覆盖。
在图1中的步骤S50中且如图2F至图2G、图3F至图3G、图4F至图4G及图5F至图5G中所示，执行第二鳍切割工艺以移除第二半导体鳍108B的不需要的部分，直至在第二区域中在绝缘体110a之间形成多个凹部111为止。举例来说，通过光刻工艺及刻蚀工艺来执行第二鳍切割工艺。第二鳍切割工艺的详细描述如以下所示。
在绝缘体110a的顶表面T1上形成第二图案化光刻胶层PR2，进而使第二半导体鳍108B的需要的部分被局部地覆盖。换句话说，第二半导体鳍108B的不需要的部分不被覆盖且被第二图案化光刻胶层PR2暴露出。第二图案化光刻胶层PR2进一步覆盖第一区域中的第一半导体鳍108A。接着，移除未被第二图案化光刻胶层PR2覆盖的第二半导体鳍108B的部分，进而使得在半导体衬底100a上形成或存留多个第二半导体部分108B’。由于第二图案化光刻胶层PR2形成于绝缘体110a的顶表面T1上，因此分布于半导体装置的第二区域(例如，核心区域)中的第二半导体鳍108B可容易地被第二图案化光刻胶层PR2覆盖并受到第二图案化光刻胶层PR2的保护。换句话说，第二半导体鳍108B的上部部分被第二图案化光刻胶层PR2保护而第二半导体鳍108B的下部部分被绝缘体110a保护。当形成第二图案化光刻胶层PR2以覆盖分布于半导体装置的第二区域(例如，核心区域)中的第二半导体鳍108B时，由於第二半导体鳍108B的下部部分被绝缘体110a保护，因此，容易满足第二图案化光刻胶层PR2的厚度要求(即，充分厚)。相似地，第二图案化光刻胶层PR2妥善地保护分布于半导体装置的第一区域(例如，输入/输出区域)中的第一半导体鳍108A。
在绝缘体110a之上形成第二图案化光刻胶层PR2之后，移除未被第二图案化光刻胶层PR2覆盖的第二半导体鳍108B的不需要的部分，直至在第二区域中在绝缘体110a之间形成凹部111为止。第二半导体鳍108B的不需要的部分的移除是自对准工艺(self-alignedprocess)，且在形成第二图案化光刻胶层PR2时具有足够大工艺窗口(process window)。在某些实施例中，利用第二图案化光刻胶层PR2作为刻蚀掩模来刻蚀第二半导体鳍108B的不需要的部分。在移除第二半导体鳍108B的不需要的部分期间，第二半导体鳍108B的不需要的部分例如被刻蚀剂(例如，HBr、He、Cl2、NF3、O2、SF6、CF4、CH3F、CH2F2、CHxFy、N2、SO2、Ar等)有效地刻蚀，且刻蚀剂并不会大幅地损坏绝缘体110a。在某些实施例中，上述用于移除第二半导体鳍108B的不需要的部分的刻蚀工艺可为湿刻蚀工艺或干刻蚀工艺。
凹部111的数目仅用于说明，在某些替代实施例中，可根据实际设计要求形成一个凹部或超过两个凹部。
如图2G、图3G、图4G及图5G中所示，在移除第二半导体鳍108B的不需要的部分之后，在凹部111下方存留有多个第二半导体部分108B’。在某些实施例中，第二半导体部分108B’可包括位于其顶部上的曲面CS且曲面CS被凹部111暴露出。曲面CS低于绝缘体110a的顶表面T1。举例来说，第二半导体部分108B’是位于凹部111下方的突出部分。此外，举例来说，曲面CS是凹陷的表面。
在某些替代实施例中，如图6及图7中所示，可移除(例如，刻蚀掉)第二半导体鳍108B的不需要的部分，直至形成半导体衬底100a的多个曲面CS’且多个曲面CS’被凹部111暴露出。曲面CS’低于绝缘体110a的底表面。换句话说，在凹部111中不存留有半导体部分或突出部。举例来说，曲面CS’是凹陷的表面。
在移除第二半导体鳍108B的不需要的部分之后，移除图2G、图3G、图4G及图5G中所示的第二图案化光刻胶层PR2。
在图1中的步骤S60中且如图2H至图2L、图3H至图3L、图4H至图4L及图5H至图5L中所示，接着形成栅极堆叠结构GS(图2L及图4L中所示)，以局部地覆盖第一半导体鳍108A、第二半导体鳍108B及绝缘体110a。
在图1中的步骤S60中且如图2H、图3H、图4H及图5H中所示，形成栅极介电层112以填充凹部111并覆盖第一半导体鳍108A、第二半导体鳍108B及绝缘体110a。换句话说，在第二区域中在绝缘体110a之间的凹部111被栅极介电层112及半导体部分108B’填充。在第二区域中在绝缘体110a之间填充的栅极介电层112提供良好的绝缘特性及结构强度。在某些实施例中，栅极介电层112的厚度处于约1纳米至约50纳米的范围内。栅极介电层112可包含氧化硅、氮化硅、氮氧化硅或高介电系数电介质。高介电系数电介质包括金属氧化物。用于高介电系数电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物及/或其混合物。可通过例如原子层沉积(atomic layer deposition，ALD)、化学气相沉积(CVD)、物理气相沉积(physical vapordeposition，PVD)、热氧化、紫外臭氧氧化(UV-ozone oxidation)等合适的工艺来形成栅极介电层112。
在某些实施例中，绝缘体110a之间的凹部111可完全被栅极介电层112及半导体部分108B’填充。换句话说，栅极介电层112包括分布于凹部111中的少量孔洞。在某些替代实施例中，如图8及图9中所示，栅极介电层112可包括分布于凹部111中的孔洞V。应注意，栅极介电层112中的孔洞V可增强栅极介电层112的绝缘特性且提供充分的结构强度。
在图1中的步骤S60中且如图2H至图2I、图3H至图3I、图4H至图4I及图5H至图5I中所示，在栅极介电层112上形成拟栅极条114，其中拟栅极条114的长度方向D1不同于第一半导体鳍108A及第二半导体鳍108B的长度方向D2。在某些实施例中，拟栅极条114的长度方向D1垂直于第一半导体鳍108A及第二半导体鳍108B的长度方向D2。图2I及图4I中所示的拟栅极条114的数目仅用于说明，在某些替代实施例中，可根据实际设计要求在第一区域及第二区域中形成两个或更多个平行拟栅极条。拟栅极条114包含含有硅的材料，例如多晶硅、非晶硅或其组合。
如图2I及图4I中所示，在形成拟栅极条114之后，在拟栅极条114的侧壁上形成一对间隔壁116。间隔壁116形成于栅极介电层112上且沿拟栅极条114的侧壁延伸。换句话说，间隔壁116沿长度方向D1延伸。间隔壁116由例如氮化硅或SiCON等介电材料形成。间隔壁116可包括单层结构或多层结构。
在图1中的步骤S60中且如图2I至图2J、图3I至图3J、图4I至图4J及图5I至图5J中所示，形成图案化介电层118以覆盖未被拟栅极条114及间隔壁116覆盖的栅极介电层112。举例来说，图案化介电层118的顶表面与拟栅极条114的顶表面实质上共平面。在某些实施例中，在形成图案化介电层118之前，可提前执行某些工艺(例如，栅极介电层112的图案化工艺、第一半导体鳍108A及第二半导体鳍108B的凹入(recessing)工艺、对半导体鳍108进行的应变源极/漏极外延工艺、硅化(silicidation)工艺等)。不再对上述可选的工艺的细节予以赘述。
如图2J至图4J中所示，间隔壁116与图案化介电层118的组合可被视作邻近于拟栅极条114的介电结构DS。换句话说，拟栅极条114可嵌于介电结构DS中且介电结构DS局部地覆盖第一半导体鳍108A、第二半导体鳍108B及绝缘体110a。
在图1中的步骤S60中且如图2J至图2K、图3J至图3K、图4J至图4K及图5J至图5K中所示，移除拟栅极条114。在某些实施例中，例如通过刻蚀工艺移除拟栅极条114。通过恰当地选择刻蚀剂来移除拟栅极条114，而不会对图案化介电层118、栅极介电层112及间隔壁116造成大幅的损坏。在移除拟栅极条114之后，在间隔壁116之间形成空腔C。换句话说，栅极介电层112被空腔C局部地暴露出。
在图1中的步骤S60中且如图2K至图2L、图3K至图3L、图4K至图4L及图5K至图5L中所示，在形成空腔C之后，栅极122形成于空腔C中且填充空腔C，并且栅极122覆盖被空腔C暴露出的栅极介电层112。栅极122的宽度与拟栅极条114(如图2I及图4I中所示)的宽度实质上相同。鳍型场效晶体管的沟道长度与栅极122的宽度相关或由栅极122的宽度来决定。换句话说，第一半导体鳍108A及第二半导体鳍108B的与对应的栅极122交叠且被对应的栅极122覆盖的部分分别用作鳍型场效晶体管的沟道。
如图2L、图3L、图4L及图5L中所示，举例来说，在一个实施例中，栅极122及其下面的栅极介电层112被视作栅极堆叠结构GS，在栅极堆叠结构GS的侧壁上形成介电结构DS(例如，间隔壁116或间隔壁116与图案化介电层118的组合)，且介电结构DS的顶表面与栅极堆叠结构GS的顶表面实质上共平面。在某些替代实施例中，可省略上述栅极置换工艺(图2K至图2L及图3K至图3L)。
在本发明的实施例中，由于上述第二鳍切割工艺是在形成绝缘体之后执行的，因而其余的半导体鳍可被妥善地保护。因此，半导体装置或鳍型场效晶体管的性能(例如，泄漏、芯片探测(Cp)良率等)、可靠性及工艺控制(例如，工艺窗口)可得到提高。
根据本发明的某些实施例，提供一种包括以下步骤的制作半导体装置的方法。提供具有第一区域及第二区域的衬底。将所述衬底图案化以在所述衬底中形成多个沟槽及在所述沟槽之间形成多个半导体鳍，其中所述半导体鳍包括分布于所述第一区域中的多个第一半导体鳍及分布于所述第二区域中的多个第二半导体鳍。在所述第一区域中执行第一鳍切割工艺，以移除所述第一半导体鳍的部分。在执行所述第一鳍切割工艺之后，在所述沟槽中形成多个绝缘体。在所述第二区域中执行第二鳍切割工艺以移除所述第二半导体鳍的部分，直至在所述第二区域中在所述绝缘体之间形成多个凹部为止。形成栅极堆叠结构，以局部地覆盖所述第一半导体鳍、所述第二半导体鳍及所述绝缘体。
在所述的方法中，所述第一鳍切割工艺包括：形成第一图案化光刻胶层，以局部地覆盖所述第一半导体鳍，其中所述第二半导体鳍被所述第一图案化光刻胶层覆盖；移除未被所述第一图案化光刻胶层覆盖的所述第一半导体鳍的所述部分；以及在移除所述第一半导体鳍的所述部分之后，移除所述第一图案化光刻胶层。
在所述的方法中，所述第二鳍切割工艺包括：形成第二图案化光刻胶层，以局部地覆盖所述第二半导体鳍，其中所述第一半导体鳍被所述第二图案化光刻胶层覆盖；移除未被所述第二图案化光刻胶层覆盖的所述第二半导体鳍的所述部分，直至在所述第二区域中在所述绝缘体之间形成所述凹部为止；以及在形成所述凹部之后，移除所述第二图案化光刻胶层。
在所述的方法中，在执行所述第二鳍切割工艺之后，形成所述衬底的多个曲面且所述多个曲面被所述凹部暴露出。
在所述的方法中，所述第一半导体鳍的所述部分被移除以形成多个第一半导体部分，且所述第二半导体鳍的所述部分被移除以在所述绝缘体之间形成多个第二半导体部分。
在所述的方法中，形成所述栅极堆叠结构的方法包括：形成栅极介电层，所述栅极介电层填充所述凹部并覆盖所述绝缘体、所述第一半导体鳍及所述第二半导体鳍；以及在所述栅极介电层上形成栅极。
在所述的方法中，在执行所述第二鳍切割工艺之后，形成所述衬底的多个曲面且所述多个曲面被所述凹部暴露出，并且被所述凹部暴露出的所述曲面被所述栅极介电层覆盖。
在所述的方法中，所述第一半导体鳍的所述部分被移除以形成多个第一半导体部分，所述第二半导体鳍的所述部分被移除以形成被所述凹部暴露出的多个第二半导体部分，且被所述凹部暴露出的所述第二半导体部分被所述栅极介电层覆盖。
在所述的方法中，所述栅极介电层包括分布于所述凹部中的多个孔洞。
根据本发明的其他实施例，提供一种包括以下步骤的制作半导体装置的方法。提供具有第一区域及第二区域的衬底。将所述衬底图案化以在所述衬底中形成多个沟槽及在所述沟槽之间形成多个半导体鳍，其中所述半导体鳍包括分布于所述第一区域中的多个第一半导体鳍及分布于所述第二区域中的多个第二半导体鳍。在所述第一区域中执行第一鳍切割工艺。在执行所述第一鳍切割工艺之后，在所述沟槽中形成多个绝缘体。接着，在所述第二区域中执行的第二鳍切割工艺。之后，形成栅极介电层，以填充所述凹部并覆盖所述绝缘体及所述半导体鳍。在所述栅极介电层上形成栅极。所述第一鳍切割工艺包括以下步骤。形成第一图案化光刻胶层，以局部地覆盖所述第一半导体鳍，其中所述第二半导体鳍被所述第一图案化光刻胶层覆盖。移除未被所述第一图案化光刻胶层覆盖的所述第一半导体鳍的部分。在移除所述第一半导体鳍的部分之后，移除所述第一图案化光刻胶层。所述第二鳍切割工艺包括以下步骤。形成第二图案化光刻胶层，以局部地覆盖所述第二半导体鳍，其中所述第一半导体鳍被所述第二图案化光刻胶层覆盖。移除未被所述第二图案化光刻胶层覆盖的所述第二半导体鳍的部分，直至在所述第二区域中在所述绝缘体之间形成所述凹部为止。在形成所述凹部之后，移除所述第二图案化光刻胶层。
在所述的方法中，在执行所述第二鳍切割工艺之后，形成所述衬底的多个曲面且所述多个曲面被所述凹部暴露出，并且被所述凹部暴露出的所述曲面被所述栅极介电层覆盖。
在所述的方法中，所述第一半导体鳍的所述部分被移除以形成多个第一半导体部分，所述第二半导体鳍的所述部分被移除以形成被所述凹部暴露出的多个第二半导体部分，且被所述凹部暴露出的所述第二半导体部分被所述栅极介电层覆盖。
在所述的方法中，所述第一半导体部分被所述绝缘体覆盖。
在所述的方法中，所述栅极介电层包括分布于所述凹部中的多个孔洞。
根据本发明的另一实施例，提供一种半导体装置，所述半导体装置包括衬底、多个绝缘体、栅极介电层及栅极。所述衬底包括多个沟槽及位于所述沟槽之间的至少一个半导体鳍。所述半导体鳍包括分布于所述第一区域中的多个第一半导体鳍及分布于所述第二区域中的多个第二半导体鳍。所述绝缘体配置于所述沟槽中，其中所述绝缘体中的分布于所述第一区域中的两者被所述第一半导体鳍中的一者间隔开且所述绝缘体中的分布于所述第二区域中的至少两者被位于其之间的至少一个凹部间隔开。所述至少一个凹部被所述栅极介电层填充。所述栅极介电层覆盖所述绝缘体、所述第一半导体鳍及所述第二半导体鳍。所述栅极配置于所述栅极介电层上，且所述栅极局部地覆盖所述绝缘体、所述第一半导体鳍及所述第二半导体鳍。
在所述的半导体装置中，所述至少一个凹部的宽度等于所述第二半导体鳍的宽度。
在所述的半导体装置中，所述衬底的至少一个曲面被所述至少一个凹部暴露出且被所述栅极介电层覆盖。
在所述的半导体装置中，所述衬底包括位于所述至少一个凹部下方的至少一个半导体部分，且所述至少一个半导体部分被所述栅极介电层覆盖。
在所述的半导体装置中，所述至少一个凹部被所述栅极介电层及所述半导体部分填充。
在所述的半导体装置中，所述栅极介电层包括分布于所述凹部中的多个孔洞。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或达成与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，该些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种制作半导体装置的方法，其特征在于，包括：
提供具有第一区域及第二区域的衬底；
将所述衬底图案化，以在所述衬底中形成多个沟槽以及在所述沟槽之间形成多个半导体鳍，所述半导体鳍包括分布于所述第一区域中的多个第一半导体鳍及分布于所述第二区域中的多个第二半导体鳍；
在所述第一区域中执行第一鳍切割工艺，以移除所述第一半导体鳍的部分；
在执行所述第一鳍切割工艺之后，在所述沟槽中形成多个绝缘体；
在所述第二区域中执行第二鳍切割工艺以移除所述第二半导体鳍的部分，直至在所述第二区域中在所述绝缘体之间形成多个凹部为止；以及
形成栅极堆叠结构以局部地覆盖所述第一半导体鳍、所述第二半导体鳍及所述绝缘体。
CN201611108890.3A 2016-02-26 2016-12-06 制作半导体装置的方法 Pending CN107134433A (zh)

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