CN107112321B - 低剖面加强层叠封装半导体器件 - Google Patents

低剖面加强层叠封装半导体器件 Download PDF

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Publication number
CN107112321B
CN107112321B CN201580068185.2A CN201580068185A CN107112321B CN 107112321 B CN107112321 B CN 107112321B CN 201580068185 A CN201580068185 A CN 201580068185A CN 107112321 B CN107112321 B CN 107112321B
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semiconductor devices
semiconductor
semiconductor packages
redistribution layer
lid structure
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CN107112321A (zh
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H·B·蔚
D·W·金
K-P·黄
Y·K·宋
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Qualcomm Inc
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Qualcomm Inc
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Abstract

本公开提供了半导体封装以及用于制造PoP半导体封装的方法。该PoP半导体封装可包括第一半导体封装和第二半导体封装，该第一半导体封装包括阳极化金属盖结构，该结构包括(i)具有中央空腔开口方向的中央空腔以及(ii)具有面向与该中央空腔开口方向相反的方向的周界空腔开口方向的至少一个周界空腔；布置在该阳极化金属盖结构的中央空腔中的第一半导体器件；电耦合到该第一半导体器件的重分布层，其中在该重分布层中形成的导电迹线向该至少一个周界空腔曝露；以及布置在该至少一个周界空腔中的焊料材料，该第二半导体封装包括至少一个导电桩，其中该至少一个导电桩被电耦合到布置在该至少一个周界空腔中的焊料材料。

Description

低剖面加强层叠封装半导体器件
引言
本公开的诸方面一般涉及半导体器件，并尤其涉及增强具有层叠封装(PoP)半导体器件结构的半导体器件的密度和促成具有层叠封装(PoP)半导体器件结构的制造。
已经为其中电路板空间必须被节省的应用(诸如蜂窝电话和其他便携式设备之类)开发了层叠封装(PoP)半导体器件。在一种可能的场景中，底部封装是处理器封装，而顶部封装是存储器封装。PoP技术具有相对于其他技术(诸如堆栈管芯电路)而言的某些益处。例如，制造商能够通过在PoP结构中替换不同的存储器封装而非绑定到特定存储器来降低成本和增加灵活性。此外，PoP结构的顶部封装和底部封装可被独立测试。作为对比，若堆栈管芯结构中包括不良管芯，那么整个结构必须被弃用。
图1解说了典型PoP半导体器件100。电路板110被耦合到第一封装130。如图1中所示，第一封装130是底部封装。具体而言，电路板110包括电路板触点112，和将电路板110耦合到第一封装130的焊球120。第一封装130包括第一基板140和第一半导体器件150。第一半导体器件150可以被嵌入到第一模具152中。在一个可能的场景中，第一半导体器件150是处理器。第一封装130经由焊球160被耦合到第二封装170。焊球160将第一封装130的表面上的触点(未示出)耦合到第二封装170的表面上的触点(未示出)。第二封装170包括第二基板180和第二半导体器件190。第二半导体器件190可以被嵌入到第二模具192中。
改进的PoP半导体器件设计面临两个关键的技术挑战。首先，PoP半导体器件的总体高度必须被减小使得该器件剖面较小。其次，随着PoP半导体器件的组件变得更薄，它们变得更加难以制造。例如，图1中示出的第一基板140可能在制造期间显现出增加的翘曲倾向。作为结果，需要新的材料、设计和工艺来防止制造期间薄组件的翘曲。
相应地，在本领域中需要提供增大的密度和制造的简易度的改进的PoP架构。
概览
在一方面，本公开提供了一种PoP半导体封装，该PoP半导体封装包括第一半导体封装和第二半导体封装，该第一半导体封装包括阳极化金属盖结构，该结构包括(i)具有中央空腔开口方向的中央空腔以及(ii)具有面向与该中央空腔开口方向相反的方向的周界空腔开口方向的至少一个周界空腔；布置在该阳极化金属盖结构的该中央空腔中的第一半导体器件；电耦合到该第一半导体器件的重分布层，其中在该重分布层中形成的导电迹线向该至少一个周界空腔曝露；以及布置在该至少一个周界空腔中的焊料材料，该第二半导体封装包括至少一个导电桩，其中该至少一个导电桩被电耦合到布置在该至少一个周界空腔中的焊料材料。
在另一方面，本公开提供了一种制造PoP半导体封装的方法，该方法包括形成阳极化金属盖结构，其中形成该阳极化金属盖结构包括在该阳极化金属盖结构中定义具有中央空腔开口方向的中央空腔，以及在该阳极化金属盖结构中定义具有周界空腔开口方向的至少一个周界空腔，其中该周界空腔开口方向面向与该中央空腔开口方向相反的方向；将第一半导体器件放置到该阳极化金属盖结构的中央空腔中；通过将该第一半导体器件电耦合到重分布层来形成第一半导体封装，其中该重分布层中形成的导电迹线向该至少一个周界空腔曝露；用焊料材料来填充该至少一个周界空腔的至少部分；以及通过将至少一个导电桩耦合到该焊料材料来将具有该至少一个导电桩的第二半导体封装附连到该第一半导体封装。
在还有另一方面，本公开提供了一种PoP半导体器件，该PoP半导体器件包括第一半导体封装和第二半导体封装，该第一半导体封装包括用于电隔离并保护该第一半导体封装的装置，该装置具有第一开口并具有面向与该第一开口相反的方向的第二开口；布置在该用于电隔离并保护该第一半导体器件的装置的第一开口中的第一半导体器件；耦合到该第一半导体器件的用于重分布电信号的装置，其中该用于重分布电信号的装置向该第二开口曝露，以及布置在该第二开口中的第一用于耦合的装置，该第二半导体封装包括第二用于耦合的装置，其中该第二用于耦合的装置电耦合到布置在用于转移电荷的装置中的该第一用于耦合的装置。
附图简述
对本公开的各方面及其许多伴随优点的更完整领会将因其在参考结合附图考虑的以下详细描述时变得更好理解而易于获得，附图仅出于解说目的被给出而不对本发明构成任何限定，并且其中：
图1一般地解说了常规PoP半导体器件封装。
图2一般地解说了根据本公开的一方面的PoP半导体器件封装。
图3一般地解说了根据本公开的一方面的示例性制造过程。
图4A一般地解说了图3的制造过程的一阶段中的示例性组件布置的示意图。
图4B一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4C一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4D一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4E一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4F一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4G一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4H一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4I一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4J一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4K一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4L一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图4M一般地解说了图3的制造过程的另一个阶段中的示例性组件布置的示意图。
图5一般地解说了其中可有利地采用本公开的一方面的示例性无线通信系统的框图。
图6一般地解说了解说用于所公开的半导体IC封装的电路、布局以及逻辑设计的设计工作站的框图。
详细描述
本公开的诸方面在以下针对本公开具体方面的描述和有关附图中被公开。可构想出替换性方面而不背离本发明的范围。另外，本发明中众所周知的元素将不被详细描述或将被省去以免湮没本发明的相关细节。
措辞“示例性”和/或“示例”在本文中用于意指“用作示例、实例或解说”。本文描述为“示例性”和/或“示例”的任何方面不必被解释为优于或胜过其他方面。类似地，术语“本发明的诸方面”并不要求本发明的所有方面都包括所讨论的特征、优点或操作模式。
如本文中所使用的，术语“垂直”一般是针对其上形成半导体封装的基板或载体的表面定义的。该基板或载体将一般地定义“水平”面，而垂直方向接近大致垂直于该水平面的方向。
为了解决常规PoP半导体封装设计的一些缺点，PoP半导体器件的总体高度必须被减小从而使得器件剖面较小。此外，需要新的材料、设计和工艺来防止制造期间薄组件的翘曲。本公开呈现了PoP半导体封装中的组件的各种布置。本公开还呈现了用于制造PoP半导体封装的各种方法。
在常规设计中，放置在第一封装和第二封装之间的焊球(例如，图1中所示的焊球160)容易增加PoP半导体封装的总体高度。在本公开的一个方面，第一封装和第二封装在不使用焊球的情况下彼此耦合，由此减小了PoP半导体封装的总体高度。常规设计还利用了随着变薄而易于翘曲的基板(例如，图1中所示的第一基板140)。在本公开的另一方面，为了利于抗翘曲设计而省略了常规基板。
图2一般地解说了根据本发明的一方面的PoP半导体封装200。PoP半导体封装200包括第一半导体封装202和第二半导体封装204。在一个可能的场景中，第一半导体封装202是PoP半导体封装200的PoP结构中的底部封装，而第二半导体封装204是PoP半导体封装200的PoP结构中的顶部封装。
第一半导体封装202包括第一半导体器件220，而第二半导体封装204包括第二半导体器件270。第一半导体器件220和第二半导体器件270各自可以是例如集成电路(IC)、处理器IC、存储器IC、管芯、芯片、片上系统(SoC)、移动站调制解调器TM(MSM-TM)或类似器件。在一个可能的场景中，第一半导体器件220是处理器IC，而第二半导体器件270是存储器IC。
第一半导体封装202进一步包括阳极化金属盖结构210。在图2的解说中，阳极化金属盖结构210包括阳极化层214和金属层216。在一个可能的场景中，阳极化层214覆盖了阳极化金属盖结构210的整个外部表面，而金属层216位于阳极化层214之下。因为阳极化层214是阳极化的，所以它是绝缘的和不导电的。换言之，接触阳极化层214的携带电荷的组件将不会把电荷转移到或转移通过阳极化层214。在阳极化层214覆盖阳极化金属盖结构210的整个外部表面的场景中，将理解阳极化金属盖结构210将不会与毗邻组件或通过毗邻组件来转移电荷。
如上文所提及的，阳极化层214可以是覆盖阳极化金属盖结构210的整个外部表面的薄层。然而，将理解，阳极化层214可以覆盖少于阳极化金属盖结构210的外部表面的整体。此外，将理解阳极化层214可以是相对厚的层，且阳极化层214之下的金属层216可以相比而言相对较薄。在还有另一个可能的场景中，金属层216被整个省略，且阳极化金属盖结构210被整个阳极化。
阳极化金属盖结构210可以用以电隔离、支持、和保护第一半导体器件220。阳极化金属盖结构210是用于电隔离并保护第一半导体封装202的装置的一示例。如将参照图4A-4M更具体地描述的，第一半导体器件220可以位于阳极化金属盖结构210中形成的中央空腔中。第一半导体器件220可以使用第一接合剂222来接合到阳极化金属盖结构210。阳极化金属盖结构210还可以包括形成在阳极化金属盖结构210中的用于通过阳极化金属盖结构210电耦合的通孔238。通孔238可以允许电荷从第二半导体封装204转移到位于阳极化金属盖结构210的相对侧的重分布层240。例如，通孔238可以允许电荷从第一重分布子层230中的导电迹线232转移通过阳极化金属盖结构210并进入焊料材料250，如图2中所解说的。
如图2中所解说的，重分布层240包括三个子层。第一重分布子层230布置成毗邻于阳极化金属盖结构210和第一半导体器件220。第一重分布子层230包括导电迹线232，该导电迹线232可以将一个或多个通孔238电耦合到第一半导体器件220的一个或多个电触点。导电迹线232还可以将多个通孔238彼此电耦合和/或将第一半导体器件220的多个电触点彼此电耦合。导电迹线232还可以形成在毗邻于第一重分布子层230的第二重分布子层234中，以及还可以形成在毗邻于第二重分布子层234的第三重分布子层236中。将理解，重分布层240可包括多于三个子层或少于三个子层，如设计考量所要求的。
重分布层240电耦合到一个或多个焊球242。焊球242可以将PoP半导体封装200耦合到电路板(未示出)，例如，印刷电路板。焊球242可以布置成球栅阵列(BGA)。焊球242在重分布层240和电路板之间转移电荷。如图2中所解说的，焊球242耦合到导电迹线232，该导电迹线232形成在第三重分布子层236中。然而，如上文所提及的，重分布层240可包括多于三个子层或少于三个子层，如设计考量所要求的。焊球242可以形成在电路板所耦合到的重分布层240的任何子层上。在一个可能的场景中，电路板将信号和/或功率递送到至少一个焊球242。重分布层240将信号和/或功率从至少一个焊球242分布到第一半导体器件220和/或一个或多个通孔238。
如上文所提及的，重分布层240将电荷转移通过形成在阳极化金属盖结构210中的通孔238。电荷可以被转移到被包括在第二半导体封装204中的第二封装基板260。第二封装基板260包括经由焊料材料250电耦合到通孔238的一个或多个导电桩262。在制造过程的一个阶段，焊料材料250可包括，例如，焊膏和/或银膏。在一个可能的场景中，导电桩262从第二封装基板260延伸并被插入焊料材料250中。如将在以下参照图4A-4M更详细地描述的，焊料材料250可以填充一个或多个周界空腔的至少一部分。在一个可能的场景中，每个导电桩262被插入到包含焊料材料250的对应周界空腔中。
第二封装基板260可以使用第二接合剂264接合到阳极化金属盖结构210。第二半导体器件270耦合至第二封装基板260。在一个可能的场景中，第二半导体器件270被嵌入在隔离、支持、和/或保护第二半导体器件270的模具中。该模具可以耦合到第二封装基板260和第二半导体器件270。该模具可以是例如模塑底部填料(MUF)或环氧树脂模制复合物(EMC)。在另一可能的场景中，如图2中所示，模具可以被省略。
根据本公开的一方面，阳极化金属盖结构210与常规组件(例如，图1中解说的第一基板140)相比更适合用于隔离、支持、和/或保护第一半导体器件220。根据本公开的另一方面，阳极化金属盖结构210可以比常规组件(例如，图1中解说的第一基板140)更简单地且更可靠地来被制造。根据本公开的还有另一方面，PoP半导体封装200与常规PoP结构(例如，图1中解说的PoP半导体器件封装100)相比具有增加的密度。例如，阳极化金属盖结构210的周界空腔内的焊料材料250的布置，以及从第二封装基板260延伸到焊料材料250中的互补导电桩262的放置可以使得能用在例如大约600μm到800μm的量级的减小的剖面来生产PoP半导体封装200。作为比较，使用常规组件(例如，图1中解说了用以将第一基板140耦合到第二基板180的焊球160)可能导致增加的封装剖面和减小的密度。
图3一般地解说了用于制造半导体封装的示例性方法300。方法300中制造的半导体封装可以类似于图2中公开的PoP半导体封装200。在310，通过例如切割或打孔金属板在金属板中形成了孔洞。在320，金属板被阳极化。在330，在金属板中形成了中央空腔和至少一个周界空腔。中央空腔可以具有与该至少一个周界空腔的周界空腔开口方向相反的中央空腔开口方向。将理解，310、320和330可以按任何次序完成。在完成310、320和330之后，金属板可以被变换成类似于阳极化金属盖结构210的阳极化金属盖结构。
在340，半导体器件被放置到在330形成的中央空腔中。该半导体器件可以类似于第一半导体器件220。在350，在310、320和330处形成的阳极化金属盖结构、以及在340处放置到中央空腔中的半导体器件上形成了重分布层。该重分布层可以类似于图2中解说的重分布层240。在一个可能的示例中，重分布层240形成在图2中解说的阳极化金属盖结构210和第一半导体器件220上。
在360，该至少一个周界空腔被用焊料材料至少部分填充。该焊料材料可以类似于图2中解说的焊料材料250。在370，半导体封装被耦合到阳极化金属盖结构。在一个可能的示例中，半导体封装和阳极化金属盖结构类似于图2中解说的第二半导体封装204和阳极化金属盖结构210。在一个可能的场景中，被包括在半导体封装中的至少一个导电桩被插入到焊料材料250(例如，图2中解说的350)中。
图4A到4M一般地解说了制造过程中各个阶段的组件的布置。该制造过程可以被用来制造图2中解说的PoP半导体封装200。图4A-4M中解说的制造过程的各个阶段可以对应于图3中解说的示例性方法300中描绘的一个或多个框。
图4A一般地解说了第一阶段405处的组件布置。在第一阶段405，阳极化金属盖结构210起始为金属平板片。图4A示出了金属平板片的横截面。该金属平板片的大小、形状和比例可以根据设计考量按需修改。
图4B一般地解说了第二阶段410处的组件布置。在第二阶段410，在来自第一阶段405的金属平板片中形成了孔洞212。孔洞212的大小、形状和比例可以根据设计考量按需修改。在图2的设计中，例如，孔洞212具备合适的大小、形状和比例来容适通孔238，这些通孔238是阳极化金属盖结构210的恰当利用所必要的。孔洞212可以通过切割、打孔或任何其他合适的过程来形成。
图4C一般地解说了第三阶段415处的组件布置。在第三阶段415，来自第二阶段410的金属平板片被阳极化。作为阳极化的结果，在阳极化金属盖结构210的外表面上形成了阳极化层214。阳极化金属盖结构210的未曝露部分可以不被阳极化。作为结果，金属层216可以保持在阳极化层214的表面之下。因为阳极化金属盖结构210是由金属制成的，所以它可以贯穿图4A-4M中解说的每个阶段抗翘曲。阳极化金属盖结构210还可以更适合于支持并保护其他组件(例如，第一半导体器件220)。因为阳极化层214是阳极化的，所以阳极化金属盖结构210将不会导电。阳极化金属盖结构210将因此仍然适合用于毗邻组件的电隔离。阳极化金属盖结构210可包括任何合适的材料，例如，铜、铝、包括铜和/或铝的合金，等等。
图4D一般地解说了第四阶段420处的组件布置。在第四阶段420，阳极化金属盖结构210被塑形以形成至少一个周界空腔218和至少一个中央空腔219。在图4D中，示出了两个周界空腔218和一个中央空腔219，但是将会领会可以包括任何数目的周界空腔218和任何数目的中央空腔219。在一个可能的场景中，每个周界空腔218对应于个体孔洞212。
如图4D中所示，中央空腔219被形成使得中央空腔219具有面向下的开口方向。(将理解，“向下”和“向上”是解说性术语，且在所公开的过程中，根据制造考量，开口方向可包括任何合适的方向。)周界空腔218被形成为具有面向上的开口方向，即，沿与中央空腔219的开口方向相反的方向。
将理解，各个周界空腔218和中央空腔219可以具有任何三维形状，例如，圆柱体、立方体、长方体等。例如，在图2中解说的设计中，中央空腔219可以被设计成容适具有平坦的六面长方体结构的第一半导体器件220，其中第一半导体器件220的高度相对于长度和宽度而言较小。(将理解，“长度”、“宽度”和“高度”是解说性术语，以及出于解说的目的，“高度”对应于“向上”和“向下”的方面，如图4D中所解说的。)根据该示例，中央空腔219可以被设计成使得其对应于平坦的六面第一半导体器件220。在一个可能的场景中，中央空腔219具有五面——对应于第一半导体器件220的宽度和长度的第一面，以及从第一面向下方向延伸的四面。根据该示例，中央空腔219的缺失的第六面(图4D中面向下)将对应于中央空腔219的开口方向。
在图2中解说的设计的另一示例中，周界空腔218可以被设计成容适导电桩262和特定体积的焊料材料250。例如，在图2中解说的设计中，周界空腔218可以设计成容适具有圆柱体结构的导电桩262，其中导电桩262的高度相对于半径而言较大。根据该示例，周界空腔218可以被设计成对应于圆柱体导电桩262。在一个可能的场景中，周界空腔218具有其中形成了孔洞212的基座和对应于周界空腔218的开口方向的缺失的顶部。周界空腔的体积可能足以容适导电桩262和预定体积的焊料材料250。
在其他可能的场景中，中央空腔219可以设计成除了互补器件之外容适第一半导体器件220。附加地或替换地，可以形成多个中央空腔，每个中央空腔容适一个或多个器件。此外，周界空腔218可以设计成容适多个导电桩262和/或其他组件。
任何合适的过程可以被用来形成阳极化金属盖结构210中的一个或多个周界空腔218和一个或多个中央空腔219。例如，阳极化金属盖结构210可以被折叠、弯曲、穿孔，或抵压在模具上。
将理解，图4D中解说的阳极化金属盖结构210可以由根据本公开的诸方面的任何合适的过程来形成。阳极化金属盖结构210可以通过首先形成孔洞212，通过接着阳极化该金属来形成阳极化层214，以及通过最后形成周界空腔218和中央空腔219来形成。图4B到4D解说了这些事项的特定次序。然而，将理解，阳极化金属盖结构210的阳极化可以在形成孔洞之前执行，或替换地，在形成空腔之后执行。在另一可能的场景中，周界空腔218和中央空腔219通过相异的操作来形成。在还有另一可能的场景中，孔洞212、周界空腔218和中央空腔219各自在阳极化之前、之后和/或与之同时用单个操作形成，
图4E一般地解说了第五阶段425处的组件布置。在第五阶段425，第一接合剂222被提供给阳极化金属盖结构210的中央空腔219。虽然图4E示出了处于“翻转”状态的阳极化金属盖结构210，使得中央空腔219的开口方向是向上的方向，但将理解，图4A-4M中的各组件的取向仅出于解说性目的而示出。
图4F一般地解说了第六阶段430处的组件布置。在第六阶段430，半导体器件(例如，第一半导体器件220)被置于形成在第四阶段420中的中央空腔219内。在一个可能的场景中，图4F中示出的组件的布置包括半导体封装，例如，图2中解说的第一半导体封装202。第一半导体器件220具有于其上形成的电触点224。在放置了第一半导体器件220之后，第一半导体器件220的其上形成电触点224的那面对应于中央空腔219的开口方向。第五阶段425中提供到中央空腔219的第一接合剂222被用来将第一半导体器件220接合到阳极化金属盖结构210。在本公开的另一方面，第一接合剂222被省略，且第一半导体220被压合到中央空腔219。第一接合剂222可包括任何合适的材料，例如，粘合剂、树脂、模具，等等。
图4G一般地解说了第七阶段435处的组件布置。在第七阶段435，重分布层的第一子层(例如，图2中解说的重分布层240的第一重分布子层230)形成在电触点224和孔洞212之上。
图4H一般地解说了第八阶段440处的组件布置。在第八阶段440，重分布层(例如，图2中解说的重分布层240)从第一重分布子层230形成。一旦第七阶段435中第一重分布子层230被形成在电触点224和孔洞212之上，导电迹线232就被形成在第一重分布子层230中。导电迹线232可以使用任何合适的技术(例如，光刻技术)来形成。导电迹线232可包括通过用导电材料至少部分填充孔洞212形成的通孔238。替换地，导电迹线232和通孔238可以在分开的阶段中形成。一个或多个导电迹线232和/或通孔238可以向至少一个周界空腔218曝露。形成导电迹线232和/或通孔238的导电材料可以整体或部分填充一个或多个孔洞212。替换地，导电迹线232和/或通孔238可以驻留在该一个或多个孔洞212之外。
重分布层240的剩余层(例如，第二重分布子层234和第三重分布子层236)可以使用类似的技术来制造。根据设计考量，导电迹线232可以具有延伸通过重分布层240的每个子层的分支。重分布层240是用于重分布电信号的装置的一示例。
图4I一般地解说了第九阶段445处的组件布置。第九阶段445的组件的布置与图4H中所示的布置相同，除了组件被解说为处于“翻转”状态，从而周界空腔218的开口方向为向上的方向。将理解，图4A-4M中的各组件的取向仅出于解说的目的而示出。
图4J一般地解说了第十阶段450处的组件布置。在第十阶段450，在重分布层240上形成了一个或多个焊球(例如，图2中解说的焊球242)。焊球242可以促成PoP半导体封装200到例如电路板(未示出)的耦合。
图4K一般地解说了第十一阶段455处的组件布置。在第十一阶段455，至少一个周界空腔218被用焊料材料(例如，图2中解说的焊料材料250)来至少部分填充。在第十一阶段455填充至少一个周界空腔218之际，焊料材料250将被电耦合到导电迹线232和/或通孔238。焊料材料250可以整体或部分填充该一个或多个孔洞212。替换地，焊料材料250可以驻留在该一个或多个孔洞212之外。焊料材料250是第一用于耦合的装置的示例。
图4L一般地解说了第十二阶段460处的组件布置。在第十二阶段460，接合剂(例如，图2中解说的第二接合剂264)被提供到阳极化金属盖结构210的表面。第二接合剂264被用来将第一半导体封装202接合到另一半导体封装，例如，图2中解说的第二半导体封装204。具体而言，第二接合剂264将阳极化金属盖结构210的表面接合到被包括在第二半导体封装204中的基板(例如，第二封装基板260)的表面。第二封装基板260支持半导体管芯，例如，图2中解说的第二半导体器件270。第二封装基板260还包括其上形成的导电桩262。在一个可能的场景中，导电桩262从第二封装基板260的底面向下延伸。导电桩262是第二用于耦合的装置的示例。
图4M一般地解说了第十三阶段465处的组件布置。在第十三阶段465，第二半导体封装204根据任何合适的工艺(例如，压缩或压合)被耦合到第一半导体封装202在一个可能的场景中，每个形成在第二半导体封装204上的导电桩262对应于至少部分被用焊料材料250填充的孔洞218。
图5是示出其中可有利地采用本公开的一方面的示例性无线通信系统500的框图。出于解说目的，图5示出了三个远程单元520、530和550以及两个基站540。将认识到，无线通信系统可具有多得多的远程单元和基站。如以下所公开的，远程单元520、530和550包括IC器件525、535和555。将认识到，包含IC的任何设备也可包括具有所公开的特征的半导体组件和/或由本文所公开的过程制造的组件，包括基站、交换设备以及网络装备。图5示出了从基站540到远程单元520、530和550的前向链路信号580，以及从远程单元520、530和550到基站540的反向链路信号590。
在图5中，远程单元520被示为移动电话，远程单元530被示为便携式计算机，而远程单元550被示为无线本地环路系统中的固定位置远程单元。例如，这些远程单元可以是诸如音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、位置固定的数据单元、以及计算机的设备。尽管图5解说了根据本公开的教导的远程单元，但本公开并不限于这些所解说的示例性单元。如下文所描述的，在包括半导体组件的任何设备中可以合适地采用本公开。
本文中公开的半导体封装(例如，半导体封装PoP半导体封装200等)可被包括在一设备中，诸如机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、固定位置数据单元或计算机。
图6是解说如本文中公开的用于半导体部件的电路、布局以及设计的设计工作站的框图。设计工作站600可包括硬盘601，该硬盘601包含操作系统软件、支持文件、以及设计软件(诸如Cadence或OrCAD)。该设计工作站600还包括显示器以促成可包括电路和半导体管芯的半导体部件610的设计。提供存储介质604以用于有形地存储半导体部件610。半导体部件610可以文件格式(诸如GDSII或GERBER)存储在存储介质604上。存储介质604可以是CD-ROM、DVD、硬盘、闪存、或其他合适的设备。此外，设计工作站600包括用于从存储介质604接受输入或者将输出写到存储介质604的驱动装置603。
存储介质604上记录的数据可指定逻辑电路配置、用于光刻掩模的图案数据、或用于串写工具(诸如电子束光刻)的掩模图案数据。在存储介质604上提供数据通过减少用于设计电路和半导体管芯的工艺的数目促成了半导体部件610的设计。
以上描述可能参照分立的元件或属性，诸如电容器、电容性、电阻器、电阻性、电感器、电感性、导体、导电性以及类似的。然而，将领会本文中公开的各方面不限于特定元件，并且各种各样的组件、元件或者组件或元件的部分可以被用来达成一个或多个分立元件或属性的功能性。例如，电容性组件或电容性元件可以是分立的器件并可以由被介电材料分隔的导电迹线的特定布置来形成，或者是其组合。类似地，电感性组件或电感性元件可以是分立的器件或者可以由导电迹线和材料(例如，无芯线圈、磁性的、顺磁性的等)的特定布置来形成，或者是其组合。类似地，电阻性组件或电阻性元件可以是分立的器件或者可以由半导体材料、绝缘材料、调节导电迹线的长度和/或横截面积来形成，或者是其组合。此外，导电迹线和材料的特定布置可以提供一个或多个电阻性、电容性或电感性功能。相应地，将领会，本文中公开的各组件或元件并不限于特定方面和/或详细布置，这些方面和/或布置是仅作为解说性示例而提供的。
尽管前面的公开示出了本公开的解说性方面，但是应当注意，在其中可作出各种变更和修改而不会脱离如所附权利要求定义的本发明的范围。根据本文所描述的本公开的各方面的方法权利要求中的功能、步骤和/或动作不必按任何特定次序来执行。此外，尽管本公开的要素可能是以单数来描述或主张权利的，但是复数也是已料想了的，除非显式地声明了限定于单数。

Claims (19)

1.一种层叠封装半导体器件，包括：
第一半导体封装，所述第一半导体封装包括：
阳极化金属盖结构，其包括(i)具有中央空腔开口方向的中央空腔和(ii)具有面对与所述中央空腔开口方向相反的方向的周界空腔开口方向的至少一个周界空腔；
布置在所述阳极化金属盖结构的所述中央空腔中的第一半导体器件；
电耦合到所述第一半导体器件的重分布层，其中形成在所述重分布层中的导电迹线向所述至少一个周界空腔曝露；以及
布置在所述至少一个周界空腔中的焊料材料；以及
第二半导体封装，所述第二半导体封装包括至少一个导电桩，其中所述至少一个导电桩电耦合到布置在所述至少一个周界空腔中的所述焊料材料。
2.如权利要求1所述的层叠封装半导体器件，其特征在于，所述阳极化金属盖结构进一步包括配置成容适电荷从形成在所述重分布层中的所述导电迹线向所述焊料材料的转移的孔洞。
3.如权利要求1所述的层叠封装半导体器件，其特征在于，所述第一半导体器件用第一接合剂接合到所述中央空腔的表面。
4.如权利要求1所述的半导体器件，其特征在于，所述重分布层是光刻重分布层。
5.如权利要求1所述的层叠封装半导体器件，其特征在于，进一步包括焊球，所述焊球在所述重分布层的与所述半导体器件被耦合到的所述重分布层的那侧相反的一侧上被耦合到所述重分布层。
6.如权利要求1所述的层叠封装半导体器件，其特征在于，所述第二半导体封装是用第二接合剂来接合到所述第一半导体封装的。
7.如权利要求6所述的层叠封装半导体器件，其特征在于，所述第二半导体封装被压缩接合到所述第一半导体封装。
8.如权利要求6所述的层叠封装半导体器件，其特征在于，所述第二半导体封装的第二半导体器件经由所述至少一个导电桩和所述焊料材料被电耦合到所述第一半导体封装的所述第一半导体器件。
9.如权利要求1所述的层叠封装半导体器件，其特征在于，所述层叠封装半导体具有600μm到800μm的高度。
10.一种包括如权利要求1所述的层叠封装半导体器件的设备，所述设备选自包括机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理、固定位置数据单元和计算机的组。
11.一种制造层叠封装半导体器件的方法，包括：
形成阳极化金属盖结构，其中形成所述阳极化金属盖结构包括：
在所述阳极化金属盖结构中定义具有中央空腔开口方向的中央空腔；以及
在所述阳极化金属盖结构中定义具有周界空腔开口方向的至少一个周界空腔，其中所述周界空腔开口方向面向与所述中央空腔开口方向相反的方向；
将第一半导体器件放置在所述阳极化金属盖结构的所述中央空腔中；
提供第一半导体封装，其中提供所述第一半导体封装包括将所述第一半导体器件电耦合到重分布层，以及形成在所述重分布层中形成的导电迹线，从而所述导电迹线向所述至少一个周界空腔曝露；
用焊料材料填充所述至少一个周界空腔的至少一部分；以及
通过将至少一个导电桩耦合到所述焊料材料来将具有所述至少一个导电桩的第二半导体封装耦合到所述第一半导体封装。
12.如权利要求11所述的方法，其特征在于，形成所述阳极化金属盖结构进一步包括：
在金属板中形成孔洞；以及
阳极化所述金属板。
13.如权利要求11所述的方法，其特征在于，将所述第一半导体器件放置到所述中央空腔中包括用第一接合剂将所述第一半导体器件接合到所述中央空腔。
14.如权利要求11所述的方法，其特征在于，将所述第一半导体器件耦合到所述重分布层包括使用光刻技术形成所述重分布层。
15.如权利要求11所述的方法，其特征在于，进一步包括将焊球在所述重分布层的与所述半导体器件被耦合到的所述重分布层的那侧相反的一侧上耦合到所述重分布层。
16.如权利要求11所述的方法，其特征在于，耦合所述第二半导体封装进一步包括将所述第二半导体封装接合到所述第一半导体封装。
17.如权利要求16所述的方法，其特征在于，将所述第二半导体封装接合到所述第一半导体封装包括压缩接合。
18.如权利要求16所述的方法，其特征在于，将所述至少一个导电桩耦合到所述焊料材料包括将所述第二半导体封装的第二半导体器件电耦合到所述第一半导体封装的所述第一半导体器件。
19.如权利要求11所述的方法，其特征在于，制造所述层叠封装半导体器件包括制造具有600μm到800μm的高度的层叠封装半导体。
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