CN107104056A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN107104056A CN107104056A CN201610989359.5A CN201610989359A CN107104056A CN 107104056 A CN107104056 A CN 107104056A CN 201610989359 A CN201610989359 A CN 201610989359A CN 107104056 A CN107104056 A CN 107104056A
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- scolding tin
- component
- heat treatment
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- films
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Abstract
本发明提供一种半导体装置的制造方法,其目的在于,在相互被焊接的两个部件的各Ni膜上生成预先设定的量的(Cu,Ni)6Sn5。本发明的半导体装置的制造方法包括第一热处理工序、第二热处理工序和第三热处理工序。在第一热处理工序中,使含有重量百分比0.9%以上的Cu的第一Sn‑Cu系焊锡在被形成于第一部件上的Ni膜上熔融,从而在第一部件的Ni膜上生成(Cu,Ni)6Sn5。在第二热处理工序中,使含有重量百分比0.9%以上的Cu的第二Sn‑Cu系焊锡在被形成于第二部件上的Ni膜上熔融,从而在第二部件的Ni膜上生成(Cu,Ni)6Sn5。而且,在第三热处理工序中,使第一热处理工序后的第一Sn‑Cu系焊锡与第二热处理工序后的第二Sn‑Cu系焊锡熔融而一体化,从而使第一部件与第二部件相互接合。
Description
技术领域
本说明书中公开的技术涉及一种半导体装置的制造方法。
背景技术
在半导体装置中,例如半导体元件与引线框之类的两个以上的部件通过焊锡而被接合。在通过焊锡而对两个部件进行接合的情况下,广泛地实施在各个部件的表面上设置镀Ni(镍)层之类的Ni膜的措施,以防止接合界面上的金属间化合物的过度的生长。然而,当该Ni膜长时间经历达到200℃那样的高温时,存在与焊锡之间生成金属间化合物(例如Ni3Sn4)的情况。在该情况下,有可能产生接合强度降低之类的问题。
关于上述的问题,在日本专利文献1中记载有使用含有Cu6Sn5的Sn-Cu系焊锡的半导体装置的制造方法。该制造方法包括在两个部件之间配置Sn-Cu系焊锡的工序和对Sn-Cu系焊锡进行加热而使之熔融从而在各个部件的Ni膜上生成(Cu,Ni)6Sn5的工序。根据该制造方法,生成在Ni膜上的(Cu,Ni)6Sn5作为对Ni膜的金属间化合物化进行抑制的阻挡层而发挥功能,从而能够防止焊锡与Ni膜之间的接合界面的接合强度的降低。
在先技术文献
专利文献
专利文献1:日本特开2007-67158号公报
发明内容
发明所要解决的课题
在专利文献1所记载的制造方法中,通过使焊锡在两个部件之间熔融,从而使(Cu,Ni)6Sn5同时生成在两个部件的各Ni膜上。在该情况下,在焊锡于两个部件之间熔融的期间,焊锡中所含有的Cu6Sn5的一部分向一方的部件移动而生成(Cu,Ni)6Sn5,另外一部分向另一方的部件移动而生成(Cu,Ni)6Sn5。在此,难以对位于两个部件之间的焊锡均匀地进行加热,例如,加热过程中的焊锡的温度分布有可能在其厚度方向上变得不均匀。这时,存在如下情况,即,在与一方的部件接触的范围内,焊锡的温度上升较快从而焊锡在早期便熔融,另一方面,在与另一方的部件接触的范围内,焊锡的温度上升较慢从而焊锡较迟地熔融的情况。在该情况下,在一方的部件中先开始(Cu,Ni)6Sn5的生成,在另一方的部件中较迟地开始(Cu,Ni)6Sn5的生成。其结果为,存在如下情况,即,焊锡所含有的Cu6Sn5的大部分在一方的部件中被消耗,从而无法在另一方的部件上生成预先设定的量的(Cu,Ni)6Sn5的情况。
关于上述的问题,例如考虑到将使用的Sn-Cu系焊锡的Cu浓度设为较高。当Cu浓度变高时,焊锡中所包含的Cu6Sn5的量也增多。而且,当在焊锡中丰富地含有Cu6Sn5时,即使在两个部件之间不均匀地生成有(Cu,Ni)6Sn5的情况下,也能够在两个部件的各个表面上生成所需的(Cu,Ni)6Sn5。然而,在Sn-Cu系焊锡中,Cu浓度越高,熔融温度(液相温度)也越高(参照图22)。因此,当将使用的Sn-Cu系焊锡的Cu浓度设为较高时,需要在使焊锡熔融的工序中将焊锡加热至更高的温度。例如,在专利文献1记载的制造方法中,使用了含有重量百分比3~7%的Cu的Sn-Cu系焊锡,其熔融温度达到约330℃~400℃。
鉴于以上的实际情况,本说明书提供一种如下的技术,即,在使用Sn-Cu系焊锡而使两个以上的部件被接合在一起的制造半导体装置的方法中,即使在使用了Cu浓度比较低的Sn-Cu系焊锡的情况下,也能够在各个部件的Ni膜上生成预先设定的量的(Cu,Ni)6Sn5。
用于解决课题的方法
本说明书公开了一种半导体装置的制造方法,所述半导体装置具有第一部件和被接合在第一部件上的第二部件。该制造方法包括第一热处理工序、第二热处理工序和第三热处理工序。在第一热处理工序中,使含有重量百分比0.9%以上的Cu的第一Sn-Cu系焊锡在被形成于第一部件上的Ni膜上熔融,从而在第一部件的Ni膜上生成(Cu,Ni)6Sn5。在第二热处理工序中,使含有重量百分比0.9%以上的Cu的第二Sn-Cu系焊锡在被形成于第二部件上的Ni膜上熔融,从而在第二部件的Ni膜上生成(Cu,Ni)6Sn5。而且,在第三热处理工序中,使第一热处理工序后的第一Sn-Cu系焊锡与第二热处理工序后的第二Sn-Cu系焊锡熔融而一体化,从而使第一部件与第二部件相互接合。第一热处理工序与第二热处理工序既可以同时实施,也可以在不同的时刻实施。第一热处理工序与第二热处理工序的顺序也不被特别地限定。此外,Ni膜并不限定于纯Ni的膜,也包括添加有P(磷)等其他的元素的Ni膜。
在上述的制造方法中,能够在将第一部件与第二部件组合之前,对第一部件实施第一热处理工序,且对第二部件实施第二热处理工序。在第一热处理工序中,使用第一Sn-Cu系焊锡而在第一部件的Ni膜上生成(Cu,Ni)6Sn5。在第二热处理工序中,使用与第一Sn-Cu系焊锡不同的第二Sn-Cu系焊锡而在第二部件的Ni膜上生成(Cu,Ni)6Sn5。由于不像专利文献1中所记载的制造方法那样,将一个焊锡中所含有的Cu6Sn5分给两个部件,因此即使在第一及第二Sn-Cu系焊锡的Cu浓度比较低的情况下,也能够在第一部件及第二部件的各Ni膜上生成预先设定的量的(Cu,Ni)6Sn5。在此,当第一Sn-Cu系焊锡的Cu浓度在重量百分比0.9%以上时,能够在第一部件的Ni膜上生成可作为阻挡层而发挥功能的量的(Cu,Ni)6Sn5。对于第二Sn-Cu系焊锡也同样如此。在第一热处理工序及第二热处理工序之后,通过将第一部件与第二部件组合并实施第三热处理工序,从而能够使第一部件与第二部件相互接合。
附图说明
图1为表示焊接方法的一个工序的图,且表示配置有第一焊锡14的第一部件10与配置有第二焊锡24的第二部件20。
图2为表示焊接方法的一个工序的图,且表示第一热处理工序后的第一部件10与第二热处理工序后的第二部件20。
图3为表示焊接方法的一个工序的图,且表示将第一热处理工序后的第一部件10与第二热处理工序后的第二部件20组合在一起的状态。
图4为表示焊接方法的一个工序的图,且表示第三热处理工序后的第一部件10以及第二部件20。
图5(A)~图5(E)为对焊接后(第三热处理工序后)的Ni膜12(Ni-P)与焊锡接合层30之间的接合界面进行拍摄所得到的电子显微镜照片。
图6(A)~图6(E)为对焊接后(第三热处理工序后)的Ni膜12(Ni)与焊锡接合层30之间的接合界面进行拍摄所得到的电子显微镜照片。
图7为表示使第一焊锡14以及第二焊锡24的Cu浓度发生变化而实施的焊接的结果的表。
图8为表示在第一焊锡14以及第二焊锡24的每个Cu浓度下,在高温耐久试验中所测量到的富P层的生长的图表。
图9(A)~图9(E)为在500小时的高温耐久试验后对Ni膜12(Ni-P)与焊锡接合层30之间的接合界面进行拍摄所得到的电子显微镜照片。图9(A)~(E)表示将第一及第二焊锡14、24的Cu浓度分别设为重量百分比0.7%、重量百分比0.9%、重量百分比1.4%、重量百分比1.5%、重量百分比1.6%的情况。
图10(A)~图10(E)为在高温耐久试验后对Ni膜12(Ni-P)与焊锡接合层30之间的接合界面进行拍摄所得到的电子显微镜照片。图10(A)为将Cu浓度设为重量百分比0.7%并实施了250小时的高温耐久试验的情况,图10(B)为将Cu浓度设为重量百分比0.9%并实施了250小时的高温耐久试验的情况,图10(C)为将Cu浓度设为重量百分比1.4%并实施了500小时的高温耐久试验的情况,图10(D)为将Cu浓度设为重量百分比1.5%并实施了500小时的高温耐久试验的情况,图10(E)为将Cu浓度设为重量百分比1.6%并实施了1000小时的高温耐久试验的情况。
图11为示意性地表示半导体装置50的立体图。
图12为示意性地表示半导体装置50的结构的分解图。另外,树脂封装件60被省略图示。
图13为表示半导体装置50的电结构的电路图。
图14为图11的XIV-XIV线处的剖视图。
图15为图14的XV部的放大图。
图16为表示半导体装置50的制造方法的一个工序的图,且表示第一热处理工序或第二热处理工序后的各个部件。
图17为表示半导体装置50的制造方法的一个工序的图,且表示组合有一部分部件的半成品。
图18为表示半导体装置50的制造方法的一个工序的图,且表示第三热处理工序后的半成品。
图19为表示半导体装置50的制造方法的一个工序的图,且表示进一步组合有其他部件的半成品。
图20为表示半导体装置50的制造方法的一个工序的图,且表示第二次的第三热处理工序后的半成品。
图21为表示半导体装置50的制造方法的一个工序的图,且表示形成有树脂封装件60的半导体装置50。
图22为表示Sn-Cu系焊锡的状态图(相图)。
具体实施方式
实施例
首先,对本说明书中公开的焊接方法进行说明。在该焊接方法中,如图1至图4所示,使用第一焊锡14与第二焊锡24而将第一部件10与第二部件20相互接合。该焊接方法可应用于各种工业产品的制造中。因此,第一部件10以及第二部件20并不限定于特定的部件。例如,第一部件10以及第二部件20为构成半导体装置的多个部件中的两个。在该情况下,本说明书中公开的焊接方法能够应用于半导体元件与导电部件(例如引线框)之间的焊接、导电部件与导电部件之间的焊接以及半导体元件与半导体元件之间的焊接中的任意焊接中。
首先,如图1所示,在第一部件10的表面10a上配置第一焊锡14,并在第二部件20的表面20a上配置第二焊锡24。在第一部件10的表面10a上形成有Ni膜12。此处,Ni膜是指将Ni(镍)作为主要成分的金属层,例如可以为无电解镀Ni-P层或电解镀Ni层。Ni膜12是为了对第一部件10与第一焊锡14之间的接合界面处的金属化合物的过多的生成进行抑制而被设置的。Ni膜12的初始厚度D0未被特别地限定,例如能够设为几μm至几百μm。同样地,在第二部件20的表面20a上也形成有Ni膜22。另外,Ni膜12、22也可以通过Au(金)或Ag(银)之类的其他的金属膜而被覆盖以防止Ni膜12、22的腐蚀。这样的金属膜在之后的第一热处理工序或第二热处理工序中,会在焊锡14、24熔融的期间内向该焊锡14、24中扩散。
第一焊锡14以及第二焊锡24分别为在Sn(锡)中添加有Cu(铜)的Sn-Cu系焊锡,并含有作为Cu与Sn的金属间化合物的Cu6Sn5(符号16、26)。虽然详细内容将在后文叙述,但优选为各个焊锡14、24含有重量百分比0.9%以上的Cu。各个焊锡14、24可以为各种形态,可以为薄片状、丝线状、膏状。此外,在第一焊锡14与第二焊锡24之间Cu浓度既可以相同,也可以不同。
接着,如图2所示,实施对被配置在第一部件10上的第一焊锡14进行加热的第一热处理工序和对被配置在第二部件20上的第二焊锡24进行加热的第二热处理工序。第一热处理工序与第二热处理工序既可以被同时实施,也可以在不同的时刻被实施。此外,第一热处理工序与第二热处理工序还可以单独地在物理上分离的位置处被实施。在第一热处理工序中,通过对第一焊锡14进行加热,从而使第一焊锡14在第一部件10的Ni膜12上熔融。即,在第一热处理工序中,将第一焊锡14加热至其熔融温度(液相点)以上。此处,如从图22所示的相图所理解的那样,Sn-Cu系焊锡的熔融温度根据Sn-Cu系焊锡中所包含的Cu浓度而变化,Cu浓度越高,熔融温度也越高。例如,在Cu浓度为重量百分比0.9%的情况下,Sn-Cu系焊锡的熔融温度成为230℃~235℃。关于这一点,第一焊锡14的Cu浓度优选为较低。对于后述的第二焊锡24也同样如此。
当第一焊锡14熔融时,第一焊锡14中所含有的Cu6Sn5会向Ni膜12上移动而生成(Cu,Ni)6Sn5(符号18)。由此,第一部件10与第一焊锡14被牢固地连接。(Cu,Ni)6Sn5通过对Ni膜12进行覆盖,从而作为对Ni3Sn4的生成进行抑制的阻挡层而发挥功能。在第一热处理工序中,将第一焊锡14维持在熔融的状态的熔融时间例如可以设为3分钟~10分钟。但是,该熔融时间并不限定于3分钟~10分钟,能够考虑生成预先设定的量(Cu,Ni)6Sn5所需的时间而适当地进行设定。另外,生成在Ni膜12上的(Cu,Ni)6Sn5的量根据第一焊锡14的Cu浓度而变化,并且Cu浓度越高,(Cu,Ni)6Sn5的生成量越多。关于这一点,第一焊锡14的Cu浓度优选为较高。对于后述的第二焊锡24也同样如此。
同样地,在第二热处理工序中,通过对第二焊锡24进行加热,从而使第二焊锡24在第二部件20的Ni膜22上熔融。即,在第二热处理工序中,将第二焊锡24加热至其熔融温度(液相点)以上。当第二焊锡24熔融时,第二焊锡24中所含有的Cu6Sn5会向Ni膜22上移动而生成(Cu,Ni)6Sn5(符号28)。(Cu,Ni)6Sn5也通过对Ni膜22进行覆盖,从而作为对Ni3Sn4的生成进行抑制的阻挡层而发挥功能。在第二热处理工序中,将第二焊锡24维持在熔融的状态的熔融时间例如也可以设定为3分钟~10分钟。但是,对于该熔融时间,也能够考虑生成预先设定的量的(Cu,Ni)6Sn5所需的时间而适当地进行设定。第二热处理工序中的熔融时间既可以与第一热处理工序中的熔融时间相同,也可以不同。另外,即使在第一部件10的Ni膜12或第二部件20的Ni膜22被Au或Ag之类的其他的金属膜覆盖的情况下,也由于这样的金属膜在焊锡14、24熔融的期间内会扩散到焊锡14、24中,因此同样会在Ni膜12、22上生成(Cu,Ni)6Sn5。
接着,如图3所示,以使第一焊锡14与第二焊锡24相对的方式对第一部件10与第二部件20进行组合。这时,既可以使第一焊锡14与第二焊锡24直接接触,也可以使其他焊锡或其他部件介于第一焊锡14与第二焊锡24之间。
接着,如图4所示,实施对第一焊锡14以及第二焊锡24进行加热的第三热处理工序。在第三热处理工序中,使第一热处理工序后的第一焊锡14与第二热处理工序后的第二焊锡24熔融而一体化。之后,当第一焊锡14以及第二焊锡24凝固时,会在第一部件10与所述第二部件20之间形成有两个焊锡14、24成为一体而得到的焊锡接合层30,从而第一部件10与第二部件20被相互接合在一起。在第三热处理工序中,各个焊锡14、24哪怕熔融较短时间,也能够使两者一体化。因此,在第三热处理工序中,可以将熔融时间设为例如几秒,该熔融时间为将焊锡14、24维持在熔融的状态的时间。因此,虽然能够考虑各种条件而对第三热处理工序中的熔融时间进行适当地设定,但是可以设为短于第一热处理工序以及第二热处理工序中的各熔融时间。
在上述的焊接方法中,在对第一部件10与第二部件20进行组合之前,对第一部件10实施第一热处理工序,且对第二部件实施第二热处理工序。在第一热处理工序中,使用第一焊锡14而在第一部件10的Ni膜12上生成(Cu,Ni)6Sn5。在第二热处理工序中,使用与第一焊锡14不同的第二焊锡24而在第二部件20的Ni膜22上生成(Cu,Ni)6Sn5。与此相对,在现有的焊接方法中,通过使共用的焊锡在两个部件之间熔融,从而在两个部件的各Ni膜上同时生成(Cu,Ni)6Sn5。在使用这种方法时,存在如下情况,即,将焊锡中所含有的Cu6Sn5分给两个部件,当在一方的部件中过度地生成(Cu,Ni)6Sn5时,在另一方的部件中将无法充分地形成(Cu,Ni)6Sn5。与此相对,根据本说明书中公开的焊接方法,不将一个焊锡中所含有的Cu6Sn5分给第一部件10以及第二部件20。因此,即使在第一焊锡14以及第二焊锡24的Cu浓度比较低的情况下,也能够在第一部件10以及第二部件20的各Ni膜12、22上生成预先设定的量的(Cu,Ni)6Sn5。当将第一焊锡14以及第二焊锡24的Cu浓度设为较低时,第一焊锡14以及第二焊锡24的各熔融温度将降低(参照图22)。因此,能够分别将在第一热处理工序中对第一焊锡14进行加热的目标温度以及在第二热处理工序中对第二焊锡24进行加热的目标温度设为较低。如果将这两个目标温度设为较低,则能够例如抑制各个热处理工序中所需的能量消耗量。或者,能够避免对与第一焊锡14或第二焊锡24一同被加热的各种部件的负面影响。
接着,对第一焊锡14以及第二焊锡24的Cu浓度进行研究。如前文所述,将第一焊锡14的Cu浓度设为越高,在Ni膜12上会生成越多的(Cu,Ni)6Sn5,从而能够形成越理想的阻挡层。由于对于第二焊锡24也同样如此,因此在以下以第一焊锡14为示例而进行说明。图5为对焊接后的Ni膜12与焊锡接合层30之间的界面进行拍摄所得到的电子显微镜照片。另外,图5(A)~图5(E)的各个照片为,将第一部件10设为Cu且将Ni膜12设为无电解镀Ni-P层的照片。此外,图5(A)~图5(E)表示将第一焊锡14的Cu浓度分别设为重量百分比0.7%、重量百分比1.7%、重量百分比2.7%、重量百分比3.0%、重量百分比3.2%的情况。如图5(A)所示,可确认如下情况,即,在第一焊锡14的Cu浓度为重量百分比0.7%的情况下,(Cu,Ni)6Sn5的生成不充分,从而较广地生成有Ni3SnP。此外,所生成的富P层(生成有Ni3P的层)的厚度D1也较大。此处,富P层的厚度D1与从Ni膜12消耗的Ni的量相关,富P层的厚度D1越大,表示从Ni膜12消耗了越多的Ni。另一方面,如图5(B)~图5(E)所示,当第一焊锡14的Cu浓度在重量百分比1.7%以上时,未确认到Ni3SnP的生成,而确认到充分地生成有(Cu,Ni)6Sn5。此外,还确认到富P层的厚度D1也比较小,从而(Cu,Ni)6Sn5对Ni膜12进行覆盖而作为阻挡层发挥了功能。
图6(A)~图6(E)的各个照片为,与图5(A)~图5(E)所示的照片相比较,将Ni膜12变更为电解镀Ni层的照片。图6(A)~图6(E)表示将第一焊锡14的Cu浓度分别设为重量百分比0.7%、重量百分比1.7%、重量百分比2.7%、重量百分比3.0%、重量百分比3.2%的情况。如图6(A)所示,可确认如下情况,即,在第一焊锡14的Cu浓度为重量百分比0.7%的情况下,(Cu,Ni)6Sn5的生成不充分,从而较广地生成有(Ni,Cu)3Sn4。此外,Ni膜12的厚度D2与初始厚度D0相比较大地减少。即,确认到从Ni膜12消耗了较多的Ni。另一方面,如图6(B)~图6(E)所示,当第一焊锡14的Cu浓度在重量百分比1.7%以上时,未确认到(Ni,Cu)3Sn4的生成,而确认到充分地生成有(Cu,Ni)6Sn5。此外,还确认到Ni膜12的消失量(即,D0与D2之差)也比较小,从而(Cu,Ni)6Sn5对Ni膜12进行覆盖而作为阻挡层发挥了功能。
从上述的实验结果可确认如下内容,即,当第一焊锡14以及第二焊锡24的Cu浓度在重量百分比1.7%以上时,在各个Ni膜12、22上生成有可作为阻挡层而发挥功能的量的(Cu,Ni)6Sn5。然而,在Cu浓度为重量百分比1.7%的情况下,Sn-Cu系焊锡的熔融温度成为250℃~260℃(参照图22)。如前文所述,在Sn-Cu系焊锡中,Cu浓度越低,熔融温度越低,由此能够使第一热处理工序以及第二热处理工序中的目标加热温度降低。此处,根据图5、图6所示的实验结果可推测出,即使第一焊锡14以及第二焊锡24的Cu浓度小于重量百分比1.7%,也能够在各个Ni膜12、22上生成可作为阻挡层而发挥功能的量的(Cu,Ni)6Sn5。从该观点出发,以下对第一焊锡14以及第二焊锡24的Cu浓度为重量百分比0.7~1.7%的范围的情况进一步进行研究。
图7~图10表示本申请发明人们实施的实验的结果。在该实验中,对于使第一焊锡14以及第二焊锡24的Cu浓度发生变化的各个样品,实施放置在200℃的高温气氛下的高温耐久试验。另外,在该实验中,将Ni膜12、22设为无电解镀Ni-P层,且将第一部件10以及第二部件20设为Cu。此外,对于各个样品的评价,以Cu浓度为重量百分比0.7%的情况为基准而对相对于此的“Ni消失量的多少”以及“(Ni,Cu)3Sn4的生成难易度”进行相对地判断。在图7所示的表中,圆形记号“○”表示与该基准(Ref)相比优异,圆形记号的数量越多,表示越优秀。此处,“焊接”的栏表示在刚焊接后对各个样品进行观察以及测量后的结果,“高温耐久(200℃)”的栏表示在高温耐久试验后对各个样品进行观察以及测量后的结果。图8为表示高温耐久试验中的保持时间(将各个样品放置在200℃的高温气氛下的时间)与所测量出的富P层的厚度D1之间的关系的图表。此处,图7所示的“Ni消失量的多少”基于图8所示的富P层的厚度D1而被评价。
如从图8、图9、图10中所确认的那样,可确认如下的情况,即,在Cu浓度为重量百分比0.7%的样品中,通过500小时的高温耐久试验,Ni膜12几乎完全消失,并且(Ni,Cu)3Sn4的生成显著。与此相对,当Cu浓度在重量百分比0.9%以上时,即使通过500小时的高温耐久试验,也可确认出Ni膜12的残留,并且(Ni,Cu)3Sn4的生成也被抑制。由此可判断出,当第一焊锡14以及第二焊锡24的Cu浓度在重量百分比0.9%以上时,即使在可能经受达到200℃那样的高温的工业产品中,也能够实施在实用方面可耐受的焊接。
另外,根据图8的图表,Cu浓度越高,所生成的富P层的厚度越减少。这表示Cu浓度越高,在Ni膜12、22上会生成越厚的(Cu,Ni)6Sn5,从而由(Cu,Ni)6Sn5实现的阻挡性越优异。尤其可确认如下情况,即,在Cu浓度为重量百分比1.6%的样品中,即使在500小时~1000小时的高温耐久试验中,富P层的生成仍会稳定地被抑制,从而(Cu,Ni)6Sn5的层具有特别优异的阻挡性。由此,可判断出第一焊锡14以及第二焊锡24的Cu浓度更优选在重量百分比1.6%以上。
本说明书中公开的焊接方法能够应用于需要焊接的各种工业产品的制造中。在以下,作为一个示例而对应用了本说明书中公开的焊接方法的半导体装置50的制造方法进行说明。首先,参照图11~图15而对半导体装置50的结构进行说明。该半导体装置50为,在电动汽车(包括混合动力汽车以及燃料电池汽车)中被用于向电动机供给电力的路径中的功率模块。
如图11~图13所示,半导体装置50具备多个半导体元件52、54、56、58和对这些半导体元件52、54、56、58进行密封的树脂封装件60。多个半导体元件52、54、56、58包括第一晶体管元件52、第二晶体管元件54、第一二极管元件56和第二二极管元件58。各个半导体元件52、54、56、58中,容许电流在100安培以上,从而属于功率半导体元件。如图13所示,第一晶体管元件52与第二晶体管元件54串联电连接。第一二极管元件56与第一晶体管元件52逆并联电连接,并且第二二极管元件58与第二晶体管元件54逆并联电连接。
半导体装置50还具备多个散热板62、64、66、68、多个隔离部件72、74、76、78。多个散热板62、64、66、68以及多个隔离部件72、74、76、78中的每一个均为导电部件,并且由例如铜之类的金属材料形成。各个散热板62、64、66、68露出于树脂封装件60的下表面60a或上表面60b,从而将多个半导体元件52、54、56、58的热量向外部放出。如图14所示,第一晶体管元件52的下表面电极52a与散热板62被相互焊接在一起,从而在两者之间形成有焊锡接合层91。第一晶体管元件52的上表面电极52b与隔离部件72的下表面被相互焊接在一起,从而在两者之间形成有焊锡接合层92。隔离部件72的上表面与散热板66被相互焊接在一起,从而在两者之间形成有焊锡接合层93。
同样地,第二晶体管元件54的下表面电极54a与散热板64被相互焊接在一起,从而在两者之间形成有焊锡接合层94。第二晶体管元件54的上表面电极54b与隔离部件74的下表面被相互焊接在一起,从而在两者之间形成有焊锡接合层95。隔离部件74的上表面与散热板68被相互焊接在一起,从而在两者之间形成有焊锡接合层96。此外,散热板64的接合部65与散热板66的接合部67被相互焊接在一起,从而在两者之间形成有焊锡接合层97。虽然省略了图示,但与第一晶体管元件52以及第二晶体管元件54相同地,第一二极管元件56以及第二二极管元件58也通过焊接而被固定在散热板62、64、66、68以及隔离部件76、78上。
如图14、15所示,在与焊锡接合层91相接的散热板62以及第一晶体管元件52的各表面上形成有Ni膜101、102。此外,在与焊锡接合层92相接的第一晶体管元件52以及隔离部件72的各表面上形成有Ni膜103、104。虽然省略了图示,但与其他的焊锡接合层93~97相接的两个部件的各表面上也分别形成有Ni膜。
如图11、图12所示,半导体装置50还具备正极端子82、负极端子84、输出端子86以及多个控制端子88。正极端子82与散热板62被形成为一体。负极端子84被焊接在散热板68的接合部69上。输出端子86与散热板64被形成为一体。此处,各个散热板62、64、66、68与多个半导体元件52、54、56、58电连接而构成了导电路径。各个控制端子88经由接合引线89而与第一晶体管元件52或第二晶体管元件54的栅极衬垫等其他的电极衬垫连接。
以下,参照图16~图21而对上述的半导体装置50的制造方法进行说明。首先,如图16所示,对相互进行焊接的两个部件实施前文所述的第一热处理工序以及第二热处理工序。由此,使焊锡熔敷在各个部件上。例如,关于相互进行焊接的散热板62与第一晶体管元件52,对散热板62实施第一热处理工序,且对第一晶体管元件52实施第二热处理工序。在第一热处理工序中,使作为Sn-Cu系焊锡的第一焊锡91a在被形成于散热板62上的Ni膜101上熔融,从而在该Ni膜101上生成(Cu,Ni)6Sn5。另一方面,在第二热处理工序中,使同样作为Sn-Cu系焊锡的第二焊锡91b在被形成于第一晶体管元件52上的Ni膜102上熔融,从而在该Ni膜102上生成(Cu,Ni)6Sn5。此处,如前文所述,第一焊锡91a以及第二焊锡91b含有重量百分比0.9%以上的Cu,并且更优选为含有重量百分比1.6%以上的Cu。关于其他的焊接位置也以同样的方式,对各个部件实施第一热处理工序或第二热处理工序而使第一焊锡92a~97a或第二焊锡92b~97b熔敷在各个部件上(另外,图16中未图示的第一二极管元件56等其他部件也同样如此)。
接着,如图17所示,在散热板62上重叠地配置第一晶体管元件52以及隔离部件72,并且在散热板64上重叠地配置第二晶体管元件54以及隔离部件74。这时,被熔敷在散热板62上的第一焊锡91a与被熔敷在第一晶体管元件52的下表面上的第二焊锡91b接触或对置,被熔敷在第一晶体管元件52的上表面上的第一焊锡92a与被熔敷在隔离部件72的下表面上的第二焊锡92b接触或对置。关于第二晶体管元件54侧也以同样的方式,第一焊锡94a、95a分别与对应的第二焊锡94b、95b接触或对置。虽然省略图示,但在散热板62上还重叠地配置第一二极管元件56以及隔离部件76,并且在散热板64上还重叠地配置第二二极管元件58以及隔离部件78。另外,散热板62以及散热板64能够作为与多个控制端子88等被形成为一体的引线框而准备。
接着,如图18所示,通过实施前文所述的第三热处理工序,从而使被熔敷在各个部件上的第一焊锡91a、92a、94a、95a与被熔敷在各个部件上的第二焊锡91b、92b、94b、95b熔融而一体化。由此,第一晶体管元件52经由焊锡接合层91而与散热板62接合且经由焊锡接合层92而与隔离部件72接合。此外,第二晶体管元件54经由焊锡接合层94而与散热板64接合且经由焊锡接合层95而与隔离部件74接合。虽然省略图示,但以同样的方式,第一二极管元件56经由焊锡接合层而与散热板62以及隔离部件76接合,并且第二二极管元件58经由焊锡接合层而与散热板64以及隔离部件78接合。之后,实施相对于控制端子88的引线接合。
接着,如图19所示,将上述的第三热处理工序后的半成品与散热板66、68进行组合。这时,被熔敷在隔离部件72的上表面上的第一焊锡93a与被熔敷在散热板66的下表面上的第二焊锡93b接触或对置,并且被熔敷在隔离部件74的上表面上的第一焊锡96a与被熔敷在散热板68的下表面上的第二焊锡96b接触或对置。此外,被熔敷在散热板64的接合部65上的第一焊锡97a与被熔敷在散热板66的接合部67上的第二焊锡97b接触或对置。
接着,如图20所示,通过实施第二次的第三热处理工序,从而使被熔敷在各个部件上的第一焊锡93a、96a、97a与被熔敷在各个部件上的第二焊锡93b、96b、97b熔融而一体化。由此,散热板66经由焊锡接合层93而与隔离部件72接合,散热板68经由焊锡接合层96而与隔离部件74接合。此外,散热板66的接合部67经由焊锡接合层97而与散热板64的接合部65接合。虽然省略图示,但散热板66还被焊接在第一二极管元件56上的隔离部件76上,并且散热板68还被焊接在第二二极管元件58上的隔离部件78上。之后,如图21所示,通过模压成形而形成树脂封装件60,并实施引线框的切断以及其他所需的工序,从而完成半导体装置50。
上述的半导体装置50的制造方法为一个示例,在本说明书中公开的焊接方法也能应用于各种结构的半导体装置的制造方法中。但是,也假定如下的情况,即,半导体装置50具有功率半导体元件52、54、56、58,由于通电有大电流从而使焊接位置达到200℃。关于这一点,根据上述的制造方法,通过在各个部件的Ni膜(例如Ni膜101、102、103)上生成充分的(Cu,Ni)6Sn5,从而能够形成即使在200℃的高温下也可抑制Ni膜的金属间化合物化的阻挡层。因此,上述的制造方法能够理想地应用于具有功率半导体元件52、54、56、58的半导体装置50的制造方法中。另外,虽然在上述的半导体装置50的制造方法中,将本说明书中所公开的焊接方法应用于多个焊接位置,但本说明书中所公开的焊接方法也可以仅应用于多个焊接位置的一部分。
以上,虽然对几个具体例进行了详细说明,但这些仅为示例,并不对权利要求书进行限定。在权利要求书所记载的技术中包括对上文所例示的具体例进行了各种改变、变更的技术。以下,对从本说明书的公开内容中所掌握的技术事项进行列述。另外,以下记载的技术事项分别为独立的技术事项,并且通过单独或各种组合的形式来发挥技术上的有用性。
在本说明书中,公开了一种具有第一部件和被接合在第一部件上的第二部件的半导体装置的制造方法。该制造方法包括:使含有重量百分比0.9%以上的Cu的第一Sn-Cu系焊锡在被形成于第一部件上的Ni膜上熔融,从而在第一部件的Ni膜上生成(Cu,Ni)6Sn5的第一热处理工序;使含有重量百分比0.9%以上的Cu的第二Sn-Cu系焊锡在被形成于第二部件上的Ni膜上熔融,从而在第二部件的Ni膜上生成(Cu,Ni)6Sn5的第二热处理工序;使第一热处理工序后的第一Sn-Cu系焊锡与第二热处理工序后的第二Sn-Cu系焊锡熔融而一体化,从而使第一部件与第二部件相互接合的第三热处理工序。根据该制造方法,即使在第一以及第二Sn-Cu系焊锡的Cu浓度比较低的情况下,也能够在第一部件以及第二部件的各Ni膜上生成预先设定的量的(Cu,Ni)6Sn5。
在上述的制造方法中,可以将在第三热处理工序中使第一Sn-Cu系焊锡以及第二Sn-Cu系焊锡熔融的时间设为短于在第一热处理工序中使第一Sn-Cu系焊锡熔融的时间以及在第二热处理工序中使第二Sn-Cu系焊锡熔融的时间。第三热处理工序并非以金属化合物的生成为目的,而是仅通过使第一Sn-Cu系焊锡以及第二Sn-Cu系焊锡熔融便能够使两者一体化。因此,可以使在第三热处理工序中使焊锡熔融的时间短于在第一热处理工序以及第二処理工序中使焊锡熔融的时间,由此,能够缩短半导体装置的制造所需的时间。
在上述的制造方法中,优选为,第一Sn-Cu系焊锡与第二Sn-Cu系焊锡中的至少一方含有重量百分比1.6%以上的Cu。由此,能够在第一部件与第二部件的至少一方的Ni膜上生成可发挥更为优异的阻挡性的量的(Cu,Ni)6Sn5。
在上述的制造方法中,优选为,第一部件与第二部件中的至少一方为功率半导体元件。在具有功率半导体元件的半导体装置中,存在因通电有较大的电流,从而焊接位置被加热至例如达到200℃那样的高温的情况。关于这一点,根据上述的制造方法,通过在Ni膜上生成充分的(Cu,Ni)6Sn5,从而能够形成即使在200℃的高温下也可长时间抑制Ni膜的金属间化合物化的阻挡层。由此,能够显著地提高具有功率半导体元件的半导体装置的耐热性。
符号说明
10:第一部件;12:第一部件的Ni膜;14:第一焊锡;20:第二部件;22:第二部件的Ni膜;24:第二焊锡;30:焊锡接合层;50:半导体装置;52:第一晶体管元件;54:第二晶体管元件;56:第一二极管元件;58:第二二极管元件;60:树脂封装件;62、64、66、68:散热板;72、74、76、78:隔离部件;60:树脂封装件;91、92、93、94、95、96:焊锡接合层;91a、92a、94a、95a、96a:第一焊锡;91b、92b、94b、95b、96b:第二焊锡;101、102、103、104:Ni膜。
Claims (5)
1.一种半导体装置的制造方法,所述半导体装置具有第一部件和被接合在所述第一部件上的第二部件,所述制造方法包括:第一热处理工序,使含有重量百分比0.9%以上的Cu的第一Sn-Cu系焊锡在被形成于所述第一部件上的Ni膜上熔融,从而在所述第一部件的所述Ni膜上生成(Cu,Ni)6Sn5;第二热处理工序,使含有重量百分比0.9%以上的Cu的第二Sn-Cu系焊锡在被形成于所述第二部件上的Ni膜上熔融,从而在所述第二部件的所述Ni膜上生成(Cu,Ni)6Sn5;第三热处理工序,使所述第一热处理工序后的所述第一Sn-Cu系焊锡与所述第二热处理工序后的所述第二Sn-Cu系焊锡熔融而一体化,从而使所述第一部件与所述第二部件相互接合。
2.如权利要求1所述的制造方法,其中,
在所述第三热处理工序中使所述第一Sn-Cu系焊锡以及所述第二Sn-Cu系焊锡熔融的时间短于,在所述第一热处理工序中使所述第一Sn-Cu系焊锡熔融的时间以及在所述第二热处理工序中使所述第二Sn-Cu系焊锡熔融的时间。
3.如权利要求1或2所述的制造方法,其中,
所述第一Sn-Cu系焊锡与所述第二Sn-Cu系焊锡中的至少一方含有重量百分比1.6%以上的Cu。
4.如权利要求1至3中任意一项所述的制造方法,其中,
所述第一部件与所述第二部件中的至少一方为功率半导体元件。
5.如权利要求1至4中任意一项所述的制造方法,其中,
所述第一部件的所述Ni膜与所述第二部件的所述Ni膜中的至少一方被Au或Ag覆盖。
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP6772768B2 (ja) * | 2016-11-09 | 2020-10-21 | 株式会社デンソー | 半導体装置 |
US10896869B2 (en) | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
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US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010090433A (ja) * | 2008-10-08 | 2010-04-22 | Hitachi Ltd | 金属条の製造方法 |
CN101996969A (zh) * | 2009-08-24 | 2011-03-30 | 株式会社日立制作所 | 半导体装置以及车载交流发电机 |
US20110186989A1 (en) * | 2010-02-04 | 2011-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Bump Formation Process |
JP2012028589A (ja) * | 2010-07-23 | 2012-02-09 | Ayumi Kogyo Kk | 加熱溶融処理方法および加熱溶融処理装置 |
CN103717340A (zh) * | 2012-08-02 | 2014-04-09 | 株式会社谷黑组 | 具有电极熔蚀防止层的部件及其制造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3152945B2 (ja) | 1998-03-26 | 2001-04-03 | 株式会社日本スペリア社 | 無鉛はんだ合金 |
JP4105409B2 (ja) * | 2001-06-22 | 2008-06-25 | 株式会社ルネサステクノロジ | マルチチップモジュールの製造方法 |
JP3607655B2 (ja) * | 2001-09-26 | 2005-01-05 | 株式会社東芝 | マウント材、半導体装置及び半導体装置の製造方法 |
JP3757881B2 (ja) * | 2002-03-08 | 2006-03-22 | 株式会社日立製作所 | はんだ |
JP4416373B2 (ja) * | 2002-03-08 | 2010-02-17 | 株式会社日立製作所 | 電子機器 |
JP4325571B2 (ja) * | 2005-02-28 | 2009-09-02 | 株式会社日立製作所 | 電子装置の製造方法 |
US7670951B2 (en) * | 2005-06-27 | 2010-03-02 | Intel Corporation | Grid array connection device and method |
JP4569423B2 (ja) | 2005-08-31 | 2010-10-27 | 株式会社日立製作所 | 半導体装置の製造方法 |
US20070238283A1 (en) * | 2006-04-05 | 2007-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel under-bump metallization for bond pad soldering |
JP4939891B2 (ja) * | 2006-10-06 | 2012-05-30 | 株式会社日立製作所 | 電子装置 |
JP2010147245A (ja) * | 2008-12-18 | 2010-07-01 | Shinko Electric Ind Co Ltd | 電子部品の製造方法 |
CN101447548B (zh) * | 2008-12-26 | 2011-03-30 | 中国科学院上海硅酸盐研究所 | 热电器件的制作方法 |
JP5517694B2 (ja) | 2010-03-29 | 2014-06-11 | 株式会社 日立パワーデバイス | 半導体装置 |
TW201311944A (zh) * | 2011-08-12 | 2013-03-16 | Mitsubishi Materials Corp | 插拔性優異的鍍錫銅合金端子材及其製造方法 |
US20130042912A1 (en) * | 2011-08-12 | 2013-02-21 | Hitachi Chemical Company, Ltd. | Solder bonded body, method of producing solder bonded body, element, photovoltaic cell, method of producing element and method of producing photovoltaic cell |
JP2015072996A (ja) * | 2013-10-02 | 2015-04-16 | 新光電気工業株式会社 | 半導体装置 |
JP5779666B2 (ja) * | 2014-01-06 | 2015-09-16 | 株式会社 日立パワーデバイス | 自動車用パワーモジュール、自動車 |
JP6287759B2 (ja) | 2014-10-30 | 2018-03-07 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
JP6281468B2 (ja) | 2014-10-30 | 2018-02-21 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
-
2015
- 2015-11-16 JP JP2015224317A patent/JP6330786B2/ja active Active
-
2016
- 2016-11-02 US US15/341,379 patent/US10312211B2/en active Active
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- 2016-11-14 TW TW105137093A patent/TWI632623B/zh active
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010090433A (ja) * | 2008-10-08 | 2010-04-22 | Hitachi Ltd | 金属条の製造方法 |
CN101996969A (zh) * | 2009-08-24 | 2011-03-30 | 株式会社日立制作所 | 半导体装置以及车载交流发电机 |
US20110186989A1 (en) * | 2010-02-04 | 2011-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Bump Formation Process |
JP2012028589A (ja) * | 2010-07-23 | 2012-02-09 | Ayumi Kogyo Kk | 加熱溶融処理方法および加熱溶融処理装置 |
CN103717340A (zh) * | 2012-08-02 | 2014-04-09 | 株式会社谷黑组 | 具有电极熔蚀防止层的部件及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111435646A (zh) * | 2019-01-11 | 2020-07-21 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN111435646B (zh) * | 2019-01-11 | 2023-09-08 | 株式会社电装 | 半导体装置及其制造方法 |
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