CN107078122A - 一种指纹芯片封装及加工方法 - Google Patents

一种指纹芯片封装及加工方法 Download PDF

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CN107078122A
CN107078122A CN201780000027.2A CN201780000027A CN107078122A CN 107078122 A CN107078122 A CN 107078122A CN 201780000027 A CN201780000027 A CN 201780000027A CN 107078122 A CN107078122 A CN 107078122A
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chip
golden finger
dao
chip package
fingerprint
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CN107078122B (zh
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曾珊珊
汪鹏辉
罗军平
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Huiding Technology Co Ltd
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Abstract

本发明公开了一种指纹芯片封装及加工方法，涉及生物识别领域，该指纹芯片封装包括：引线框架，芯片，以及包裹所述引线框架和芯片的塑封件；所述引线框架包括基岛、连筋以及金手指；所述基岛用于承载所述芯片；所述连筋用于支撑所述引线框架并通过所述金手指连接所述基岛；所述金手指用于固定所述基岛，以及电性连接所述芯片。有效降低所述指纹芯片封装的切割难度，提高封装单颗分离的效率，同时多边金手指与基岛的接触面积大于现有技术中连筋与基岛的接触面积，提高了芯片贴合焊线连接生产稳定性，同时，与芯片有电性连接的金手指端部的连筋被完全蚀刻，使指纹芯片封装内部各个组成部分断开电性连接，可以实现对所述指纹芯片封装的条状测试。

Description

一种指纹芯片封装及加工方法
技术领域
本发明涉及生物识别领域，尤其涉及一种指纹芯片封装及加工方法。
背景技术
指纹芯片封装需要根据客户不同需求，被切割成不同形状，因此一般是条状出货，在出货前会先做测试，也称为条状测试。
如图1所示，为现有的普通引线框架类封装体内部的结构示意图，连筋将引线框架所有部件连接起来，包括放置芯片用的基岛，和连接封装体与外部PCB(印刷线路板)的金手指，以实现物理连接；在封装过程中，引线框架内部件会与芯片铝垫通过焊线连接实现电气连接，不同部件会被赋予不同电信号；由于连筋将所有部件连接起来，因此所有部件被电性短路，无法进行条状测试。
一般引线框架一个单元内部，会有四条连筋来支撑基岛，对于一些面积大的封装体，连筋太长容易变形导致基岛倾斜，而指纹芯片一般面积较大，普通引线框架设计用于指纹芯片封装的话，容易发生引线框架变形的异常，影响生产稳定性和良率。
此外，连筋为金属材质，相比封装用塑料件，不易被切割。
发明内容
为了克服现有技术中相关产品的不足，本发明提出一种指纹芯片封装及加工方法，解决当前的指纹芯片封装结构不稳定的问题。
本发明提供了一种指纹芯片封装，包括：引线框架，芯片，以及包裹所述引线框架和芯片的塑封件；所述引线框架包括基岛、连筋以及金手指；所述基岛用于承载所述芯片；所述连筋用于支撑所述引线框架并通过所述金手指连接所述基岛；所述金手指用于固定所述基岛，以及电性连接所述芯片。
作为本发明的进一步改进，所述金手指设置于所述引线框架的四条边上，且每条边上设置至少一个金手指。
作为本发明的进一步改进，所述金手指用于固定所述基岛，以及电性连接所述芯片，包括：至少两条边上的所述金手指与所述基岛连接，以固定所述基岛；以及至少一条边上的所述金手指与所述芯片电性连接。
作为本发明的进一步改进，三条边上的所述金手指与所述基岛连接，且一条边上的所述金手指与所述芯片电性连接。
作为本发明的进一步改进，所述芯片上包括至少一个铝垫；所述金手指电性连接所述芯片，包括：使用焊线将所述芯片上的铝垫与所述金手指一一对应连接。
作为本发明的进一步改进，还包括：所述用于电性连接所述芯片的金手指之间的电性连接完全断开。
本发明提供了一种指纹芯片封装的加工方法，用于加工上述的指纹芯片封装，包括：将芯片贴合在引线框架的基岛上并固定；使用焊线电性连接所述芯片与至少一条边上的所述金手指；使用塑封件注塑所述指纹芯片封装；断开所述电性连接所述芯片的金手指之间的电性连接。
作为本发明的进一步改进，所述断开所述电性连接所述芯片的金手指之间的电性连接，包括：背面蚀刻所述电性连接所述芯片的金手指对应的连筋，以断开所述电性连接所述芯片的金手指之间的电性连接。
作为本发明的进一步改进，还包括：条状测试所述指纹芯片封装。
与现有技术相比，本发明有以下优点：
有效降低所述指纹芯片封装的切割难度，提高封装单颗分离的效率，同时多边的连筋上的金手指与基岛的接触面积大于现有技术中连筋与基岛的接触面积，提高了芯片贴合焊线连接生产稳定性，同时，与芯片有电性连接金手指端部的连筋被完全蚀刻，使指纹芯片封装内部各个组成部分及相邻指纹芯片封装体均断开电性连接，可以实现对所述指纹芯片封装的条状测试。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有普通引线框架类封装体内部的结构示意图；
图2为本发明实施例所述指纹芯片封装的结构示意图；
图3为本发明实施例所述指纹芯片封装加工方法的流程示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例,附图中给出了本发明的较佳实施例。本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例，相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
参阅图2所示，所述指纹芯片封装包括引线框架1、芯片2以及包裹所述引线框架1和芯片2的塑封件(图未示)，所述的芯片2设置在所述引线框架1中间区域并与所述引线框架1固定连接，所述的芯片2为硅基指纹芯片，在其他实施方式中，也可以是其他材质或其他功能的芯片。
所述引线框架1是所述芯片2的载体，主要用于连接芯片2内部电路与外部PCB，所述芯片2贴合在所述引线框架1上并固定，所述引线框架1包括基岛13、连筋11以及金手指12。
所述的连筋11是由金属材质组成的框架，包括四条边，是引线框架中对所有部件起物理连接的结构，在所述连筋11的每条边上均设置有至少一个金手指12，所述连筋11用于支撑所述引线框架1并通过所述金手指12连接所述基岛13，所述的金手指12用于电性连接所述芯片2与所述指纹芯片封装外部结构以及固定所述基岛13；所述金手指12在各边连筋11上的数量根据实际需求设置，在本发明实施例中，所述金手指12在各边连筋11上的数量相同，在本发明的其他实施方式中，所述金手指12在各边连筋11上的数量也可以不同；在引线框架1的中间区域设置有基岛13，所述基岛13与至少两条边上的金手指12固定连接，所述芯片2固定设置在所述基岛13上，所述芯片2上设置有至少一个铝垫21，所述铝垫21通过焊线3与至少一条边上的金手指12电性连接，其中，使用焊线3将所述芯片2上的铝垫21与所述金手指12一一对应连接，剩余边上的金手指12与所述基岛13固定连接，所述芯片2通过与金手指12电性连接将电信号传递到外部PCB板的结构，在本发明的其他实施例中，与所述铝垫21通过焊线3连接的金手指的数量及排列方式可以灵活选择，可以连续排列也可以分散排列，数量不限定一排。
在塑封件注塑前，本发明实施例先不对所述连筋11进行处理，待塑封件注塑完成后，由于连筋11背面与注塑的模板位于同一平面上，所述连筋11背面没有被注塑材料覆盖，在塑封件注塑完成后可以对所述连筋11进行蚀刻，使金手指12与相邻的单颗封装体之间电性连接被断开，具体的：
如图2所示，其中，图中浅色区域为连筋11半蚀刻的位置，图中深色区域为连筋11完全蚀刻的位置，所述基岛13与连筋11任意三边上的金手指12固定连接，所述铝垫21通过焊线3与第四边连筋11上的金手指12电性连接；在本发明的其他实施例中，与基岛13相连的连筋11的区域大小和分布，及与芯片2有电性连接的金手指12端部的连筋11的区域大小和分布，可灵活选择；所述连筋11在在塑封件注塑前不进行蚀刻，在所述塑封件注塑完成后，所述与基岛13连接的三边连筋11进行半蚀刻，所述与所述芯片2通过焊线3连接的金手指12所在的第四边连筋11进行完全蚀刻，所述完全蚀刻的部分位于与金手指12固定连接的区域，在其他实施方式中，其完全蚀刻的范围也可以根据实际需求自行选择；通过该过程，通过焊线3与外部电性连接第四边连筋11此时与其他连筋11断开，使所述指纹芯片封装内各个组成部分完全断开电性连接，同时由于塑封件的存在，即便是对连筋11部分进行完全蚀刻，所述塑封件也足以支撑所述指纹芯片封装内各个组成部分的物理结构，在保证了结构稳定的基础上，可以实现对所述指纹芯片封装的条状测试；所述半蚀刻和完全蚀刻的位置均位于连筋11的背面。
在本发明的其他实施方式中，所述芯片2与金手指12电性连接的位置可以是一边，也可以是多边，根据实际情况进行选择，与所述芯片2有电性连接的金手指12的排列方式可以灵活选择，可以是连续排列，也可以分散放置，当所述芯片2与金手指12电性连接的位置为多边时，相应的，所述多排金手指12对应连接的连筋11进行完全蚀刻，即完全蚀刻的连筋11也为多边。
所述的蚀刻是指通过化学方法使材料移除的手段，在本发明的实施例中，连筋11的半蚀刻是指蚀刻连筋11的一半厚度，用于保持与连筋11连接的所述指纹芯片封装内各个组成部分物理结构，连筋11的完全蚀刻是指蚀刻连筋11的整体厚度即完全移除连筋11，用于将连筋11的整体断开，避免因连筋11的连接作用使所述指纹芯片封装内各个组成部分电性短路，在本发明的其他实施方式中，所述的完全蚀刻的深度也可为其他厚度，只要断开所述指纹芯片封装内各个组成部分电性连接即可。
在本发明中，与基岛13连接的连筋11在注塑完成后背面半蚀刻，在其他实施例中，与基岛13连接的连筋11也可以在注塑前进行背面半蚀刻，与基岛13连接的连筋11由于没有与芯片2进行电性连接，因此其蚀刻方式及蚀刻厚度及蚀刻区域可灵活选择。
在本发明中，与芯片2有电性连接的金手指12端部的连筋11，在注塑完成后进行背面全蚀刻以断开电性连接，在其他实施例中，与芯片2有电性连接的金手指12端部的连筋11，也可以在注塑前进行正面半蚀刻，然后在注塑后进行背面半蚀刻，其蚀刻方式及蚀刻厚度及蚀刻区域也可灵活选择，只要是通过蚀刻方式断开封装体内各部件电性连接的方式，均在本发明保护范围内。
本发明实施例通过连筋11的任意三边上的金手指12与所述基岛13固定连接，而不是在引线框架的四个角落通过连筋对所述基岛13进行固定，可以有效降低所述指纹芯片封装的切割难度，提高封装单颗分离的效率，同时多边金手指12与基岛13的接触面积大于现有技术中连筋11与基岛13的接触面积，提高了芯片2贴合焊线3连接生产稳定性，同时，与芯片2有电性连接的金手指12端部的连筋11被完全蚀刻，使指纹芯片封装内部各个组成部分及相邻指纹芯片封装体均断开电性连接，可以实现对所述指纹芯片封装的条状测试。
在上述实施例的基础上，参阅图3所示，为本发明应用于所述指纹芯片封装的加工方法的流程示意图，所述指纹芯片封装的加工方法包括：
S101：将芯片贴合在引线框架的基岛上并固定。
S102：使用焊线电性连接所述芯片与至少一条边上的所述金手指。
S103：使用塑封件注塑所述指纹芯片封装。
S104：断开所述电性连接所述芯片的金手指之间的电性连接。
本发明实施例通过背面蚀刻所述电性连接所述芯片的金手指对应的连筋，以断开所述电性连接所述芯片的金手指之间的电性连接。
可选的，在本发明实施例中，所述指纹芯片封装的加工方法还包括：
S105：条状测试所述指纹芯片封装。
本发明实施例所述的指纹芯片封装的加工方法应用于上述实施例所提供的指纹芯片封装，所述指纹芯片封装的加工方法具备上述指纹芯片封装相应的功能模块和有益效果，具体请参阅上述指纹芯片封装的实施例，本发明实施例在此不再赘述。
在本发明所提供的上述实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如，多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
以上仅为本发明的实施例，但并不限制本发明的专利范围，尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来而言，其依然可以对前述各具体实施方式所记载的技术方案进行修改，或者对其中部分技术特征进行等效替换。凡是利用本发明说明书及附图内容所做的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明专利保护范围之内。

Claims (9)

1.一种指纹芯片封装，其特征在于，包括：
引线框架，芯片，以及包裹所述引线框架和芯片的塑封件；
所述引线框架包括基岛、连筋以及金手指；
所述基岛用于承载所述芯片；
所述连筋用于支撑所述引线框架并通过所述金手指连接所述基岛；
所述金手指用于固定所述基岛，以及电性连接所述芯片。
2.根据权利要求1所述的指纹芯片封装，其特征在于，所述金手指设置于所述引线框架的四条边上，且每条边上设置至少一个金手指。
3.根据权利要求2所述的指纹芯片封装，其特征在于，所述金手指用于固定所述基岛，以及电性连接所述芯片，包括：
至少两条边上的所述金手指与所述基岛连接，以固定所述基岛；以及
至少一条边上的所述金手指与所述芯片电性连接。
4.根据权利要求3所述的指纹封装结构，其特征在于，三条边上的所述金手指与所述基岛连接，且一条边上的所述金手指与所述芯片电性连接。
5.根据权利要求1-4任意一项所述的指纹封装结构，其特征在于，所述芯片上包括至少一个铝垫；
所述金手指电性连接所述芯片，包括：
使用焊线将所述芯片上的铝垫与所述金手指一一对应连接。
6.根据权利要求1-5任一项所述的指纹芯片封装，其特征在于，还包括：
所述用于电性连接所述芯片的金手指之间的电性连接完全断开。
7.一种指纹芯片封装的加工方法，用于加工权利要求1-6所述的指纹芯片封装，其特征在于，包括：
将芯片贴合在引线框架的基岛上并固定；
使用焊线电性连接所述芯片与至少一条边上的所述金手指；
使用塑封件注塑所述指纹芯片封装；
断开所述电性连接所述芯片的金手指之间的电性连接。
8.根据权利要求7所述的指纹芯片封装的加工方法，其特征在于，所述断开所述电性连接所述芯片的金手指之间的电性连接，包括：
背面蚀刻所述电性连接所述芯片的金手指对应的连筋，以断开所述电性连接所述芯片的金手指之间的电性连接。
9.根据权利要求7或8所述的指纹芯片封装的加工方法，其特征在于，还包括：
条状测试所述指纹芯片封装。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037084A (zh) * 2018-07-27 2018-12-18 星科金朋半导体（江阴）有限公司 一种qfn指纹识别芯片的封装方法
CN110600496A (zh) * 2019-09-20 2019-12-20 上海显耀显示科技有限公司 一种Micro-LED芯片封装结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW429570B (en) * 1998-10-21 2001-04-11 Amkor Technology Inc Plastic integrated circuit device package and micro-leadframe and method for making the package
CN1735963A (zh) * 2003-01-15 2006-02-15 先进互联技术有限公司 具有局部预制图形化引线框架的半导体封装及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4314685B2 (ja) * 1999-08-20 2009-08-19 ソニー株式会社 指紋認識用半導体装置
US6653723B2 (en) * 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
US6797540B1 (en) * 2002-11-18 2004-09-28 National Semiconductor Corporation Dap isolation process
JP2005026466A (ja) * 2003-07-02 2005-01-27 Renesas Technology Corp 半導体装置およびリードフレーム
CN101826499A (zh) * 2009-03-06 2010-09-08 日月光半导体制造股份有限公司 四方扁平无引脚封装
US8334467B2 (en) * 2009-06-17 2012-12-18 Lsi Corporation Lead frame design to improve reliability
JP2011066241A (ja) * 2009-09-17 2011-03-31 Sony Corp 固体撮像装置とその製造方法、及び電子機器
US20150076675A1 (en) * 2013-09-16 2015-03-19 Stmicroelectronics, Inc. Leadframe package with wettable sides and method of manufacturing same
US20160148876A1 (en) * 2014-11-20 2016-05-26 Microchip Technology Incorporated Flat no-leads package with improved contact pins
KR20160143071A (ko) * 2015-06-04 2016-12-14 앰코 테크놀로지 코리아 주식회사 지문센서 패키지
CN204991696U (zh) * 2015-09-11 2016-01-20 深圳市汇顶科技股份有限公司 传感芯片封装组件和具有该传感芯片封装组件的电子设备

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW429570B (en) * 1998-10-21 2001-04-11 Amkor Technology Inc Plastic integrated circuit device package and micro-leadframe and method for making the package
CN1735963A (zh) * 2003-01-15 2006-02-15 先进互联技术有限公司 具有局部预制图形化引线框架的半导体封装及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037084A (zh) * 2018-07-27 2018-12-18 星科金朋半导体（江阴）有限公司 一种qfn指纹识别芯片的封装方法
CN110600496A (zh) * 2019-09-20 2019-12-20 上海显耀显示科技有限公司 一种Micro-LED芯片封装结构

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