CN107068693A - 电子组件及其制造方法、转置元件及微元件的转置方法 - Google Patents
电子组件及其制造方法、转置元件及微元件的转置方法 Download PDFInfo
- Publication number
- CN107068693A CN107068693A CN201710282050.7A CN201710282050A CN107068693A CN 107068693 A CN107068693 A CN 107068693A CN 201710282050 A CN201710282050 A CN 201710282050A CN 107068693 A CN107068693 A CN 107068693A
- Authority
- CN
- China
- Prior art keywords
- connection electrode
- solder
- transparency conducting
- conducting layer
- microcomponent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 229910000679 solder Inorganic materials 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000002105 nanoparticle Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 167
- 229910052751 metal Inorganic materials 0.000 claims description 79
- 239000002184 metal Substances 0.000 claims description 79
- 230000017105 transposition Effects 0.000 claims description 59
- 239000011469 building brick Substances 0.000 claims description 53
- 239000011241 protective layer Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 15
- 230000008018 melting Effects 0.000 claims description 14
- 238000002844 melting Methods 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 11
- 238000009738 saturating Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229920005573 silicon-containing polymer Polymers 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims 7
- 230000037431 insertion Effects 0.000 claims 7
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 7
- 241000209094 Oryza Species 0.000 description 18
- 235000007164 Oryza sativa Nutrition 0.000 description 18
- 239000010408 film Substances 0.000 description 18
- 235000009566 rice Nutrition 0.000 description 18
- 239000007789 gas Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052725 zinc Inorganic materials 0.000 description 7
- 239000011701 zinc Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 239000011787 zinc oxide Substances 0.000 description 5
- 239000002585 base Substances 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000007788 roughening Methods 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910001195 gallium oxide Inorganic materials 0.000 description 3
- 230000012447 hatching Effects 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 229910005555 GaZnO Inorganic materials 0.000 description 1
- -1 IZO) Chemical compound 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Polymers C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- LFLZOWIFJOBEPN-UHFFFAOYSA-N nitrate, nitrate Chemical compound O[N+]([O-])=O.O[N+]([O-])=O LFLZOWIFJOBEPN-UHFFFAOYSA-N 0.000 description 1
- 150000003961 organosilicon compounds Chemical class 0.000 description 1
- NIFHFRBCEUSGEE-UHFFFAOYSA-N oxalic acid Chemical compound OC(=O)C(O)=O.OC(=O)C(O)=O NIFHFRBCEUSGEE-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
- H01L2224/03614—Physical or chemical etching by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/03831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05017—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/276—Manufacturing methods by patterning a pre-deposited material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/276—Manufacturing methods by patterning a pre-deposited material
- H01L2224/2761—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29023—Disposition the whole layer connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32501—Material at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75312—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83365—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electroluminescent Light Sources (AREA)
- Led Device Packages (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
一种电子组件包括电路基板、连接电极、微元件以及焊料。连接电极位于电路基板上。连接电极具有第一透明导电层,且第一透明导电层的表面位于相对电路基板的一侧且具有多个微米或纳米级颗粒。微元件与连接电极电性连接。焊料位于连接电极与微元件之间,且固着微元件于连接电极上。
Description
技术领域
本发明关于一种微元件的转置技术,特别是一种电子组件、转置组件、电子组件的制造方法及微元件的转置方法。
背景技术
目前来说,电子产品,例如笔记本电脑、显示面板、平板、智能型手机等,其市场趋势持续朝向轻薄化的设计迈进。因此,将微元件应用于电子设备、装置、仪器上已蔚为主流。
在设置微元件的制程中,需通过转置技术以将微元件移动并设置于目标基板上。一般而言,可以通过真空吸头吸取微元件。然而,真空吸头一般为硬质材料,在吸取过程中,真空吸头容易与微元件碰撞而导致微元件受损。此外,在转置过程中,容易因下压力不均而使得微元件位移或是与目标基板电性接触不良,或是在移开真空吸头时拉力不均而使焊料龟裂。
发明内容
本发明一实施例提出一种电子组件,其包括电路基板、连接电极、微元件以及焊料。连接电极位于电路基板上。连接电极具有第一透明导电层。第一透明导电层的表面位于相对电路基板的一侧且具有多个微米或纳米级颗粒。微元件与连接电极电性连接。焊料位于连接电极与微元件之间,且固着微元件于连接电极上。
本发明一实施例提出一种电子组件的制造方法,其包含:提供一电路基板以及形成连接电极于电路基板上。于此,连接电极的相对于电路基板的一侧的表面具有多数微突起。其中,形成连接电极于电路基板上的步骤包括:形成第一透明导电薄膜于电路基板上、图案化第一透明导电薄膜以形成第一透明导电图案、对第一透明导电图案进行非完全退火以及蚀刻第一透明图案的相对电路基板的一侧的表面以形成第一透明导电层,以使第一透明导电层的表面具有多个微米或纳米级颗粒。其中,此些微突起为此些微米或纳米级颗粒。
本发明一实施例提出一种微元件的转置方法,其包含:形成焊料于连接电极上、通过转置组件拾取微元件、通过转置组件将拾取的微元件移动于焊料上、以焊料将微元件固着于连接电极上、驱动帮浦件以通入气体至通孔,以及于气体的通入过程中分离微元件与弹性吸头。于此,各连接电极具有第一透明导电层,并且第一透明导电层的表面具有多个微米或纳米级颗粒。于此,转置组件包括弹性吸头以及帮浦件。弹性吸头的表面具有分别拾取微元件的凸部,且弹性吸头的另一表面耦接帮浦件。帮浦件具有至少一气孔,且弹性吸头具有连通气孔的通孔,并且各通孔由弹性吸头的表面穿过凸部而贯穿至弹性吸头的另一表面。其中各连接电极的此些微米或纳米级颗粒中的多数者嵌入对应的焊料的底部。
本发明一实施例提出一种转置组件,其包含弹性吸头与帮浦件。弹性吸头的表面具有至少一凸部。弹性吸头具有至少一通孔,并且各通孔由弹性吸头的表面穿过至少一凸部中之一贯穿至弹性吸头的另一表面。帮浦件耦接弹性吸头的另一表面。帮浦件具有至少一气孔,并且至少一气孔连通于至少一通孔。
综上所述,本发明实施例的电子组件、转置组件、电子组件的制造方法及微元件的转置方法,其通过在连接电极的表面形成多数微突起以使焊料能更稳固地将转置的微元件与连接电极相互固着。依此,连接电极表面的多数微突起嵌入于焊料的底部,藉以增加焊料与连接电极之间的接触面积以及附着力。因此,能避免转置组件于转置过程中离开微元件时,因焊料与连接电极接着不佳而使微元件歪斜、位移或是脱落等情况发生,进而能提高电子组件的良率。在一些实施例中,本发明实施例的转置组件及微元件的转置方法,其通过弹性吸头来黏取微元件,由于弹性吸头具有黏性及弹性而且为柔软材料,因此弹性吸头不易与微元件碰撞而导致微元件受损。在一些实施例中,本发明实施例的转置组件及微元件的转置方法,更可通过于通孔中抽取气体或是吹送气体以利于弹性吸头更加地拾取或放置微元件。
附图说明
图1为本发明一实施例的电子组件的结构俯视示意图。
图2为对应于图1之A-A剖线的电子组件的截面示意图。
图3为本发明一实施例的电子组件的剖面结构示意图。
图4为本发明另一实施例的电子组件的剖面结构示意图。
图5为本发明又一实施例的电子组件的剖面结构示意图。
图6为本发明又一实施例的电子组件的剖面结构示意图。
图7为本发明又一实施例的电子组件的剖面结构示意图。
图8为本发明再一实施例的电子组件的剖面结构示意图。
图9为本发明一实施例的电子组件的制造方法的流程图。
图10至15分别是本发明一实施例的电子组件的制造方法于各步骤所形成的剖面示意图。
图16为本发明另一实施例的连接电极的制造方法的流程图。
图17为本发明另一实施例的连接电极的制造方法的流程图。
图18为本发明另一实施例的连接电极的制造方法的流程图。
图19为本发明又一实施例的连接电极的制造方法的流程图。
图20为本发明一实施例的转置组件的结构剖面示意图。
图21为本发明一实施例的微元件的转置方法的流程图。
图22至25分别是本发明一实施例的微元件的转置方法于各步骤所形成的剖面示意图。
其中,附图标记:
100电子组件 110电路基板
111底板 112钝化层
120连接电极 121第一透明导电层
121a第一透明导电薄膜 121b第一透明导电图案
121s表面 122s表面
122金属层 122a表面
123第二透明导电层 122s表面
123s表面 130微元件
140焊料 150保护层
200转置组件 210弹性吸头
210a第一表面 210b第二表面
211凸部 220帮浦件
A-A剖线 A1接触区段
A2贯穿区段 M1微结构
H1通孔 F1气孔
P1颗粒 T1第一突起
T2第二突起 W1接触窗
TFT主动元件 D1汲极
S1、S2、S21a~S21d、S22a、S22b、S23a、S23b、S3、
S4、S41、S42、S5、S51、S52、S6S7、SS、SS1、SS2步骤
具体实施方式
图1为本发明一实施例的电子组件的结构俯视示意图。图2为对应于图1之A-A剖线的电子组件的截面示意图。请参阅图1,电子组件100包括电路基板110、连接电极120、微元件130以及焊料140。其中,连接电极120位于电路基板110上。焊料140位于连接电极120与微元件130之间,并且焊料140将微元件130固着于连接电极120上,使得微元件130与连接电极120电性连接。在一些实施例中,微元件130可以是但不限于微发光二极管(micro lightemitting diode,micro-led)、微集成电路(micro integrated circuit,micro-IC)等。
在一些实施例中,电路基板110包括底板111、主动元件TFT及钝化层112。主动元件TFT位于底板111上,且钝化层112覆盖于底板111与主动元件TFT上。于此,钝化层112可具有至少一个接触窗W1,接触窗W1位于对应的主动元件TFT上。部分的连接电极120经由接触窗W1而贯穿钝化层112以与主动元件TFT电性连接。详细而言,连接电极120包括接触区段A1以及贯穿区段A2。接触区段A1外露于钝化层112,贯穿区段A2的一端与接触区段A1耦接且位于接触窗W1内,而贯穿区段A2的另一端耦接主动元件TFT(例如是汲极D1)。
在一些实施例中,底板111的材料可以是但不限于硅基板、玻璃基板、石英基板或是高分子基板。
在一些实施例中,钝化层112的材料可以是但不限于氮化硅(SiNx)、氧化硅(SiOx)或其组合。
在一些实施例中,连接电极120的结构可以是单层或者是双层以上之迭层。若连接电极120为迭层结构,则位于接触区段A1或是贯穿区段A2的层数、层别及材料种类并不特别受限。以下详述各实施态样。
为了便于说明,于图3中仅绘示图2中之电路基板110、连接电极120及焊料140。于此实施例中,如图3所绘示,连接电极120具有第一透明导电层121,且第一透明导电层121的表面121s具有多个微米或纳米级颗粒P1且位于相对电路基板110的一侧。此些微米或纳米级颗粒P1即为第一透明导电层121的表面121s突起或凹陷的微结构,且此些微结构的尺寸(颗粒P1最宽处之长度)系介于纳米至微米之间。
第一透明导电层121的表面121s可以通过非完全退火方法及蚀刻方法来进行表面粗糙化处理。在一些实施例中,非完全退火方法的退火温度介于150度(℃)至180度(℃)之间。在另一些实施例中,退火时间介于5分钟至120分钟。于此,第一透明导电层121的表面121s可以形成此些微米或纳米级颗粒P1。换言之,此些微米或纳米级颗粒P1即为第一透明导电层121的表面121s经由粗糙化处理所产生微结构。其中,各微米或纳米级颗粒P1的形状可以是但不限于是球形、尖形、块形或杆形等。在一些实施例中,颗粒P1的尺寸介于10nm至1000nm之间。当焊料140施加于连接电极120上时,焊料140与第一透明导电层121的表面121s接触,从而第一透明导电层121的表面121s的微米或纳米级颗粒P1中的多个(例如是全部的微米或纳米级颗粒P1或是部分的微米或纳米级颗粒P1)可以嵌入焊料140的底部,以增加焊料140与连接电极120之间的接触面积以及附着力。
在一些实施例中,第一透明导电层121的材料可以是氧化锌(Zinc oxide,ZnO)、氧化铟锌(Indium-Zinc Oxide,IZO)、氧化镓锌(Gallium-Zinc Oxide,GaZnO)、氧化锌锡(Zinc-Tin Oxide,ZTO)、氧化铟锡(Indium-Tin Oxide,ITO)等。于本实施例中,第一透明导电层121的材料是氧化铟镓锌。
在另一些实施例中,如图4所绘示,除了第一透明导电层121之外,连接电极120可以更包括金属层122。金属层122与第一透明导电层121连接且位于电路基板110与第一透明导电层121之间。当焊料140施加于连接电极120上时,焊料140与第一透明导电层121的表面121s接触,并且第一透明导电层121的表面121s的微米或纳米级颗粒P1中的多个(例如是全部的微米或纳米级颗粒P1或是部分的微米或纳米级颗粒P1)会嵌入焊料140的底部。即,表面121s与焊料140接触的区域中的微米或纳米级颗粒P1会嵌入焊料140的底部。
在连接电极120的另一些实施例中,如图5所绘示,连接电极120的金属层122系位于第一透明导电层121上且覆盖第一透明导电层121的表面121s。其中,金属层122随着覆盖第一透明导电层121的表面121s上的此些微米或纳米级颗粒P1而起伏,于此,金属层122于相对第一透明导电层121的一侧的表面122s形成多数第一突起T1。于一些实施例中,由于金属层122是沿着第一透明导电层121的表面121s而起伏,所以第一突起T1的形状大致上与微米或纳米级颗粒P1的形状相同,可以是但不限于是球形、尖形、块形或杆形等。于另一些实施例中,且第一突起T1的尺寸介于10nm至1000nm之间。当焊料140施加于连接电极120上时,焊料140与金属层122的表面122s接触。依此,金属层122的表面122s的第一突起T1中的多个(例如是全部的第一突起T1或是部分的第一突起T1)可以嵌入焊料140的底部。即,金属层122的表面122s与焊料140接触的区域中的微米或纳米级颗粒P1会嵌入焊料140的底部。
在又一些实施例中,除了第一透明导电层121与金属层122之外,连接电极120可以更包括第二透明导电层123。于此一实施例中,如图6所绘示,金属层122位于第一透明导电层121与第二透明导电层123之间,而第二透明导电层123与金属层122连接且位于电路基板110与金属层122之间。换言之,连接电极120可以更包括依序形成于电路基板110上的第二透明导电层123、金属层122及第一透明导电层121。当焊料140施加于连接电极120上时,焊料140仍与第一透明导电层121的表面121s接触。依此,第一透明导电层121的表面121s的微米或纳米级颗粒P1中的多个可以嵌入焊料140的底部。
此外,于一些实施例中,电子组件100可视产品需求而选择性包括保护层150。如图7所绘示,详细来说,保护层150用以保护第一透明导电层121的表面121s的多个微米或纳米级颗粒P1。保护层150位于第一透明导电层121之上且覆盖第一透明导电层121的表面121s,因此保护层150覆盖此些微米或纳米级颗粒P1而沿着第一透明导电层121的表面121s而起伏,于此,保护层150于相对第一透明导电层121的一侧的表面形成多数微结构M1。于另一些实施例中,由于保护层150是沿着第一透明导电层121的表面121s而起伏,所以微结构M1的形状大致上与微米或纳米级颗粒P1的形状相同,可以是但不限于是球形、尖形、块形或杆形等。于另一些实施例中,微结构M1的尺寸介于10nm至1000nm之间。
值得说明的是,在一些实施例中,保护层150可以形成在不同实施态样的连接电极120上。不过,在又一些实施例中,连接电极120上也可以不用形成保护层150。
于一些实施例中,保护层150的材料可以是但不限于透明导电材料,例如是氧化锌、氧化铟锌、氧化镓锌、氧化锌锡、氧化铟锡等。于本实施例中,透明导电材料是氧化铟镓锌。此外,保护层150的材料可以与第一透明导电层121的材料相同,也可以与第一透明导电层121的材料不同。不过,本发明并不对此加以限制。
在连接电极120的另一些实施例中,如图8所绘示,金属层122位于第一透明导电层121与第二透明导电层123之间,第二透明导电层123位于金属层122之上,而第一透明导电层121与金属层122连接且位于电路基板110与金属层122之间。换言之,连接电极120可以更包括依序形成于电路基板110上的第一透明导电层121、金属层122及第二透明导电层123。由于金属层122随着覆盖第一透明导电层121的表面121s的此些微米或纳米级颗粒P1而起伏,于此,金属层122于相对第一透明导电层121的一侧的表面122s形成多数第一突起T1。而且,由于第二透明导电层123随着覆盖金属层122的表面122s的此些第一突起T1而起伏,于此,第二透明导电层123于相对金属层122的一侧的表面123a形成多数第二突起T2。
在一些实施例中,由于金属层122是沿着第一透明导电层121的表面121s而起伏,所以第一突起T1的形状大致上与微米或纳米级颗粒P1的形状相同,可以是但不限于是球形、尖形、块形或杆形。在一些实施例中,且第一突起T1的尺寸介于10nm至1000nm之间。此外,由于第二透明导电层123是沿着金属层122的表面122s而起伏,所以第二突起T2的形状大致上与第一突起T1的形状相同,且第二突起T2的尺寸介于10nm至1000nm之间。当焊料140施加于连接电极120上时,焊料140与第二透明导电层123的表面123s接触。依此,第二透明导电层123的表面123s的第二突起T2中的多个可以嵌入焊料140的底部。
图9为本发明一实施例的电子组件的制造方法的流程图。请参阅图9,电子组件的制造方法包括提供一电路基板110(步骤S1)、形成连接电极120于电路基板110上(步骤S2)、形成焊料140于连接电极120之上(步骤S3)、转置微元件130于焊料140上(步骤S4)以及以焊料140固着微元件130(步骤S5)。其中,连接电极120之相对电路基板110的一侧的表面具有多数微突起,并且连接电极120具有第一透明导电层121。
于步骤S1中,在一些实施例中,电路基板110可以是但不限于主动元件数组基板,其可包括底板111、主动元件TFT及具有接触窗W1的钝化层112。
在一些实施例中,步骤S2包括形成第一透明导电薄膜121a于电路基板110上(步骤S21a)、图案化第一透明导电薄膜121a以形成第一透明导电图案121b(步骤S21b)、对第一透明导电图案121b进行非完全退火(步骤S21c)、以及蚀刻第一透明导电图案121b的相对电路基板110的一侧的表面121s以形成一第一透明导电层(步骤S21d)。
于步骤S21a的一些实施例中,如图10所绘示,可通过蒸镀法(Evaporation)、化学气相沉积法(Chemical vapor deposition,CVD)或溅镀法(sputtering)等方法沉积第一透明导电材料于电路基板110上,以形成第一透明导电薄膜121a。值得说明的是,第一透明导电材料可以是氧化锌、氧化铟锌、氧化镓锌、氧化锌锡、氧化铟锡等。于本实施例中,第一透明导电材料是氧化铟镓锌。不过,本发明并不对此加以限制。
于步骤S21b的一些实施例中,如图11所绘示,经由微影蚀刻制程将整层的第一透明导电薄膜121a图案化,以形成岛状的第一透明导电图案121b。
于步骤S21c的一些实施例中,对第一透明导电图案121b进行非完全退火(或称为不完全退火)(subcritical annealing),使得第一透明导电图案121b尚未完全转为结晶化结构而呈现多晶结构。于一些实施例中,退火温度介于150度(℃)至180度(℃)之间,且退火时间介于5分钟至120分钟。
于步骤S21d的一些实施例中,如图12所绘示,对第一透明导电图案121b的表面进行表面粗糙化处理。可以通过浸泡或是喷洒等方式在第一透明导电图案121b的表面施以化学溶液来蚀刻。其中,蚀刻处理时间大约是60秒至70秒之间。化学溶液可以是酸性溶液或碱性溶液,例如是但不限于草酸(oxalic acid)、盐酸(hydrochloric acid)、硝酸(nitricacid)、ITO蚀刻液、或是其两者以上之混和溶液。依此,第一透明导电图案121b的表面经由粗糙化处理后形成第一透明导电层121,且第一透明导电层121的相对电路基板110的一侧的表面121s形成此些微米或纳米级颗粒P1。于此实施例中,此些微米或纳米级颗粒P1即为连接电极120之多个微突起,用以增加后续所施加的焊料140与连接电极120之间的接触面积以及附着力。
于步骤S3中,如图13所绘示,将焊料140施加于连接电极120的第一透明导电层121之上。
于步骤S4中,如图14所绘示,将微元件130转置于焊料140上。于一些实施例中,可以通过转置组件200拾取至少一微元件130放置于形成焊料140上。
于一些实施例中,请参阅图14及图15,步骤S5包括熔融焊料140(步骤S51)以及固化熔融的焊料140以使微元件130通过焊料140固着于连接电极120上(步骤S52)。
于步骤S51中,请参阅图14,通过提高温度以使焊料140呈现熔融状态,使得熔融的焊料140可以陷入此些微米或纳米级颗粒P1中的多数者之间。
于步骤S52中,请参阅图15,通过降温以使熔融的焊料140得以固化,第一透明导电层121的表面121s的微米或纳米级颗粒P1中的多个可以嵌入焊料140的底部,而焊料140的顶部固着于微元件130的底面,以致而微元件130能够通过焊料140而固着于连接电极120上。依此,增加焊料140与连接电极120之间的接触面积以及附着力。
须说明的是,连接电极120的结构也可以是双层以上之迭层。
在另一些实施例中,请参阅图16以及再次配合参阅图4。
于一实施例中,步骤S2可以更包括形成金属薄膜于电路基板上(步骤S22a)以及图案化金属薄膜以形成金属层(步骤S22b)。其中,步骤S22a以及步骤S22b在形成第一透明导电层121(步骤S21a、S21b、S21c及S21d)之前。换言之,先于电路基板110上形成金属层122,再于金属层122上形成第一透明导电层121。以下详细说明。
于步骤S22a中,可通过喷涂(spray)或溅镀法等方法沉积金属材料于电路基板110上,以形成整层的金属薄膜。
接着,于步骤S22b中,经由微影蚀刻制程将整层的金属薄膜图案化,以形成岛状的金属层122。
接下来,在金属层122上进行步骤S21a、S21b、S21c及S21d,以在金属层122上形成第一透明导电层121。步骤S21a、S21b、S21c及S21d与前述大致相同,故于此不再赘述。依此,金属层122位于电路基板110与第一透明导电层121之间。
接着,在步骤S2之后,可以接续进行步骤S3、步骤S4及步骤S5,焊料140可以与连接电极120的第一透明导电层121的表面121s接触,因此于熔融时,熔融的焊料140可以陷入此些微米或纳米级颗粒P1中的多数者之间。当熔融的焊料140固化后,此些微米或纳米级颗粒P1中的多个即嵌入焊料140的底部,而焊料140的顶部固着于微元件130的底面,以致微元件130能够通过焊料140固着于连接电极120上。
承此,在连接电极120的又一些实施例中,其中,连接电极120的金属层122系位于第一透明导电层121上且覆盖第一透明导电层121的表面121s。图17为本发明又一实施例的连接电极120的制造方法的流程图。请参阅图17以及再次配合参阅图5。
于此一实施例,步骤S22b在步骤S21a、S21b、S21c及S21d之后。换言之,先于电路基板110上形成第一透明导电层121,再于电路基板110及第一透明导电层121上形成金属层122。于此,金属层122于相对第一透明导电层121的一侧的表面122s形成多数第一突起T1。其中,由于金属层122是沿着第一透明导电层121的表面121s而起伏,因此金属层122于相对第一透明导电层121的一侧的表面122s形成多个与微米或纳米级颗粒P1的形状相同的第一突起T1。
接着,在进行步骤S2之后,可以接续进行步骤S3、步骤S4及步骤S5,焊料140可以与连接电极120的金属层122的表面122s接触,且熔融的焊料140可以陷入此些第一突起T1中的多数者之间,亦即此些第一突起T1中的多个可以嵌入焊料140的底部。当熔融的焊料140固化后,微元件130能够通过焊料140固着于连接电极120上。
在又一些实施例中,除了第一透明导电层121与金属层122之外,连接电极120可以更包括第二透明导电层123。其中,金属层122位于第一透明导电层121与第二透明导电层123之间,而第二透明导电层123与金属层122连接且位于电路基板110与金属层122之间。图18为本发明另一实施例的连接电极120的制造方法的流程图。请参阅图18以及再次配合参阅图6。
于此一实施例,步骤S2可以更包括形成第二透明导电薄膜于电路基板上(步骤S23a)以及图案化第二透明导电薄膜以形成第二透明导电层123(步骤S23b)。其中,于步骤S2中,先进行步骤S23a以及步骤S23b,接着进行步骤S22a以及步骤S22b,而后再进行步骤S21a、S21b、S21c及S21d。换言之,先于电路基板110上形成第二透明导电层123,再于第二透明导电层123上形成金属层122,而后于金属层122上形成第一透明导电层121。以下详细说明。
于步骤S23a中,可通过蒸镀法(Evaporation)、化学气相沉积法(Chemical vapordeposition,CVD)或溅镀法(sputtering)等方法沉积第二透明导电材料于电路基板110上,以形成第二透明导电薄膜122a。需说明的是,第二透明导电材料可以与第一透明导电材料相同,也可以与第一透明导电材料不同。
接着,于步骤S23b中,经由微影蚀刻制程将整层的第二透明导电薄膜图案化,以形成岛状的第二透明导电层123。
接下来,在第二透明导电层123上进行步骤S22a、S22b、S21a、S21b、S21c及S21d,以在第二透明导电层123上形成金属层122且在金属层122上形成第一透明导电层121。步骤S22a、S22b、S21a、S21b、S21c及S21d与前述大致相同,故于此不再赘述。依此,金属层122位于电路基板110与第一透明导电层121之间,且第二透明导电层123与电路基板110接触。于此,包括有依序形成于电路基板110上的第二透明导电层123、金属层122及第一透明导电层121的连接电极120大致上已完成。
接着,在步骤S2之后,可以接续进行步骤S3、步骤S4及步骤S5,焊料140可以与连接电极120的第一透明导电层121的表面121s接触,且熔融的焊料140可以陷入此些微米或纳米级颗粒P1中的多数者之间,亦即此些微米或纳米级颗粒P1中的多个可以嵌入焊料140的底部。当熔融的焊料140固化后,微元件130能够通过焊料140固着于连接电极120上。
另外,于另一些实施例,电子组件的制造方法可以视产品需求而选择性包括形成保护薄膜于第一透明导电层121的表面121s上(步骤SS1)以及图案化保护薄膜以形成保护层150(步骤SS2)。请再参阅图18以及配合参阅图7。其中,先进行步骤S2,接着,在进行步骤SS1及步骤SS2,而后再进行步骤S3、S4、S5。换言之,先于电路基板110上形成连接电极120后,再于连接电极120的第一透明导电层121上形成保护层150,而后再接续于保护层150上形成焊料140、转置微元件及以焊料140固着微元件130。以下详细说明。
于步骤SS1中,可通过蒸镀法、化学气相沉积法或溅镀法等方法沉积透明导电材料于连接电极120的第一透明导电层121上,以形成保护薄膜。需说明的是,保护层的材料可以与第一透明导电材料相同,也可以与第一透明导电材料不同。接着,于步骤SS2中,经由微影蚀刻制程将整层的保护薄膜图案化,以形成岛状的保护层150。此外,步骤SS1及步骤SS2系为选择性的步骤。值得说明的是,在一些实施例中,步骤SS1及步骤SS2可以将保护层150形成在不同实施态样的连接电极120上。不过,在另一些实施例中,电子组件的制造方法可以不包括步骤SS1及步骤SS2。也就是说,连接电极120上也可以不用形成保护层150。
此外,在连接电极120的另一些实施例中,其中,连接电极120的金属层122位于第一透明导电层121与第二透明导电层123之间,第二透明导电层123位于金属层122之上,而第一透明导电层121与金属层122连接且位于电路基板110与金属层122之间。图19为本发明又一实施例的连接电极120的制造方法的流程图。请参阅图19以及再次配合参阅图8。
于此一实施例,步骤S23a以及步骤S23b在步骤S22a、步骤S22b、步骤S21a、步骤S21b、步骤S21c及步骤S21d之后。换言之,先于电路基板110上形成第一透明导电层121,再于电路基板110及第一透明导电层121上形成金属层122,而后在于金属层122上形成第二透明导电层123。于此,金属层122于相对第一透明导电层121的一侧的表面122s形成多数第一突起T1。而且,由于第二透明导电层123随着覆盖金属层122的表面122s的此些第一突起T1而起伏,于此,第二透明导电层123于相对金属层122的一侧的表面123a形成多数第二突起T2。
其中,由于金属层122是沿着第一透明导电层121的表面121s而起伏,因此金属层122于相对于第一透明导电层121的一侧的表面122s形成多个与微米或纳米级颗粒P1的形状相同的第一突起T1。而且,由于第二透明导电层123是沿着金属层122的表面122s而起伏,因此第二透明导电层123于相对于金属层122一侧的表面123a形成多个与第一突起T1的形状相同的第二突起T2。
接着,在步骤S2之后,可以接续进行步骤S3、步骤S4及步骤S5,焊料140可以与连接电极120的第二透明导电层123的表面123s接触,且熔融的焊料140可以陷入此些第一突起T2中的多数者之间,亦即此些第一突起T2中的多个可以嵌入焊料140的底部。当熔融的焊料140固化后,微元件130能够通过焊料140固着于连接电极120上。
图20为本发明一实施例的转置组件的结构剖面示意图。请参阅图20,转置组件200包括弹性吸头210及帮浦件220,其中帮浦件220与弹性吸头210耦接。
在此实施例中,弹性吸头210具有第一表面210a以及相对于第一表面210a的第二表面210b。其中,第一表面210a具有至少一凸部211,而第二表面210b为一大致平坦表面。此外,第一表面210a更具有至少一通孔H1,且各通孔H1系由弹性吸头200的第一表面210a穿过各凸部211而贯穿至弹性吸头200的第二表面210b。换言之,各通孔H1系位于对应凸部211处且贯穿凸部211。
在一些实施例中,弹性吸头210可以是藉由在模具(未绘示)内灌注高分子材料并且塑型而成的。其中,模具可以是两个具有不同微结构且对向设置的基板。具体来说,可以通过微影蚀刻制程在两个硅基板的表面分别形成凹槽以及凸柱,且凹槽的槽宽大于凸柱的柱宽。将具有凹槽的硅基板以及具有凸柱的硅基板相对,并且使凸柱与凹槽对位以及使凸柱的顶面抵触凹槽的槽底面。而后,于两硅基板间灌注高分子材料,大致上即可形成弹性吸头210。须说明的是,此两对向设置的硅基板之间的空隙极为弹性吸头210的形状,且硅基板上的凸柱的柱宽即为通孔H1的孔径。
在一些实施例中,弹性吸头210的材料可以是但不限于具有黏性及弹性的高分子有机硅化合物材料,例如为聚二甲基硅氧烷(Polydimethylsiloxane,PDMS)或模塑硅氧树脂(Moldable Silicone,MS)等柔软的材料。
帮浦件220与弹性吸头210的平坦的第二表面210b耦接。于一些实施例中,弹性吸头210可藉由其黏性而黏附于帮浦件220,以使弹性吸头210的第二表面210b耦接于帮浦件220
其中,帮浦件220具有至少一气孔F1,并且气孔F1能与通孔H1连通。具体来说,帮浦件220能够藉由气孔F1流通气流,也就是说,可以将空气经由气孔F1而抽取气体或是吹送气体。须说明的是,气孔F1的数量与位置并不一定与通孔H1的数量和位置一致。当帮浦件220在抽取气体或是吹送气体时,气体能够经由气孔F1及通孔H1而流通。
图21为本发明一实施例的微元件的转置方法的流程图。请参阅图21以及配合参阅图22至图25。微元件的转置方法可以包括形成焊料140于连接电极120上(步骤S3)、转置微元件130于焊料140上(步骤S4)、以焊料140固着微元件130于连接电极120上(步骤S5)、驱动帮浦件220以通入气体至此些通孔H1(步骤S6)以及分离微元件130与弹性吸头210(步骤S7)。其中,步骤S3、S4及S5与前述大致相同,故相同的说明于此些实施例中不再赘述。
首先,如图22所绘示,于步骤S3中,将焊料140施加于连接电极120之上。为了便于说明,于图22中仅简单绘示连接电极120,而省略其分层。其中,焊料140可视不同实施例的连接电极120而与连接电极120的第一透明导电层121的多数微米或纳米级颗粒P1、金属层122的多数第一突起T1或者是第二透明导电层123的多数第二突起T2接触。
接着,如图23所绘示,在其中一些实施例中,步骤S4可以更包括通过转置组件200拾取微元件130(步骤S41)以及通过转置组件200将拾取的微元件130移动于焊料上(步骤S42)。详细来说,于步骤S41中,将转置组件200移动到微元件130的上方,使转置组件200的弹性吸头210的各凸部211对应各个微元件130。接着,转置组件200垂直向下移动,使得弹性吸头210的各凸部211接触各个微元件130,以黏取各微元件130。于其中又一些实施例中,此时,帮浦件220可以产生负压以通过气孔F1抽取气体,使得气体可以在气孔F1及通孔H1中流通,从而除了弹性吸头210的黏着力之外,微元件130可以更通过帮浦件220的吸力而更佳地附着于各凸部211。
接着,如图24所绘示,于步骤S42中,转置组件200可以移动所黏取及/或吸取的微元件130且放置在形成有焊料140的连接电极120上。
接着,进行步骤S5,请再次参阅图24及配合参阅图14、图15。须说明的是,步骤S51及S51与前述大致相同,故于此不再赘述。其中,熔融的焊料140可视不同实施例的连接电极120而陷入连接电极120的第一透明导电层121的多数微米或纳米级颗粒、金属层122的多数第一突起T1或者是第二透明导电层123的多数第二突起T2之间。换言之,第一透明导电层121的微米或纳米级颗粒P1、金属层122的多数第一突起T1或者是第二透明导电层123的多数第二突起T2中的多个可以嵌入焊料140的底部,从而增加焊料140与连接电极120之间的接触面积以及附着力。依此,微元件130能与电路基板110上的连接电极120电性连接。
接着,于步骤S6中,驱动帮浦件220以将气体由气孔F1通入至此些通孔H1,使得弹性吸头210的各凸部211与各微元件130之间产生小缝隙。换言之,弹性吸头210的各凸部211与各微元件130些微地分开,藉以便于使弹性吸头210与微元件130之间分离。
而后,于步骤S7中,如图25所绘示,于气体的通入过程中,将微元件130与弹性吸头210的各凸部211分离。依此,转置组件200离开微元件130时,不会拉扯微元件130而致使微元件130发生歪斜、位移或是脱落等情况。
综上所述,本发明实施例的电子组件、转置组件、电子组件的制造方法及微元件的转置方法,其通过在连接电极的表面形成多数微突起以使焊料能更稳固地将转置的微元件与连接电极相互固着。依此,连接电极表面的多数微突起嵌入于焊料的底部,藉以增加焊料与连接电极之间的接触面积以及附着力。因此,能避免转置组件于转置过程中离开微元件时,因焊料与连接电极接着不佳而使微元件歪斜、位移或是脱落等情况发生,进而能提高电子组件的良率。在一些实施例中,本发明实施例的转置组件及微元件的转置方法,其通过弹性吸头来黏取微元件,由于弹性吸头具有黏性及弹性而且为柔软材料,因此弹性吸头不易与微元件碰撞而导致微元件受损。在一些实施例中,本发明实施例的转置组件及微元件的转置方法,更可通过于通孔中抽取气体或是吹送气体以利于弹性吸头更加地拾取或放置微元件。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明权利要求的保护范围。
Claims (30)
1.一种电子组件,其特征在于,包括:
一电路基板;
一连接电极,位于该电路基板上,该连接电极具有一第一透明导电层,以及该第一透明导电层的一表面位于相对该电路基板的一侧且具有多个微米或纳米级颗粒;
一微元件,与该连接电极电性连接;以及
一焊料,位于该连接电极与该微元件之间,固着该微元件于该连接电极上。
2.根据权利要求1所述的电子组件,其特征在于,各该微米或纳米级颗粒的尺寸介于10nm至1000nm之间。
3.根据权利要求1所述的电子组件,其特征在于,该连接电极更包括一金属层,且该金属层位于该电路基板与该第一透明导电层之间。
4.根据权利要求3所述的电子组件,其特征在于,该连接电极更包括一第二透明导电层,且该第二透明导电层位于该电路基板与该金属层之间。
5.根据权利要求1至4中任一项所述的电子组件,其特征在于,该些微米或纳米级颗粒中的多个嵌入该焊料的底部。
6.根据权利要求4所述的电子组件,其特征在于,更包括一保护层,该保护层覆盖该第一透明导电层的该表面,且该保护层覆盖该些微米或纳米级颗粒而沿着该第一透明导电层的该表面而起伏。
7.根据权利要求1所述的电子组件,其特征在于,该连接电极更包括一金属层,覆盖该第一透明导电层的该表面,且该金属层随着覆盖该些微米或纳米级颗粒而于相对该第一透明导电层的一侧的表面形成多数第一突起。
8.根据权利要求7所述的电子组件,其特征在于,各该第一突起的尺寸介于10nm至1000nm之间。
9.根据权利要求7或8所述的电子组件,其特征在于,该些第一突起中的多个嵌入该焊料的底部。
10.根据权利要求7所述的电子组件,其特征在于,该连接电极更包括一第二透明导电层,覆盖该金属层的该表面,该第二透明导电层随着覆盖该些第一突起而于相对该金属层的一侧的表面形成多数第二突起。
11.根据权利要求10所述的电子组件,其特征在于,各该第二突起的尺寸介于10nm至1000nm之间。
12.根据权利要求10或11所述的电子组件,其特征在于,该些第二突起中的多个嵌入该焊料的底部。
13.根据权利要求1所述的电子组件,其特征在于,该表面通过非完全退火方法及蚀刻方法形成该些微米或纳米级颗粒。
14.根据权利要求13所述的电子组件,其特征在于,该非完全退火方法的退火温度介于150度℃至180度℃之间且退火时间介于5分钟至120分钟。
15.根据权利要求1所述的电子组件,其特征在于,该电路基板包括:
一底板;
一主动元件,位于该底板上;以及
一钝化层,覆盖于该底板与该主动元件上;
其中,该连接电极包括:
一接触区段,对应该主动元件位于该钝化层上;以及
一贯穿区段,贯穿该钝化层,该贯穿区段的一端耦接该接触区段,以及该贯穿区段的另一端耦接该主动元件。
16.一种电子组件的制造方法,其特征在于,包括:
提供一电路基板;以及
形成一连接电极于该电路基板上,其中该连接电极的相对于该电路基板的一侧的一表面具有多数微突起,并且形成该连接电极于该电路基板上的步骤包括:
形成一第一透明导电薄膜于一电路基板上;
图案化该第一透明导电薄膜以形成一第一透明导电图案;
对该第一透明导电图案进行非完全退火;以及
蚀刻该第一透明导电图案的相对该电路基板的一侧的表面以形成一第一透明导电层,以使第一透明导电层的表面具有多个微米或纳米级颗粒。
17.根据权利要求16所述的电子组件的制造方法,其特征在于,更包括:
形成一焊料于该连接电极之上;
转置一微元件于该焊料上;以及
以该焊料固着该微元件。
18.根据权利要求17所述的电子组件的制造方法,其特征在于,该些微突起为该些微米或纳米级颗粒。
19.根据权利要求18所述的电子组件的制造方法,其特征在于,形成该连接电极于该电路基板上的步骤更包括:
形成一金属薄膜于该电路基板上;以及
图案化该金属薄膜以形成位于该电路基板与该第一透明导电层之间的一金属层,其中该微元件通过该焊料固着于该第一透明导电层上,且该些微米或纳米级颗粒中的多个嵌入该焊料的底部。
20.根据权利要求19所述的电子组件的制造方法,其特征在于,形成该连接电极于该电路基板上的步骤更包括:
形成一第二透明导电薄膜于该电路基板上;以及
图案化该第二透明导电薄膜以形成位于该电路基板与该金属层之间的一第二透明导电层。
21.根据权利要求20所述的电子组件的制造方法,其特征在于,更包括:
形成一保护薄膜于该第一透明导电层与该电路基板上;以及
图案化该保护薄膜以形成位于该第一透明导电层的该表面上的一保护层,其中该保护层随着覆盖该些微米或纳米级颗粒而于相对该金属层的一侧的表面形成多数微结构,其中,该焊料形成于该保护层上,该些微突起为该些微结构,且该些微结构中的多个嵌入该焊料的底部。
22.根据权利要求17所述的电子组件的制造方法,其特征在于,形成该连接电极于该电路基板上的步骤在形成该第一透明导电薄膜于该电路基板上的步骤之后,更包括:
形成一金属薄膜于该电路基板与该第一透明导电层上;以及
图案化该金属薄膜以形成位于该第一透明导电层上的一金属层,其中该金属层随着覆盖该些微米或纳米级颗粒而于相对该第一透明导电层的一侧的表面形成多数第一突起,该些微突起为该些第一突起,且该些第一突起中的多个嵌入该焊料的底部。
23.根据权利要求17所述的电子组件的制造方法,其特征在于,形成该连接电极于该电路基板上的步骤在形成该第一透明导电薄膜于该电路基板上的步骤之后,更包括:
形成一金属薄膜于该电路基板与该第一透明导电层上;
图案化该金属薄膜以形成位于该第一透明导电层上的一金属层,其中该金属层随着覆盖该些微米或纳米级颗粒而于相对该第一透明导电层的一侧的表面形成多数第一突起;
形成一第二透明导电薄膜于该电路基板与该金属层的该表面;以及
图案化该第二透明导电薄膜以形成位于该金属层上的一第二透明导电层,其中该第二透明导电层随着覆盖该些第一突起而于相对该金属层的一侧的表面形成多数第二突起,其中,该焊料形成于该第二透明导电层上,该些微突起为该些第二突起,且该些第二突起中的多个嵌入该焊料的底部。
24.根据权利要求17所述的电子组件的制造方法,其特征在于,以该焊料固着该微元件于该连接电极的步骤包括:
熔融该焊料,以使熔融的该焊料陷入该些微突起中的多数者之间;以及
固化熔融的该焊料以使该微元件通过该焊料固着于该连接电极上。
25.根据权利要求16至24中任一项所述的电子组件的制造方法,其特征在于,在对该第一透明导电图案进行非完全退火的步骤中退火温度介于150度℃至180度℃之间,退火时间介于5分钟至120分钟。
26.一种微元件的转置方法,其特征在于,包括:
形成至少一焊料于至少一连接电极上,其中各该连接电极具有一第一透明导电层,并且该第一透明导电层的表面具有多个微米或纳米级颗粒;
通过一转置组件拾取至少一微元件,其中该转置组件包括一弹性吸头以及一帮浦件,该弹性吸头的一表面具有分别拾取该至少一微元件的至少一凸部,该弹性吸头的另一表面耦接该帮浦件,该帮浦件具有至少一气孔,该弹性吸头具有连通该至少一气孔的至少一通孔,并且各该通孔由该弹性吸头的该表面穿过该至少一凸部中之一贯穿至该弹性吸头的另一表面;
通过该转置组件将拾取的该至少一微元件移动于该至少一焊料上;
以该至少一焊料将该至少一微元件固着于该至少一连接电极上,其中各该连接电极的该些微米或纳米级颗粒中的多数者嵌入对应的该焊料的底部;
驱动该帮浦件以通入气体至该至少一通孔;以及
于该气体的通入过程中,分离该至少一微元件与该弹性吸头。
27.根据权利要求26所述的微元件的转置方法,其特征在于,以该至少一焊料将该至少一微元件固着于该至少一连接电极上的步骤之后,更包括:
熔融该至少一焊料,以使该些微米或纳米级颗粒中的多数者嵌入对应的该焊料的底部;以及
固化该至少一焊料以使该至少一微元件通过该至少一焊料固着于该至少一连接电极上。
28.一种转置组件,其特征在于,包括:
一弹性吸头,该弹性吸头的一表面具有至少一凸部,其中该弹性吸头具有至少一通孔,并且各该通孔由该弹性吸头的该表面穿过该至少一凸部中之一贯穿至该弹性吸头的另一表面;以及
一帮浦件,耦接该弹性吸头的该另一表面,其中该帮浦件具有至少一气孔,并且该至少一气孔连通于该至少一通孔。
29.根据权利要求28所述的转置组件,其中该弹性吸头具有黏性。
30.根据权利要求28所述的转置组件,其中该弹性吸头的材质为聚二甲基硅氧烷或模塑硅氧树脂。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106105635A TWI691045B (zh) | 2017-02-20 | 2017-02-20 | 電子組件、電子組件的製造方法及微元件的轉置方法 |
TW106105635 | 2017-02-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107068693A true CN107068693A (zh) | 2017-08-18 |
CN107068693B CN107068693B (zh) | 2019-11-19 |
Family
ID=59603494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710282050.7A Active CN107068693B (zh) | 2017-02-20 | 2017-04-26 | 电子组件及其制造方法、转置元件及微元件的转置方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10438911B2 (zh) |
CN (1) | CN107068693B (zh) |
TW (1) | TWI691045B (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107818931A (zh) * | 2017-09-30 | 2018-03-20 | 厦门市三安光电科技有限公司 | 半导体微元件的转移方法及转移装置 |
CN109585580A (zh) * | 2018-11-08 | 2019-04-05 | 晋能光伏技术有限责任公司 | 一种基于层叠结构的异质结高效太阳能电池生产方法 |
CN109585573A (zh) * | 2018-11-05 | 2019-04-05 | 武汉三工智能装备制造有限公司 | Hit电池及其金属栅线印刷方法 |
CN109950367A (zh) * | 2017-12-20 | 2019-06-28 | 美科米尚技术有限公司 | 元件转移方法 |
CN111128819A (zh) * | 2018-10-31 | 2020-05-08 | 昆山工研院新型平板显示技术中心有限公司 | 一种微器件转移装置及其制备方法 |
CN113396485A (zh) * | 2019-02-12 | 2021-09-14 | 信越化学工业株式会社 | 微小构造体移载装置、模板头单元、微小构造体移载用模板部件及微小构造体集成部件的移载方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210242108A1 (en) * | 2021-03-26 | 2021-08-05 | Intel Corporation | Technologies for liquid cooling systems |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200426900A (en) * | 2003-05-27 | 2004-12-01 | Seiko Epson Corp | Electronic component mounting method, electronic component mounting structure, electronic component module, and electronic machine |
CN202425073U (zh) * | 2011-11-14 | 2012-09-05 | 美亚奈米科技股份有限公司 | 一种加热组件 |
US20140318837A1 (en) * | 2013-04-26 | 2014-10-30 | Panasonic Corporation | Circuit board interconnection structure and circuit board interconnection method |
CN104587936A (zh) * | 2015-01-30 | 2015-05-06 | 东莞佰鸿电子有限公司 | 一种光化学反应系统 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4542008B2 (ja) * | 2005-06-07 | 2010-09-08 | 株式会社神戸製鋼所 | 表示デバイス |
TW200719426A (en) * | 2005-11-03 | 2007-05-16 | Advanced Semiconductor Eng | Vacuum sucker and alignment apparatus using the same |
TWI293643B (en) | 2005-11-09 | 2008-02-21 | Advanced Semiconductor Eng | Surface mounting method |
TWM295131U (en) * | 2005-11-25 | 2006-08-01 | Tai Ee Mfg Co Ltd | Vacuum-sucking head for taking in electronic components |
CN101395975B (zh) * | 2006-03-14 | 2012-06-13 | 松下电器产业株式会社 | 电子部件安装结构体及其制造方法 |
TWM382693U (en) | 2010-01-29 | 2010-06-11 | Welland Ind Co Ltd | Matrix array components mounting device |
US9314930B2 (en) | 2012-12-14 | 2016-04-19 | LuxVue Technology Corporation | Micro pick up array with integrated pivot mount |
US9136161B2 (en) | 2013-06-04 | 2015-09-15 | LuxVue Technology Corporation | Micro pick up array with compliant contact |
TWI624356B (zh) * | 2013-11-11 | 2018-05-21 | Nippon Steel & Sumitomo Metal Corp | Metal joint structure using metal nanoparticle, metal joint method, and metal joint material |
US9367094B2 (en) | 2013-12-17 | 2016-06-14 | Apple Inc. | Display module and system applications |
KR101727108B1 (ko) * | 2014-12-31 | 2017-04-17 | 엘지디스플레이 주식회사 | 인셀 터치 액정 디스플레이 장치와 이의 제조방법 |
TWM501641U (zh) | 2015-02-11 | 2015-05-21 | Achrolux Inc | 移取設備 |
US10886250B2 (en) * | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
CN108574158B (zh) * | 2017-03-14 | 2020-10-09 | 群创光电股份有限公司 | 显示装置及其制造方法 |
-
2017
- 2017-02-20 TW TW106105635A patent/TWI691045B/zh active
- 2017-04-26 CN CN201710282050.7A patent/CN107068693B/zh active Active
-
2018
- 2018-01-08 US US15/864,102 patent/US10438911B2/en active Active
-
2019
- 2019-08-02 US US16/530,314 patent/US11069638B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200426900A (en) * | 2003-05-27 | 2004-12-01 | Seiko Epson Corp | Electronic component mounting method, electronic component mounting structure, electronic component module, and electronic machine |
CN202425073U (zh) * | 2011-11-14 | 2012-09-05 | 美亚奈米科技股份有限公司 | 一种加热组件 |
US20140318837A1 (en) * | 2013-04-26 | 2014-10-30 | Panasonic Corporation | Circuit board interconnection structure and circuit board interconnection method |
CN104587936A (zh) * | 2015-01-30 | 2015-05-06 | 东莞佰鸿电子有限公司 | 一种光化学反应系统 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107818931A (zh) * | 2017-09-30 | 2018-03-20 | 厦门市三安光电科技有限公司 | 半导体微元件的转移方法及转移装置 |
WO2019062117A1 (zh) * | 2017-09-30 | 2019-04-04 | 厦门市三安光电科技有限公司 | 半导体微元件的转移方法及转移装置 |
CN107818931B (zh) * | 2017-09-30 | 2021-10-19 | 厦门市三安光电科技有限公司 | 半导体微元件的转移方法及转移装置 |
CN109950367A (zh) * | 2017-12-20 | 2019-06-28 | 美科米尚技术有限公司 | 元件转移方法 |
CN109950367B (zh) * | 2017-12-20 | 2021-10-08 | 美科米尚技术有限公司 | 元件转移方法 |
CN111128819A (zh) * | 2018-10-31 | 2020-05-08 | 昆山工研院新型平板显示技术中心有限公司 | 一种微器件转移装置及其制备方法 |
CN111128819B (zh) * | 2018-10-31 | 2023-09-29 | 成都辰显光电有限公司 | 一种微器件转移装置及其制备方法 |
CN109585573A (zh) * | 2018-11-05 | 2019-04-05 | 武汉三工智能装备制造有限公司 | Hit电池及其金属栅线印刷方法 |
CN109585580A (zh) * | 2018-11-08 | 2019-04-05 | 晋能光伏技术有限责任公司 | 一种基于层叠结构的异质结高效太阳能电池生产方法 |
CN113396485A (zh) * | 2019-02-12 | 2021-09-14 | 信越化学工业株式会社 | 微小构造体移载装置、模板头单元、微小构造体移载用模板部件及微小构造体集成部件的移载方法 |
Also Published As
Publication number | Publication date |
---|---|
US20190355685A1 (en) | 2019-11-21 |
CN107068693B (zh) | 2019-11-19 |
US10438911B2 (en) | 2019-10-08 |
US20180240767A1 (en) | 2018-08-23 |
US11069638B2 (en) | 2021-07-20 |
TWI691045B (zh) | 2020-04-11 |
TW201832347A (zh) | 2018-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107068693B (zh) | 电子组件及其制造方法、转置元件及微元件的转置方法 | |
KR101320501B1 (ko) | 플렉서블 표시장치 및 그 제조 방법 | |
CN103840075B (zh) | 微型压电振动能量收集器及其制造方法 | |
CN112397559B (zh) | 可拉伸显示模组及其制备方法 | |
KR102012238B1 (ko) | 전사공정을 이용한 신축가능한 디바이스 제조방법 | |
CN107003763A (zh) | 薄膜触摸传感器及其制造方法 | |
CN108269501A (zh) | 一种可弹性形变显示基板及其制备方法、显示装置 | |
EP1890326A2 (en) | Structure combining an IC integrated substrate and a carrier, and method of manufacturing such structure | |
CN103928473B (zh) | 可挠式显示面板及可挠式显示面板的制作方法 | |
CN110431516B (zh) | 手戴型装置及其制造方法 | |
US10653012B2 (en) | Electronic device and manufacturing method thereof | |
KR101784192B1 (ko) | 플렉서블 기판 상의 전기 회로 | |
US20170060290A1 (en) | Methods for Integrating a Compliant Material with a Substrate | |
US11249603B2 (en) | Method of forming touch control module, touch control module and touch control display device | |
US20180331170A1 (en) | Connection component, connector, manufacturing method for the same and panel component | |
CN109859626B (zh) | 柔性显示屏及其制作方法 | |
JP2005078064A (ja) | フレキシブルパネルの製造方法 | |
CN104900659A (zh) | 一种软性薄膜晶体管阵列基板及其制造方法 | |
JP7119406B2 (ja) | 伸縮性配線基板およびその製造方法 | |
KR102211774B1 (ko) | 터치 스크린 패널의 제조 방법 및 이에 따라 제조된 터치 스크린 패널 | |
CN113899390B (zh) | 一种非对称的强粘易撕传感器及制备方法 | |
CN107907146A (zh) | 液态金属电极、接触传感器及手势识别手套的制备方法 | |
CN207976857U (zh) | 触控面板 | |
WO2015016113A1 (ja) | 電子デバイスの製造方法 | |
KR20170032960A (ko) | 디스플레이 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |