CN107045987A - 具有在源极/漏极区域中的扩散阻挡层的设备 - Google Patents
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Abstract
本发明涉及具有在源极/漏极区域中的扩散阻挡层的设备。一种方法包括定义于一半导体材料中的一沟道区域上方的一栅极电极结构。该半导体材料被凹陷至一源/漏区域中。一第一材料外延生长于该源/漏区域中。该第一材料包括具有一第一浓度的一掺杂种类。一扩散阻挡层形成于该第一材料上方的该源/漏区域中。一第二材料外延生长于该扩散阻挡层上方的该源/漏区域中。该第二材料包括具有大于该第一浓度的一第二浓度的该掺杂种类。
Description
技术领域
本发明通常涉及半导体设备的制造,尤指一种具有在一源/漏区域中的一扩散阻挡层的设备。
背景技术
先进集成电路的制造,例如CPU、存储装置、ASIC(专用集成电路)等,需要在一给定芯片面积中的大量的根据一指定的电路布局的信息,其中,所谓的金属氧化物场效应晶体管(MOSFET或FET)代表了基本决定该集成电路性能的一电路元素的一重要类型。一场效应晶体管为一平面型设备,通常包括一源极区域、一漏极区域、位于该源极区域及该漏极区域之间的一沟道区域,以及位于该沟道区域上方的一栅极电极。通过该场效应晶体管的电流是通过控制施加到该栅极电极的电压予以控制。如果没有电压施加到该栅极电极,则没有电流通过该设备(忽略不需要的相对较小的漏电流)。然而,当一个适当的电压施加至该栅极电极时,该沟道区域变的具有导电性,且电流被允许通过该导电性的沟道区域流至该源极区域与该漏极区域之间。
为了提高场效应晶体管的运行速度,以及增加一集成电路设备上的场效应晶体管的密度,设备的设计者于多年来已大大减小了场效应晶体管的物理尺寸。具体而言,场效应晶体管的沟道长度已明显下降,其提升了场效应晶体管的开关速度。然而,一场效应晶体管的沟道长度的减少同样也缩短了该源极区域及漏极区域之间的距离。在某些情况下,该源极区域与漏极区域之间分隔距离的减小会使得它难以有效抑制该源极区域以及该沟道的电势受到该漏极区域的电势的不利影响。这有时被称为所谓的短沟道效应,其中,该场效应晶体管作为一有源开关的特性会被退化。
相比于一平面结构的场效应晶体管,还有所谓的3D设备,例如,一说明性的鳍式场效应晶体管(FinFET)设备,其为一三维结构。具体而言,在一鳍式场效应晶体管中,形成有一通常为垂直设置的鳍式形状的有源区域,以及一栅极电极包围两侧及该鳍式形状有源区域的一上表面从而形成一三栅极结构,从而使用一个具有三维结构而非平面结构的沟道。在某些情况下,一绝缘覆盖层,例如氮化硅,位于该鳍片的顶部,该FinFET设备只有一双栅极结构。不同于一平面型场效应晶体管,在一鳍式场效应晶体管设备中,一沟道为垂直于该半导体基板的一表面形成以减小该半导体设备的物理尺寸。同样的,在一鳍式场效应晶体管中,位于该设备的漏极区域的结电容将大大减小,以减少至少一些的短沟道效应。
设备的设计者最近在场效应晶体管上使用了沟道应力功能技术以提升这些设备的电气性能,即提升电荷载流子的迁移率。具体而言,这种应力功能技术通常涉及为一PMOS晶体管于该沟道区域中产生一压缩应力。总的来说,鳍式场效应晶体管的应力工程技术已普遍用于在鳍式场效应晶体管的该源漏区域的上方或该源漏区域之中形成应力诱导层的材料。如上所述,当一鳍式场效应晶体管为一三维设备时,应力工程技术的实现可能是非常复杂的。对于NMOS晶体管,通常不使用应力材料。相反的,对于NMOS设备的性能配置一般是通过结掺杂来实现。然而,其难以增加该活化掺杂剂水平而不从短沟道效应的增加中引入降解。
图1为一说明性的现有集成电路产品100的透视图,其形成于一半导体基板105的上方。于此示例中,产品100包括五个说明性的鳍片110,115,一共享栅极结构120,一侧壁间隔125,以及一栅极盖体130。产品100实现了两种不同的FinFET设备(N型和P型)共用一共享栅极结构。该栅极结构120通常是由一绝缘材料层(未予显示),例如一高K绝缘材料层或二氧化硅层,以及一或多个用以作为产品100上的多个晶体管的栅极电极的导电材料层(例如金属及/或多晶硅)所组成。该鳍片110,115具有一三维配置。由该栅极结构120所覆盖的该鳍片110,115的部分定义出该产品100上的FinFET晶体管设备的沟道区域。一隔离结构135形成于鳍片110,115之间。该鳍片110与一第一类型(N型)的一晶体管设备相关联,该鳍片115与一互补类型(例如P型)的晶体管设备相关联。该由N型晶体管与P型晶体管分享的栅极结构120,为存储产品的一常见配置,例如静态随机存取存储器(SRAM)单元。
本发明通过各种方法及由此产生的设备可以避免或者至少减少一个或多个上述问题所带来的影响。
发明内容
以下为本发明提供的一简化的摘要,以便对本发明的某些方面提供一基本的了解。本摘要不是本发明的一详尽概述。其并非用于识别本发明的关键或重要因素,也不是用于限定本发明的范围。其唯一的目的在于用一个简化的形式呈现一些概念,以作为后续更详尽的描述的一个前奏。
一般而言,本发明涉及形成半导体设备的各种方法。一种方法包括形成一栅极电极结构于定义于一半导体材料中的一沟道区域上方的一栅极电极结构。该半导体材料凹陷于一源/漏区域中。一第一材料外延生长于该源/漏区域中。该第一材料包括具有一第一浓度的一掺杂种类。一扩散阻挡层形成于该第一材料上方的该源/漏区域中。一第二材料外延生长于该扩散阻挡层上方的该源/漏区域中。该第二材料包括具有大于该第一浓度的一第二浓度的该掺杂种类。
另一个方法包括形成一鳍片于一半导体基板上。一栅极电极结构形成于一沟道区域中的该鳍片的上方。该鳍片凹陷于一源/漏区域中。一第一半导体材料外延生长于该源/漏区域中。该第一半导体材料包括具有一第一浓度的一掺杂种类。一硅合金层外延生长于该第一半导体材料上方的该源/漏区域中。一第二半导体材料外延生长于该硅合金层上方的该源/漏区域中。该第二半导体材料包括具有大于该第一掺杂浓度的一第二浓度的该掺杂种类。
在此揭示的一说明性设备中包括,除此之外,定义于一基板上的一鳍片。一栅极电极结构位于一沟道区域中的该鳍片的上方。一源/漏区域定义于该鳍片中。该源/漏区域包括一第一外延半导体材料。该第一外延半导体材料包括具有一第一浓度的一掺杂种类。一扩散阻挡层位于该第一半导体材料的上方。一第二外延半导体材料位于该扩散阻挡层的上方。该第二外延半导体材料包括具有大于该第一掺杂浓度的一第二浓度的该掺杂种类。
附图说明
本发明可通过参考下面的描述及其所附的附图进行理解,其中相关的数字用于识别相似的元件,其中:
图1示意性描述了一说明性先前技术的FinFET设备;以及
图2A至图2F以及图3A至图3F描述了本发明的用于形成一FinFET设备的各种方法。
虽然本文中所公开的主题可以进行各种修改及替换,其具体的实施例已通过图示中的实施例的方式予以显示并详细描述。然而,应了解的是,具体实施例的描述内容并非将本发明限制于该披露的特定形式,相反的,其目的是要涵盖在本发明的精神和范围以及所界定的权利要求范围内的所有的修改、等价物以及替代品。
具体实施方式
本发明的各种说明性实施例的描述如下。为使描述清晰,在此说明书中不会描述一实际实施例的所有特征。应明确注意的是,在任何此类实际实施例的发展中,众多的具体实施决策必须完成开发商们的具体目标,例如,与系统相关的以及与企业相关的约束性,其将根据各不同的实施例而有所不同。此外,应注意的是,这样的一个发展努力可能是复杂并耗时的,不过其将是一个理性程序,用于为本发明的那些本领域的技术人员带来益处。
本发明的主题现将通过所附的图示予以描述。在该图示中各种结构、系统以及设备的概要性地描述仅用于说明的目的,以不掩盖本发明的细节,其为本领域技术人员所悉知。然而,所附的图示包括描述以及解释本发明的说明性实施例。在本文中所使用的单词以及短语应理解并解释为具有一与相关技术领域人员所理解的那些单词以及短语相一致的意思。无特定定义的术语或短语,即,一个定义,是不同于本领域技术人员所理解的普通的和习惯的含义,在此暗含了使用一致的术语以及短语。一个术语或短语所暗含的一特定含义的程度,即除了本领域技术人员所理解的意思,这样的一个特定含义将通过定义的方式在说明书中予以明文规定,藉以直接且明确地提供该术语或短语的特定定义。
本发明的主题通常涉及在设备的一源极/漏极区域中形成具有一硅合金层的一FinFET设备的各种方法。基于对本申请的一完整的理解,本领域的技术人员可以明确地了解,本方法可应用于各种设备,包括,但不限于,逻辑设备、存储设备等。结合参考所附的图示,本发明的方法以及设备的各种说明性实施例将在此予以更详细的描述。
图2A至图2F以及图3A至图3F为说明形成一FinFET设备200的各种方法。于所示的实施例中,该设备200将是一个N型晶体管设备。图2A至图2F显示了显示了一基板205的横截面视图(该设备200的栅极的宽度方向),并具有定义于其中的一鳍片210以及邻接该鳍片210形成的隔离结构215以将该鳍片210与邻接的鳍片隔离(未予显示)。图3A至图3F为说明该设备200通过在一对应于该设备200的栅极长度方向(图2A至图2F视图的旋转90度视角)的方向上的该鳍片的一横截面图。
该基板205可以有各种各样的配置,例如所述的块硅配置。该基板205也可以具有包含有一块硅层、一掩埋绝缘层以及一有源层的一绝缘体上硅(SOI)配置,其中半导体设备形成于该有源层之中及其上方。该基板205可以由硅或硅锗形成,或者其也可以由除了硅以外的材料形成,例如锗。因此,术语“基板”或“半导体基板”应被理解为覆盖所有的半导体材料以及这种材料的所有形式。该基板205可以有不同的层。例如,该鳍片210可形成于一形成于该基板205的基底层上方的处理层中。
图2B及图3B为说明在经过执行多个制程后形成一占位(或虚拟)栅极电极结构230于该鳍片210的上方的该设备200。该占位栅极电极结构230包括一栅极绝缘层235(例如,二氧化硅界面层(interfacial layer)以及一高K介电材料),一占位栅极电极240(例如多晶硅),多个侧壁间隔245(例如氮化硅或氧化硅)以及一覆盖层250(例如氮化硅)。用于形成该占位栅极电极结构230的特殊制程为本领域技术人员已知的现有技术,故在此不再予以详述。于该说明性实施例中,使用一替代栅极技术(RMG)来形成该FinFET设备200,且该占位栅极电极结构230先于一替代栅极结构的形成予以阐述,其中,该占位栅极结构240通常是用一金属栅极电极来代替。该占位栅极电极240将该鳍片分为源/漏(SD)区域255,260以及位于源漏区域之间的一沟道区域265。
图2C以及图3C用于说明于执行一硅蚀刻制程之后,使用该间隔245以及覆盖层250作为一蚀刻掩膜以于该鳍片210形成凹陷的该设备200。如图3C所述,该鳍片210凹陷至该隔离区域215的一高度。如图3C所示,于该鳍片210已凹陷如上述后,该凹陷的鳍片210的侧壁210s可与该间隔245的侧壁245s基本对齐。
图2D以及图3D为说明于该鳍片210的该凹陷的源漏(SD)部分外延生长一第一外延区域270之后的该设备200。于所述的实施例中,该第一外延区域270为原位掺杂一N型掺杂的外延生长硅,例如磷。在一些实施例中,该第一外延区域270的N型掺杂浓度可在大约1×1020至3×1020ions/cm3的范围内,大约1.6×1020的一示例值。该第一外延区域270的厚度可在大约的20-45nm范围内,视依所使用的特定技术节点而定。当设备尺寸减小时,可以采用一个更薄的厚度。
图2E及3E为说明于该第一外延其余270的上方外延生长一扩散阻挡层275之后的该设备200。在一些实施例中,该扩散阻挡层275可以是一硅合金,如硅碳(SiC)。该扩散阻挡层275通常是导电的,但阻挡该第一外延区域270中该N型掺杂的扩散。在所述的实施例中,该扩散阻挡层275为一外延生长硅合金材料。于一实施例中,该合金组分(例如碳)的浓度可在大约1×1020至5×1020的范围内。该扩散阻挡层275可掺杂或不掺杂一N型掺杂,例如磷。该扩散阻挡层275的N型掺杂浓度可在大约0至1×1020ions/cm3的范围内。该扩散阻挡层275的厚度可在大约2-8nm的范围内。该扩散阻挡层275具有一高度,该高度相当于或高于该沟道区域265内的鳍片的高度。
图2F及图3F为说明于该扩散阻挡层275上方外延生长一第二外延区域280之后的该设备200。于所述的实施例中,该第二外延区域280为原位掺杂一N型掺杂的外延生长硅,例如磷。在一些实施例中,该第二外延区域280的N型掺杂浓度可在大约2×1020至1×1021ions/cm3的范围,约5×1020的一示例值。该第二外延区域280的厚度可在大约5至10nm的范围,视依所使用的特定技术节点而定。
该第一及第二外延区域270,280可具有一普通的矩形横截面(如图所示)或一菱形横截面(未在通过图2F的沟道区域的横截面中予以显示),其视该基板205的晶体取向(crystallographic orientation)而定。
此外,可以形成各种掺杂区域,例如,光晕植入区域,井区域等,但未描绘于所附的图式中。可以执行其他的处理步骤以完成该设备200的制造,例如对设备200进行退火以活化掺杂物,形成一替代栅极电极,形成一层间介电材料以及结构结构等等。
在此描述的形成FinFET设备200的方法具有众多的优点。该第二外延区域280的高掺杂浓度降低了设备200的接触电阻,从而提高设备的性能。该扩散阻挡层275抑制了N型掺杂由该较高掺杂的第二外延区域280扩散至该第一外延区域270。在一般情况下,在掺杂剂活化退火后,该扩散阻挡层275的N型掺杂浓度将小于或等于该第一外延区域270的浓度。因为,该扩散阻挡层275位于该沟道区域265中的鳍片210的高度位置或其上方,该第二外延区域280的较高的掺杂水平从该沟道区域265分离,从而降低了来自较高掺杂水平的任何短沟道效应退化的机会。
以上所公开的特定实施例仅用于说明,因为本领域技术人员可在本发明的教示下,可使用不同但等效的方法对本发明进行修改以及实践。例如,上面所述的工艺步骤可以不同的顺序来执行。此外,本文所示的该建构的细节或设计没有任何的限制,如以下的权利要求书所述。因此很明显,上述所公开的特定的实施例可在本发明的范围以及精神下进行变化或修改。需注意的是,术语的使用,例如,在本说明书及所附的权利要求中用于描述各种工艺或结构的“第一”,“第二”,“第三”或“第四“仅用于作为这些步骤/结构的一速记参考,其并不意味着这些步骤/结构需在该顺序序列下执行/形成。当然,依据确切的权利要求语言,这些步骤的顺序序列可能需要或可能不需要。因此,本发明所寻求的保护在于所附的权利要求书中。
Claims (20)
1.一种方法,其特征为,该方法包括:
形成一栅极电极结构于定义于一半导体材料中的一沟道区域的上方;
凹陷该半导体材料于邻接该沟道区域的一源/漏区域中;
外延生长一第一材料于所述源/漏区域中,其中,该第一材料包括具有第一浓度的一掺杂种类;
形成一扩散阻挡层于该第一材料上方的该源/漏区域中;以及
外延生长一第二材料于该扩散阻挡层上方的该源/漏区域中,其中,该第二材料包括具有大于该第一浓度的一第二浓度的该掺杂种类。
2.如权利要求1所述的方法,其特征为,该掺杂种类包括一N型掺杂种类。
3.如权利要求1所述的方法,其特征为,形成该扩散阻挡层包括形成一硅合金层。
4.如权利要求2所述的方法,其特征为,形成该扩散阻挡层包括形成一硅碳层。
5.如权利要求1所述的方法,其特征为,该扩散阻挡层包括该掺杂种类具有小于该第二浓度的一第三浓度。
6.如权利要求1所述的方法,其特征为,该扩散阻挡层的一顶面位于高于该沟道区域中该半导体材料的一顶面的一高度的一高度。
7.如权利要求1所述的方法,其特征为,该第二材料的一地面位于高于该沟道区域中该半导体材料的一顶面的一高度的一高度。
8.一种方法,其特征为,该方法包括:
形成一鳍片于一半导体基板上;
形成一栅极电极结构于一沟道区域中该鳍片的上方;
凹陷该鳍片于一源/漏区域中;
外延生长一第一半导体材料于该源/漏区域中,其中,该第一半导体材料包括具有一第一浓度的一掺杂种类;
外延生长一硅合金层于该第一半导体材料上方的该源/漏区域中;以及
外延生长一第二半导体材料于该硅合金层上方的该源/漏区域中,其中,该第二半导体材料包括具有大于该第一掺杂浓度的一第二浓度的该掺杂种类。
9.如权利要求8所述的方法,其特征为,该掺杂种类包括一N型掺杂种类。
10.如权利要求8所述的方法,其特征为,形成该硅合金层包括形成一硅碳层。
11.如权利要求8所述的方法,其特征为,该硅合金层包括具有小于该第二浓度的一第三浓度的该掺杂种类。
12.如权利要求8所述的方法,其特征为,该硅合金层的一顶面位于高于该沟道区域中该鳍片的一顶面的一高度的一高度。
13.如权利要求8所述的方法,其特征为,该第二半导体材料的一底面位于高于该沟道区域中该鳍片的一顶面的一高度的一高度。
14.一种设备,其特征为,该设备包括:
一鳍片,定义于一基板上;
一栅极电极结构,位于一沟道区域中的该鳍片的上方;以及
一源/漏区域,定义于该鳍片中,包括:
一第一外延半导体材料,其中,该第一外延半导体材料包括具有一第一浓度的一掺杂种类;
一扩散阻挡层,位于该第一半导体材料的上方;以及
一第二外延半导体材料,位于该扩散阻挡层的上方,其中,该第二外延半导体包括具有大于该第一掺杂浓度的一第二浓度的该掺杂种类。
15.如权利要求14所述的设备,其特征为,该掺杂种类包括一N型掺杂种类。
16.如权利要求14所述的设备,其特征为,该扩散阻挡层包括一硅合金层。
17.如权利要求16所述的设备,其特征为,该硅合金层包括一硅碳层。
18.如权利要求14所述的设备,其特征为,该扩散阻挡层包括具有小于该第二浓度的一第三浓度的该掺杂种类。
19.如权利要求14所述的设备,其特征为,该扩散阻挡层的一顶面位于高于该沟道区域中该鳍片的一顶面的一高度的一高度。
20.如权利要求14所述的设备,其特征为,该第二外延半导体材料的一底面位于高于该沟道区域中该鳍片的一顶面的一高度的一高度。
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