CN106992125A - 一种环保型串式中心进胶塑封工艺 - Google Patents

一种环保型串式中心进胶塑封工艺 Download PDF

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Publication number
CN106992125A
CN106992125A CN201610047888.3A CN201610047888A CN106992125A CN 106992125 A CN106992125 A CN 106992125A CN 201610047888 A CN201610047888 A CN 201610047888A CN 106992125 A CN106992125 A CN 106992125A
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chip
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package process
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杨吉明
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Jiangsu High Diode Semiconductor Co Ltd
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Jiangsu High Diode Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开了一种环保型串式中心进胶塑封工艺，进胶塑封工艺依次包括以下步骤：第一步，在上、下引线框架(1)上通过框架引脚(3)均匀排列安装若干对应匹配的上、下芯片固定座(2)，将芯片焊接在上、下两块芯片固定座(2)之间，使芯片与芯片焊接面(4)接触；第二步，通过引线框将黑胶注入芯片焊接面(4)的侧面对焊接在上、下芯片固定座(2)之间的芯片进行塑封。本发明的有益效果：减少电镀工艺前处理，操作简单便捷；黑胶的使用量减少，节省材料，环境污染小，绿色环保；对芯片的冲击力也较小，框架引脚几乎没有残胶，产品品质高。

Description

一种环保型串式中心进胶塑封工艺
技术领域
本发明涉及电器加工技术领域中的一种进胶塑封方法，特别涉及一种环保型串式中心进胶塑封工艺。
背景技术
在现有的进胶塑封工艺中，固定有芯片的固定座2的注胶方式是从引线两侧注入框架引脚3后再流入固定有芯片的固定座2(如图1、图2)，这种注胶方式存在如下缺陷：首先，从框架引脚3注入的黑胶对芯片的冲击力大；其次，引脚3残留比较多，黑胶浪费量大，对环境造成一定影响；最后，电镀工艺前处理工作繁琐，操作不方便。
发明内容
针对现有进胶塑封工艺中存在的缺陷，本发明提供一种环保型串式中心进胶塑封工艺。
为了实现上述目的，本发明所采取的措施：
一种环保型串式中心进胶塑封工艺，进胶塑封工艺依次包括以下步骤：第一步，在上、下引线框架上通过框架引脚均匀排列安装若干对应匹配的上、下芯片固定座，将芯片焊接在上、下两块芯片固定座之间，使芯片与芯片焊接面接触；第二步，通过引线框将黑胶注入芯片焊接面的侧面对焊接在上、下芯片固定座之间的芯片进行塑封。
所述上、下芯片固定座2采用并排的串式排列。
本发明的有益效果：通过引线框架直接将黑胶注入芯片焊接面的侧面，减少电镀工艺前处理，操作简单便捷；黑胶的使用量减少，节省材料，环境污染小，绿色环保；对芯片的冲击力也较小，框架引脚几乎没有残胶，产品品质高。
附图说明
图1本发明中引线框架的结构示意图；
图2本发明中芯片固定座的结构示意图。
具体实施方式
为克服现有进胶塑封工艺中存在的缺陷，设计一种环保型串式中心进胶塑封工艺(如图1、图2)，进胶塑封工艺依次包括以下步骤：第一步，在上、下引线框架1上通过框架引脚3均匀排列安装若干对应匹配的上、下芯片固定座2，将芯片焊接在上、下两块芯片固定座2之间，使芯片与芯片焊接面4接触；第二步，通过引线框将黑胶注入芯片焊接面4的侧面对焊接在上、下芯片固定座2之间的芯片进行塑封。所述上、下芯片固定座2采用并排的串式排列。
本发明的有益效果：通过引线框架直接将黑胶注入芯片焊接面的侧面，减少电镀工艺前处理，操作简单便捷；黑胶的使用量减少，节省材料，环境污染小，绿色环保；对芯片的冲击力也较小，框架引脚几乎没有残胶，产品品质高。
本领域内普通的技术人员的简单更改和替换都是本发明的保护范围之内。

Claims (2)

1.一种环保型串式中心进胶塑封工艺，其特征在于，进胶塑封工艺依次包括以下步骤：第一步，在上、下引线框架(1)上通过框架引脚(3)均匀排列安装若干对应匹配的上、下芯片固定座(2)，将芯片焊接在上、下两块芯片固定座(2)之间，使芯片与芯片焊接面(4)接触；第二步，通过引线框将黑胶注入芯片焊接面(4)的侧面对焊接在上、下芯片固定座(2)之间的芯片进行塑封。
2.根据权利要求1所述的一种环保型串式中心进胶塑封工艺，其特征在于，所述上、下芯片固定座(2)采用并排的串式排列。
CN201610047888.3A 2016-01-21 2016-01-21 一种环保型串式中心进胶塑封工艺 Pending CN106992125A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262720A1 (en) * 2003-06-30 2004-12-30 Renesas Technology Corp. Semiconductor device
CN204271072U (zh) * 2014-10-21 2015-04-15 深圳深爱半导体股份有限公司 引线框架封装结构
CN204946893U (zh) * 2015-08-03 2016-01-06 冯立强 一种过流过压保护复合件及其引线框架

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262720A1 (en) * 2003-06-30 2004-12-30 Renesas Technology Corp. Semiconductor device
CN204271072U (zh) * 2014-10-21 2015-04-15 深圳深爱半导体股份有限公司 引线框架封装结构
CN204946893U (zh) * 2015-08-03 2016-01-06 冯立强 一种过流过压保护复合件及其引线框架

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Application publication date: 20170728