CN106973492A - A kind of PCB internal layer circuits interconnection architecture and its processing method - Google Patents
A kind of PCB internal layer circuits interconnection architecture and its processing method Download PDFInfo
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- CN106973492A CN106973492A CN201710132019.5A CN201710132019A CN106973492A CN 106973492 A CN106973492 A CN 106973492A CN 201710132019 A CN201710132019 A CN 201710132019A CN 106973492 A CN106973492 A CN 106973492A
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- pcb
- conductive material
- layers
- internal layer
- hole
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
Abstract
The invention discloses a kind of PCB internal layer circuits interconnection architecture and its processing method, for solving caused by traditional via stub signal transmission relevant issues and ensuring interlayer conduction.The technical scheme that the embodiment of the present invention is used is as follows：A kind of PCB internal layer circuits interconnection architecture, including：It is arranged at conductive material between Lm layers and Lm+1 layers of the internal layer circuit of the PCB, for realizing interlayer conduction, and, through the via of the conductive material position, the hole copper of the via is connected with the conductive material, and the hole copper of the certain depth of the via is removed, and removed hole copper depth between described between Lm layers and Lm+1 layer；Wherein, m is positive integer.
Description
Technical field
The present invention relates to PCB processing technique fields, and in particular to a kind of PCB internal layer circuits interconnection architecture and its processing side
Method.
Background technology
Printed circuit board（Printed Circuit Board, PCB）Using more and more extensively, design requirement is more and more multiple
It is miscellaneous.Client has very high request signal transmission when designing internal layer circuit for the internal layer circuit of certain some holes or groove.According to posting
Raw effect principle, when signal has transmitted linking sources in the line, can produce the other specification outside except inherent parameters, such as
Stray inductance, parasitic capacitance, coupled capacitor etc..And often when designing circuit, because the limitation of processing technology causes many not
The internal layer circuit of connection is needed to be connected.
Via in PCB, its traditional processing method is for controlled depth milling after the first electro-coppering of through hole, by the hole of certain depth
Copper is removed, and hole copper refers to the electro-coppering in via sidewall.Because control is deep limited in one's ability, except control is deeply outside one's consideration during design, control is deep remaining
Thickness will at least retain >=4mil, therefore, as shown in figure 1, often having the hole that unnecessary hole copper remains in via after controlled depth milling
On wall, these unnecessary hole copper are referred to as stub, and because the deep precision of control is unstable, cause stub values unstable.Via stub
Signal can be influenceed to transmit, for example, cause via stray inductance or electric capacity occur, bring through hole impedance to fall, signal reflex, return loss
Narrow band resonances point is shown, distorted signals, bit error rate increase is ultimately resulted in.
In addition, during traditional handicraft processing, if the deep precision of the deep time control of machining control is unstable, it is possible to can will need conducting
Destination layer areole copper mill off, result in the need for conducting level disconnect, reliability failures.
The content of the invention
The embodiment of the present invention provides a kind of PCB internal layer circuits interconnection architecture and its processing method, for solving traditional mistake
Signal transmits relevant issues and ensures interlayer conduction caused by the stub of hole.
To solve above-mentioned technical problem, the technical scheme that the embodiment of the present invention is used is as follows：
A kind of PCB internal layer circuits interconnection architecture, including：Be arranged at it is between Lm layers and Lm+1 layers of the internal layer circuit of the PCB, use
In the conductive material for realizing interlayer conduction, and, through the via of the conductive material position, the hole copper of the via with
Conductive material connection, and the hole copper of the certain depth of the via is removed, and removed hole copper depth between institute
State between Lm layers and Lm+1 layers；Wherein, m is positive integer.
A kind of processing method of PCB internal layer circuits interconnection architecture, including：The PCB of laminates multilayer, the PCB's is interior
The conductive material for realizing interlayer conduction is provided between Lm layers and Lm+1 layers of circuit of layer；Institute is machined through on the pcb
The via of conductive material position is stated, the hole copper of the via is connected with the conductive material；Control is carried out to the via deep
Milling, the hole copper of the certain depth of the via is removed, wherein, the depth of controlled depth milling is between described between Lm layers and Lm+1 layer.
As can be seen from the above technical solutions, the embodiment of the present invention achieves following technique effect：By in internal layer circuit
Between conductive material is set, with reference to the deep mode of control, solve the deep unstable unstable problem of the reliability brought of control, it can be ensured that mistake
Unnecessary hole copper will not be remained on the hole wall in hole, is passed so as to eliminate the signals such as the ghost effect distortion that stub is brought to via
Defeated problem, and ensure other internal layer circuit normallies.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, below will be to institute in embodiment and description of the prior art
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of schematic diagram of PCB internal layer circuits interconnection architecture of the prior art；
Fig. 2 is a kind of schematic diagram for PCB internal layer circuits interconnection architecture that inventive embodiments are provided；
Fig. 3 is the schematic flow sheet of the processing method for the PCB internal layer circuit interconnection architectures that inventive embodiments are provided.
Embodiment
In order that those skilled in the art more fully understand the present invention program, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill people
The every other embodiment that member is obtained under the premise of creative work is not made, should all belong to the model that the present invention is protected
Enclose.
Term " first ", " second ", " the 3rd " in description and claims of this specification and above-mentioned accompanying drawing etc. are
The different object for distinguishing, rather than for describing particular order.In addition, term " comprising " and " having " and they are any
Deformation, it is intended that covering is non-exclusive to be included.For example contain the process of series of steps or unit, method, system, product
Or equipment is the step of be not limited to list or unit, but the step of alternatively also include not listing or unit, or can
Selection of land is also included for the intrinsic other steps of these processes, method, product or equipment or unit.
Below by specific embodiment, it is described in detail respectively.
Fig. 2 is refer to, inventive embodiments provide a kind of PCB internal layer circuits interconnection architecture, including：
It is arranged at conductive material between Lm layers and Lm+1 layers of the internal layer circuit of the PCB200, for realizing interlayer conduction
201, and, through the via 202 of the position of conductive material 201, hole copper 203 and the conduction of the via 202
Material 201 is connected, and the hole copper of the certain depth of the via 202 is removed, and removed hole copper depth between described
Between Lm layers and Lm+1 layers；Wherein, m is positive integer.
As it is clear from fig. 2 that in the embodiment of the present invention, the PCB includes n-layer circuit altogether, n is the positive integer more than 2.Wherein,
Lm layers and Lm+1 layers are internal layer circuit, and m is more than 1 and m+1 and is less than n.
As shown in Figure 2, carrying out controlled depth milling to via 202 can be carried out from the one side where L1 layers of circuit, described
The hole copper from L1 layers to Lm layers of via is completely removed, and the hole copper from Lm+1 layers to Ln layers is then all retained to realize interlayer
Conducting, the hole copper between Lm layers and Lm+1 layers is then partly retained.
From figure 2 it can be seen that needing interlayer to interconnect between Lm layers and Lm+1 layers, if added deeply using traditional control
Work technique, because the deep precision of control is unstable, or, it may appear that the deep degree of control is inadequate, as shown in figure 1, have unnecessary hole copper and
Stub is remained, influence signal transmission；, it may appear that the deep degree of control exceedes, as shown in Fig. 2 then between Lm layers and Lm+1 layers
Connection will disconnect.
And in technical scheme of the embodiment of the present invention, as shown in Fig. 2 in the position of via 202, between Lm layers and Lm+1 layers
Between, conductive material 201 is provided with, and conductive material 201 is connected with hole copper 203 and Lm layers with Lm+1 layers, then, so that it may
So that when controlled depth milling, the deep-controlled between Lm layers and Lm+1 layers of depth will be controlled, it can so avoid producing via stub
Residual, while avoiding interlayer connection disconnection.
The margin of tolerance generally within 0.1mm, can be used traditional controlled depth milling precision in the embodiment of the present invention in other words
The conductive material of 0.1mm thickness, so just offsets the deep tolerance of control, it is ensured that avoid layer while will not producing via stub residuals
Between connect disconnect.Certainly, 0.1mm thickness is and can slightly adjusted according to the actual requirements in preferred value, practical application, adjusts model
Enclosing for example can be between 0.08 ~ 0.12mm.
In the embodiment of the present invention, the material of described conductive material 201 can select to use metal such as copper or tin or silver
Or gold or their alloy, it would however also be possible to employ nonmetallic such as conducting resinl；The shape of the conductive material 201 for example can be one
Circular square or other shapes of sheet metal.
As described above, the embodiments of the invention provide a kind of PCB internal layer circuits interconnection architecture, by being set between internal layer circuit
Conductive material is put, with reference to the deep mode of control, the deep unstable unstable problem of the reliability brought of control is solved, it can be ensured that via
Unnecessary hole copper will not be remained on hole wall, is asked so as to eliminate the transmission of the signals such as the ghost effect distortion that stub is brought to via
Topic, and ensure other internal layer circuit normallies.
It can be seen that, on the one hand scheme of the embodiment of the present invention solves the signal transmission damage that electronic component ghost effect is brought
Consumption problem, while realizing special processing request of the internal layer circuit for stub.
Fig. 3 is refer to, the embodiment of the present invention also provides a kind of PCB internal layer circuit interconnection architectures as described in Fig. 2 embodiments
Processing method, it may include：
31. it is provided between Lm layers and Lm+1 layers of the PCB of laminates multilayer, the PCB internal layer circuit for realizing interlayer
The conductive material of conducting.
PCB200 described in the present embodiment is multi-layer PCB, such as 4 layers or more than 4 layers.Multi-layer PCB is normally based on bilayer
Plate carries out increasing layer and is made.
The flow for making PCB is generally comprised：Inner figure making-matching board-profile-lamination-milling side etc..Wherein：
Inner figure makes, and is the doubling plate progress inner figure making to centre as substrate, distinguishes on the two sides of doubling plate
Internal layer circuit is produced, specific steps can include pad pasting-exposure-development-etching etc.；
Matching board, refers to each be laminated dielectric and copper foil etc. per one side in doubling plate, each exemplified by making 4 layers of PCB
Face is each laminated one layer of dielectric and one layer of copper foil；
Profile, refers to that carrying out some flutings etc. according to advance design to substrate or dielectric to be laminated or other layers adds
Work；
Lamination, refers to that the laminate structure obtained to matching board carries out HTHP pressing, is integrated into a whole it, tentatively obtains
Multi-layer PCB；
Milling side, refers to be processed the PCB that lamination is obtained using milling machine according to the appearance and size of design.
More than, it is conventional PCB work flows, technical scheme of the embodiment of the present invention is improved above-mentioned flow.
In some embodiments of the invention, before the PCB of the laminates multilayer, in addition to：
The position processing fluting on a dielectric corresponding to the conductive material, slots and runs through the dielectric in advance,
The size of fluting and the size of insulating materials match；In matching board step, has slotted dielectric and described by described
Conductive material is placed in described between Lm layers and Lm+1 layer, and the conductive material is located in the fluting.
What deserves to be explained is, the dielectric can be specifically prepreg（PP）.
That is, in profile step：To need to put dielectric such as PP between the destination layer of conductive material according to
Conductive material correspondingly-sized is slotted on PP；Then, in the matching board step before lamination is pressed in other words：According to regulation lamination
Conductive material, is implanted into by lamination at target interlayer PP flutings；Finally, in lamination step：By the conductive material of implantation with PCB
Laminate is pressed together, the PCB of the multilayer required for the obtained embodiment of the present invention.
32. be machined through the via of the conductive material position on the pcb, the hole copper of the via with it is described
Conductive material is connected.
The PCB obtained to previous step, can process via, it should be pointed out that mistake according to conventional via processing technology
Hole needs guiding through the position where the conductive material, or it is also understood that in previous step, conductive material refers to implantation
The position of processing via is being needed, the hole copper that obtained via is necessary to ensure that in its internal side wall is connected with the conductive material.
In conventional PCB processing technologys, lamination is made after the PCB of multilayer, is typically also comprised the following steps：
Ceramic brush board-drilling-controlled depth milling-outer layer inspection-hole-thickeies copper facing；Wherein,
Ceramic brush board, refers to carry out brushing using ceramic roller bearing etc. to PCB surface, can remove that surface is dirty and oxide layer；
Drilling, refers to various through holes required for being got out on PCB, such as via described in the embodiment of the present invention；
Controlled depth milling, refers to get out required blind hole on PCB；
Kong Hua, i.e., carry out hole metallization to through hole or blind hole, and conventional steps include heavy copper and plating；
Copper facing is thickeied, refers to via for being obtained after device to hole etc., thickening plating is carried out, increases the hole copper thickness of its hole wall, to carry
Its high signal transmission capabilities, improve its connection reliability.
In some embodiments of the invention, the mistake that the conductive material position is machined through on the pcb
Hole can specifically include：Using power auger or laser drilling technique, the conductive material position is machined through on the pcb
Through hole, hole metallization is then carried out to the through hole and copper facing is thickeied, required counterbore is made.
33. pair via carries out controlled depth milling, the hole copper of the certain depth of the via is removed, wherein, controlled depth milling
Depth is between described between Lm layers and Lm+1 layer.
In conventional PCB processing technologys, lamination is made after the conducting hole machineds such as the PCB of multilayer, and completion via, typically
Also comprise the following steps：
Outer graphics-graphic plating-controlled depth milling-outer layer alkaline etching-outer layer inspection-welding resistance-...-packaging；Wherein,
Outer graphics, refer to produce outer circuit respectively on PCB two sides, and specific steps can include pad pasting-exposure-aobvious
Shadow-etching etc.；
Graphic plating, refers to needing the part or all of outer graphics for improving signal/current carrying capacities to carry out graphic plating；
In pcb processing, in order to which to meet the current loading that each circuit is specified, some circuits and hole copper need to reach certain thickness, figure
Shape plating is exactly to thicken this some holes copper and circuit copper to arrive certain thickness, to carry specified load；
In controlled depth milling, the embodiment of the present invention, the step refers to carry out controlled depth milling to the certain depth of counterbore, by the depth bounds
Hole wall on hole copper remove；
Outer layer alkaline etching, refers to the alkali etching that outer layer is carried out to PCB, to remove some excess lines or metal residues such as burr
Deng；
Welding resistance, refers to set solder mask in PCB surface, outer circuit is protected；
After welding resistance, for example, it can also include surface coating step, be protected in the position tin coating such as pad or gold etc., to keep away
Exempt from oxidation.
More than, it is conventional PCB work flows, technical scheme of the embodiment of the present invention is improved above-mentioned flow.
It is described that via progress controlled depth milling is included in some embodiments of the invention：Institute is faced from the one of the PCB
State via and carry out controlled depth milling, the hole copper from L1 layers to Lm layers of the via is removed completely.
In some embodiments of the invention, before the progress controlled depth milling to the via, in addition to：The PCB is entered
Row outer graphics are processed；And, graphic plating is carried out to part or all of outer graphics.
In addition, what deserves to be explained is, in some embodiments of the invention, the material of described conductive material 201 can be selected
Using metal such as copper or tin is silver-colored or golden or their alloy, it would however also be possible to employ nonmetallic such as conducting resinl；The conduction material
The shape of material 201 for example can be a circular square or other shapes of sheet metal.It is described to lead in some embodiments of the invention
The thickness of electric material can be between 0.08 ~ 0.12mm, preferably 0.1mm.
As described above, the embodiments of the invention provide a kind of processing method of PCB internal layer circuits interconnection architecture, including
Conductive material is set between layer circuit, with reference to the deep mode of control, the deep unstable unstable problem of the reliability brought of control is solved, can be with
Ensure that unnecessary hole copper will not be remained on the hole wall of via, so as to eliminate ghost effect distortion that stub is brought to via etc.
Signal transmission issues, and ensure other internal layer circuit normallies.
It can be seen that, on the one hand technical scheme of the embodiment of the present invention solves the signal biography that electronic component ghost effect is brought
Defeated loss problem, while realizing special processing request of the internal layer circuit for stub.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and is not described in some embodiment
Part, may refer to the associated description of other embodiments.
Above-described embodiment is merely illustrative of the technical solution of the present invention, rather than its limitations；The ordinary skill people of this area
Member should be understood：It can still modify to the technical scheme described in the various embodiments described above, or to which part skill
Art feature carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from each reality of the invention
Apply the spirit and scope of a technical scheme.
Claims (10)
1. a kind of PCB internal layer circuits interconnection architecture, it is characterised in that including：
Conductive material between Lm layers and Lm+1 layers of the internal layer circuit of the PCB, for realizing interlayer conduction is arranged at, with
And, through the via of the conductive material position, the hole copper of the via is connected with the conductive material, and the via
The hole copper of certain depth be removed, and removed hole copper depth between described between Lm layers and Lm+1 layer；Wherein, m is
Positive integer.
2. PCB internal layer circuits interconnection architecture according to claim 1, it is characterised in that
The hole copper from L1 layers to Lm layers of the via is completely removed.
3. PCB internal layer circuits interconnection architecture according to claim 1, it is characterised in that
The material of the conductive material is that copper or tin are silver-colored or golden.
4. PCB internal layer circuits interconnection architecture according to claim 1, it is characterised in that
The thickness of the conductive material is 0.1mm.
5. a kind of processing method of PCB internal layer circuits interconnection architecture, it is characterised in that including：
It is provided between Lm layers and Lm+1 layers of the PCB of laminates multilayer, the PCB internal layer circuit for realizing interlayer conduction
Conductive material；
The via of the conductive material position, hole copper and the conduction material of the via are machined through on the pcb
Material connection；
Controlled depth milling is carried out to the via, the hole copper of the certain depth of the via is removed, wherein, the depth of controlled depth milling between
It is described between Lm layers and Lm+1 layer.
6. method according to claim 5, it is characterised in that before the PCB of the laminates multilayer, in addition to：
The position processing corresponding to the conductive material on a dielectric is slotted in advance；
In matching board step, the slotted dielectric of the tool and the conductive material are placed in described Lm layers and Lm+1 layers
Between, and the conductive material is in the fluting.
7. method according to claim 5, it is characterised in that described to be machined through the conductive material on the pcb
The via of position includes：
Using power auger or laser drilling technique, the through hole of the conductive material position is machined through on the pcb, to institute
State through hole to carry out hole metallization and thicken copper facing, required counterbore is made.
8. method according to claim 5, it is characterised in that before the progress controlled depth milling to the via, in addition to：
Outer graphics processing is carried out to the PCB；And,
Graphic plating is carried out to part or all of outer graphics.
9. method according to claim 5, it is characterised in that described to include to via progress controlled depth milling：
The via is faced from the one of the PCB and carries out controlled depth milling, and the hole copper from L1 layers to Lm layers of the via is gone completely
Remove.
10. according to any described method in claim 5 to 9, it is characterised in that
The material of the conductive material is that copper or tin are silver-colored or golden；
And the thickness of the conductive material is 0.1mm.
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| CN106973492B (en) | 2019-03-05 |
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