CN106971989A - 半导体封装及半导体封装组件 - Google Patents
半导体封装及半导体封装组件 Download PDFInfo
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Abstract
本发明提供了半导体封装及半导体封装组件。半导体封装包括:封装基板,具有第一区域以及限定在该封装基板的边缘与该第一区域的边缘之间的第二区域;半导体晶片,在该第一区域中设置在该封装基板上;导电屏蔽元件,设置在该封装基板上并且覆盖该半导体晶片;以及三维天线,该三维天线包括:平面结构部,在该第二区域中设置在该封装基板上;以及桥结构部,位于该平面结构部上方并且与该平面结构部连接。本发明将三维天线集成到了半导体封装中,降低了生产成本,能够实现小且紧凑的SiP组件,并且可以防止三维天线与半导体晶片之间的信号耦合。
Description
技术领域
本发明涉及半导体封装技术,更具体地,涉及具有三维(three-dimensional,3D)天线的半导体封装。
背景技术
近年来,半导体行业出现了系统级封装(system in package,SiP)概念的趋势。将系统集成到单个集成电路(integrated circuit,IC)封装中可以在成本、尺寸、性能和产品设计灵活性等方面提供诸多优势。
许多手持电子产品,如手持电脑、手机、个人数字助理、数码相机或者媒体播放器,通常包括SiP组件。这些手持电子产品也具有无线通信功能。为了实现无线通信功能,天线和通信模块(例如,具有射频设备的IC封装)通常是必需的。天线用来从通信模块发送和接收信号。
在IC封装(如,通信模块)的传统设计中,天线是不包含在其中的。即,天线和IC封装被分别制造并且被安装在电路板上后再电连接。因此,增加了生产成本,且难于实现紧凑且较小的SiP组件。
尽管已经提出了将天线集成到通常的IC封装,但是很容易发生天线与芯片或封装的不同部分之间的电磁干扰(electromagnetic interference,EMI)和信号耦合。这些都可能导致天线级性能的降低。因此,期望一种新的半导体封装。
发明内容
有鉴于此,本发明提供了半导体封装及半导体封装组件,以解决上述问题。
根据至少一个优选实施方式,提供了一种半导体封装,包括:封装基板,具有第一区域以及限定在该封装基板的边缘与该第一区域的边缘之间的第二区域;半导体晶片,在该第一区域中设置在该封装基板上;导电屏蔽元件,设置在该封装基板上并且覆盖该半导体晶片;以及三维天线,该三维天线包括:平面结构部,在该第二区域中设置在该封装基板上;以及桥结构部,位于该平面结构部上方并且与该平面结构部连接。
根据至少一个优选实施方式,提供了一种半导体封装,该半导体封装包括:封装基板,具有第一区域以及限定在该封装基板的边缘与该第一区域的边缘之间的第二区域;模塑料,在该第一区域和该第二区域中设置在该封装基板上;半导体晶片,在该第一区域中设置在该封装基板上并且位于该模塑料内部;以及三维天线和导电屏蔽元件。三维天线包括:平面结构部,位于该第二区域中该封装基板上;以及墙结构部,与该平面结构部接触并且在该第二区域中覆盖该模塑料的顶部表面或者其中一个侧壁。导电屏蔽元件包括:间隔部,位于该三维天线与该半导体晶片之间并且穿过该模塑料;以及U形墙部,覆盖该第一区域中该模塑料的侧壁并且与该三维天线的墙结构部分离。
根据至少一个优选实施方式,提供了一种半导体封装组件,包括:具有禁止区域的印刷电路板以及如上所述的半导体封装,其中该半导体封装中的该封装基板设置在该印刷电路板上,并且该封装基板的该第二区域与该禁止区域对应。
上述半导体封装以及半导体封装组件将三维天线集成到了半导体封装中,降低了生产成本,能够实现小且紧凑的SiP组件,并且可以防止三维天线与半导体晶片之间的信号耦合。
在阅读各个附图中例示的优选实施例的如下详细描述之后,本发明的这些和其他目的对本领域技术人员来说无疑将变得显而易见。
附图说明
图1A是根据本发明的一些实施方式的半导体封装的透视图;
图1B是图1A所示的示例半导体封装的部分平面图;
图1C是图1A所示的示例半导体封装的截面图;
图2是根据本发明的一些实施方式的示例半导体封装组装的截面图。
图3A是根据本发明的一些实施方式的半导体封装的透视图;
图3B是图3A所示的示例半导体封装的部分平面图;
图3C是图3A所示的示例半导体封装的截面图;
图4是根据本发明的一些实施方式的示例半导体封装组件的截面图。
具体实施方式
在说明书及后续的权利要求当中使用了某些词汇来指称特定的组件。本领域一般技术人员应可理解,电子设备制造商可能会用不同的名词来称呼同一组件。本说明书及后续的权利要求并不以名称的差异来作为区别组件的方式,而是以组件在功能上的差异来作为区别的基准。在通篇说明书及后续的权利要求当中所提及的“包含”是开放式的用语,故应解释成“包含但不限定于”。此外,“耦接”一词在此是包含任何直接及间接的电气连接手段。因此,若文中描述第一装置电性连接于第二装置,则代表该第一装置可直接连接于该第二装置,或通过其他装置或连接手段间接地连接至该第二装置。
参照图1A至图1C,其中图1A是根据本发明的一些实施方式的半导体封装10的透视图,图1B是图1A所示的示例半导体封装的部分平面图,图1C是图1A所示的示例半导体封装的截面图。在一些实施方式中,半导体封装10是倒装式(flip-chip)半导体封装。例如,半导体封装10可以是具有集成天线的系统级封装(system in package,SiP),例如封装上天线(antenna on package,AoP)或封装内天线(antenna in package,AiP)。
在实施方式中,半导体封装10包括具有第一区域100a和第二区域100b的封装基板100,如图1C所示。第二区域100b被限定在封装基板100的边缘100e与第一区域100a的边缘之间,并且第二区域100b的面积小于第一区域100a的面积。在一些实施方式,封装基板100可以通过接合工艺(bonding process)安装在基底(没有显示)上,如印刷电路板上。例如,封装基板100可以包括通过接合工艺安装在基底上并且与基底电耦接的导电结构101。在一些实施方式,导电结构101包括导电凸起结构(如,铜或焊料凸起结构)、导电柱结构、导电线结构或导电浆体结构。
在实施方式中,半导体封装10进一步包括在第一区域100a中设置在封装基板100上的半导体晶片200。在一些实施方式中,半导体晶片200可以通过接合过程安装在封装基板100上。例如,半导体晶片200包括通过接合工艺安装在封装基板100上并且与封装基板100电耦接的导电结构201。在一些实施方式,导电结构201包括导电凸起结构(如,铜或焊料凸起结构)、导电柱结构、导电线结构或导电浆体结构。在一些实施方式中,半导体晶片200可以是片上系统(system on chip,SOC)晶片,并且其中包括射频设备(没有显示)。
在实施方式中,半导体封装10进一步包括设置在封装基板100上并且覆盖半导体晶片200的导电屏蔽元件(conductive shielding element)110。在一些实施方式中,导电屏蔽元件110可以由铜、铝或其他合适的屏蔽材料形成以提供EMI保护。
在一些实施方式中,导电屏蔽元件110可以包括板状部(a plate portion)和围绕该板状部的边缘的侧壁部(sidewall portions),从而,半导体晶片200位于由导电屏蔽元件110和封装基板100所构成的空间内部。在一些实施方式中,导电屏蔽元件110具有在其中一个侧壁部中形成的开口122。例如,沿着封装基板100的边缘100a’延伸的侧壁部(如图1C所示)具有开口122(如图1A所示)。开口122使得半导体封装10中形成的一个或多个器件能够通过导电屏蔽元件110。例如,天线可以经由开口122通过导电屏蔽元件110。
在实施方式中,半导体封装10进一步包括设置于封装基板100上的3D天线140。3D天线140可以包括平面结构部(planar structure portion)120和桥结构部(bridgestructure portion)130。在一些实施方式中,平面结构部120在第二区域100b中设置封装基板100上。此外,桥结构部130设置在平面结构部120上方并且与平面结构部120连接。
在一些实施方式中,3D天线140的平面结构部120包括连接在一起的折叠样式(folded pattern)120a以及第一和第二条状样式(bar pattern)120b和120c,如图1A和图1B所示。在一些实施方式中,平面结构部120的折叠样式120a完全位于封装基板100的第二区域100b中。此外,平面结构部120的第一条状样式120b和第二条状样式120c位于封装基板100的第一区域100a和第二区域100b两者中。例如,第一条状样式120b从平面结构部120的折叠样式120a开始延伸,穿过导电屏蔽元件110的开口122,使得平面结构部120的第一条状样式120b在封装基板100的第一区域100a中具有末端(end)121。此外,第二条状样式120c也从平面结构部120的折叠样式120a延伸到封装基板100的第一区域100a,使得平面结构部120的第二条状样式120c在封装基板100的第一区域100a中具有末端121’。在这种情况下,平面结构部120的第一条状样式120b的末端121作为3D天线140的馈电点。第二条状样式120c通过封装基板100接地(图中未显示)并且可以平行于第一条状样式120b。
在一些实施方式中,3D天线140的桥结构部130也完全位于封装基板100的第二区域100b中,并且具有倒U形,如图1A所示。在这种情况下,倒U形桥结构部130可以包括第一端和第二端,第一端连接到平面结构部120的折叠样式120a并且在平面结构部120的折叠样式120a上方,第二端由封装基板100支撑。此外,倒U形桥结构部130可以具有横向延伸部分130a(如图1C所述),该横向延伸部130a平行于平面结构部120的第一条状样式120b和第二条状样式120c,并且具有末端135作为3D天线140的开口端。
在实施方式中,由于天线集成在半导体封装10中并且设置在封装基板100的相对较小的区域(例如,第二区域100b),桥结构部130使得形成3D天线,从而增加3D天线140的有效长度。因此,可以获得天线的所需操作频率。
应该理解的是,3D天线的桥结构部的形状和平面结构部的形状可以基于设计要求而改变,并不限于图1A至图1C中所示的实施方式。
在实施方式中,半导体封装10进一步包括模塑料150,模塑料150设置在封装基板100上并且将导电屏蔽元件110和3D天线140完全封进内部。在一些实施方式中,模塑料150可以由环氧基树脂、合成树脂、可塑聚合物等形成。
参考图2,图2是根据本发明的一些实施方式的示例半导体封装组装20的截面图。简便起见,以下省略了与图1A至图1C中所述元件相同或相类似的元件的描述。在实施方式中,半导体封装组件20包括图1A至图1C所示的半导体封装10。此外,半导体封装10设置在电路板300(例如,可以由聚丙烯(polypropylene,PP)形成的印刷电路板)上。例如,半导体封装10可以利用接合工艺通过封装基板100的导电结构101安装在电路板300上。
在一些实施方式中,电路板300可以具有禁止(keep-out)区域300a,禁止区域300a是其中不形成任何导电迹线或元件的区域。此外,半导体封装10以如下结构设置在电路板300上:封装基板100的第二区域100b对应于电路板300的禁止区域300a。即,第二区域100b与禁止区域300a重叠。在一些实施方式中,禁止区域300a位于电路板300的边缘300e附近,使得3D天线140设置在电路板300的边缘300e附近。
根据上述实施方式,导电屏蔽元件和3D天线集成到用于制造封装内天线(antennain package,AiP)的半导体封装中。由于3D天线集成到半导体封装中,因而生产成本降低,能够实现小且紧凑的SiP组件。
此外,3D天线的桥结构部分进一步增加了其有效长度。
此外,由于3D天线是嵌入在模塑料(molding compound)中,增强了半导体封装的系统集成的设计灵活性。
此外,导电屏蔽元件为半导体封装提供了EMI保护,可以防止天线与导电屏蔽元件内部的半导体晶片之间的信号耦合。
参照图3A至图3C,图3A是根据本发明的一些实施方式的半导体封装10’的透视图,图3B是图3A所示的示例半导体封装的部分平面图,图3C是图3A所示的示例半导体封装的截面图。简便起见,以下省略了与图1A至图1C中所述元件相同或相类似的元件的描述。在实施方式中,除了导电屏蔽元件和3D天线的结构和布置外,半导体封装10’的结构与图1A至图1C中所示的半导体封装10的结构类似。
在实施方式中,半导体封装10’包括在第一区域100a和第二区域100b中设置在封装基板100上的模塑料150。此外,半导体晶片200在第一区域100a中设置在封装基板100上并且位于模塑料150内部。
在实施方式中,半导体封装10’进一步包括设置在封装基板100上的3D天线340。3D天线340包括平面结构部320和与平面结构部320接触的墙结构部330,墙结构部330位于平面结构部320的一侧。在一些实施方式中,平面结构部320在第二区域100b中设置在封装基板100上。此外,墙结构部330在第二区域100b中覆盖模塑料150的一个或多个侧壁150a、150c和150d(例如,在图3A和图3C中例示的在封装基板100的边缘100e附近的侧壁150a)。在一些实施方式中,墙结构部330可以覆盖第二区域100b中模塑料150的顶部表面。
在一些实施方式中,3D天线340的平面结构部320包括螺旋样式320a和与螺旋样式320a分离的两个条状样式320b和320c,如图3A和图3B所示。在一些实施方式中,平面结构部320的螺旋样式320a完全位于封装基板100的第二区域100b中并且具有末端325作为3D天线340的开口端。
在一些实施方式中,平面结构部320的条状样式320b是T形并且位于封装基板100的第一区域100a和第二区域100b两者中。例如,条状样式320b(例如,T形条状样式)具有从封装基板100的第二区域100b延伸到封装基板100的第一区域100a的杆状部(stemportion)。条状样式320b的杆状部在封装基板100的第一区域100a中具有末端321。在这种情况下,条状样式320b的末端321作为3D天线340的馈电点。此外,条状样式320b(例如,T形条状样式)具有臂状部。条状样式320c从条状样式320b的臂状部开始延伸并且可以与条状样式320b的杆状部平行。在这种情况下,条状样式320c位于封装基板100的第二区域100b中,并且可以经由封装基板100接地(未示出)。
在一些实施方式中,3D天线340可以进一步包括在第二区域100b中设置在封装基板100中的第一和第二导电通孔103和105(如图3A和图3C所示),并且第一和第二导电通孔103和105分别电连接到螺旋样式320a和条状样式320b。在这种情况下,第一和第二导电通孔103和105通过封装基板100的边缘100e均具有侧壁,使得第一和第二导电通孔103和105的侧壁从封装基板100的边缘100e暴露出来。
此外,3D天线340的墙结构部330可以进一步覆盖封装基板100的位于边缘100e的侧壁,从而第一和第二导电通孔103和105的暴露的侧壁接触3D天线340的墙结构部330。因此,第一导电通孔103电连接在螺旋样式320a和墙结构部330之间,第二导电通孔105电连接在条状样式320b和墙结构部330之间。
同样地,在此实施方式中,墙结构部330使得能够形成3D天线,以增加其有效长度。因此,可以获得天线的所需操作频率。
应该理解的是,3D天线的平面结构部的形状可以根据设计要求而改变,并不限于图3A至图3C所示的实施方式。
在此实施方式中,半导体封装10’进一步包括设置在封装基板100上并且覆盖半导体晶片200的导电屏蔽元件310。在一些实施方式中,导电屏蔽元件310可以由铜、铝或其他合适的屏蔽材料形成,以提供EMI保护。在一些实施方式中,导电屏蔽元件310的材料可以与3D天线的墙结构部330的材料相同。
在此实施方式中,导电屏蔽元件310包括间隔部301、U形墙部303、板状部305。在一些实施方式中,导电屏蔽元件310的间隔部301设置在封装基板100上并且沿着封装基板100的边缘100a’(如图3C所示)延伸。此外,导电屏蔽元件310的间隔部301设置在3D天线340与半导体晶片200之间并且穿过模塑料150,从而间隔部301的顶部表面从模塑料150中暴露出来。在一些实施方式中,间隔部301的侧壁可以从模塑料150的侧壁150c和150d(如图3A所示)暴露出来。在一些实施方式中,导电屏蔽元件310的间隔部301具有开口301a。开口301a使得在半导体封装10’中形成的一个或多个器件穿过导电屏蔽元件310。例如,3D天线340的平面结构部320的条状样式320b可以经由开口301a穿过导电屏蔽元件310的间隔部301。
在一些实施方式中,U形墙部303在第一区域100a中覆盖模塑料150的侧壁150b、150c和150d,并且与3D天线340的墙结构部330分离。即,部分侧壁150c和150d可以从U形墙部303中暴露出来。
在一些实施方式中,板状部305在第一区域100a中部分覆盖模塑料150的顶部表面,使得板状部305连接到间隔部301的暴露的顶部表面。类似地,板状部305与3D天线340的墙结构部330分离,即,模塑料150的顶部表面的一部分从板状部305暴露出来。
参考图4,图4是根据本发明的一些实施方式的示例半导体封装组件20’的截面图。简便起见,以下省略了与图2和图3A至图3C中所述元件相同或相类似的元件的描述。在实施方式中,半导体封装组装20’包括图3A至图3C所示的半导体封装10’。此外,半导体封装10’设置在电路板300上。例如,半导体封装10’可以利用接合工艺通过封装基板100的导电结构101安装在电路板300上。
在一些实施方式中,半导体封装10’以如下布置设置在电路板300上:封装基板100的第二区域100b对应于电路板300的禁止区域300a。即,第二区域100b与禁止区域300a重叠。在一些实施方式中,禁止区域300a位于电路板300的边缘300e附近,从而3D天线340设置在电路板300的边缘300e附近。
根据上述实施方式,导电屏蔽元件和3D天线集成到用于制造封装内天线(antennain package,AiP)的半导体封装中。由于3D天线集成到半导体封装中,因而生产成本降低,能够实现小且紧凑的SiP组件。
此外,3D天线的墙结构部进一步增加了其有效长度。因而可以获得天线的所需操作频率。
此外,由于3D天线集成在半导体封装中,增强了半导体封装的系统集成的设计灵活性。
此外,导电屏蔽元件为半导体封装提供了EMI保护,可以防止天线与导电屏蔽元件内部的半导体晶片之间的信号耦合。
本领域技术人员将容易注意到,在保持本发明的教导的同时,可以对装置和方法做出大量修改和变化。因此,上述公开内容应当被理解为仅由权利要求的范围限制。
Claims (17)
1.一种半导体封装,包括:
封装基板,具有第一区域以及限定在该封装基板的边缘与该第一区域的边缘之间的第二区域;
半导体晶片,在该第一区域中设置在该封装基板上;
导电屏蔽元件,设置在该封装基板上并且覆盖该半导体晶片;以及
三维天线,包括:
平面结构部,在该第二区域中设置在该封装基板上;以及
桥结构部,位于该平面结构部上方并且与该平面结构部连接。
2.根据权利要求1所述的半导体封装,其特征在于,该三维天线的该平面结构部包括折叠样式以及连接到该折叠样式的第一条状样式和第二条状样式。
3.根据权利要求2所述的半导体封装,其特征在于,该第一条状样式在该第一区域中具有末端,该末端作为该三维天线的馈电点。
4.根据权利要求2所述的半导体封装,其特征在于,该第二条状样式平行于该第一条状样式,并且经由该封装基板接地。
5.根据权利要求2所述的半导体封装,其特征在于,该导电屏蔽元件在其侧壁上具有开口,该第一条状样式经由该开口穿过该导电屏蔽元件。
6.根据权利要求1所述的半导体封装,其特征在于,该三维天线的该桥结构部具有末端,该末端作为该三维天线的开口端。
7.根据权利要求1所述的半导体封装,其特征在于,该半导体封装进一步包括模塑料,该模塑料用于封装该导电屏蔽元件和该三维天线。
8.一种半导体封装,包括:
封装基板,具有第一区域以及限定在该封装基板的边缘与该第一区域的边缘之间的第二区域;
模塑料,在该第一区域和该第二区域中设置在该封装基板上;
半导体晶片,在该第一区域中设置在该封装基板上并且位于该模塑料内部;
三维天线,包括:
平面结构部,位于该第二区域中该封装基板上;以及
墙结构部,与该平面结构部接触并且在该第二区域中覆盖该模塑料的顶部表面或者其中一个侧壁;以及
导电屏蔽元件,包括:
间隔部,位于该三维天线与该半导体晶片之间并且穿过该模塑料;以及
U形墙部,覆盖该第一区域中该模塑料的侧壁并且与该三维天线的墙结构部分离。
9.根据权利要求8所述的半导体封装,其特征在于,该三维天线的该平面结构部包括螺旋样式和与该螺旋样式分离的条状样式。
10.根据权利要求9所述的半导体封装,其特征在于,该条状样式在该第一区域中具有末端,该末端作为该三维天线的馈电点。
11.根据权利要求9所述的半导体封装,其特征在于,该螺旋样式具有末端,该末端作为该三维天线的开口端。
12.根据权利要求9所述的半导体封装,其特征在于,该导电屏蔽元件的该间隔部具有开口,该条状样式经由该开口穿过该间隔部。
13.根据权利要求9所述的半导体封装,其特征在于,该三维天线进一步包括第一导电通孔和第二导电通孔,该第一导电通孔和该第二导电通孔设置在该第二区域中该封装基板中并且从该封装基板的边缘暴露出来。
14.根据权利要求13所述的半导体封装,其特征在于,该第一导电通孔电连接在该螺旋样式与该墙结构部之间,该第二导电通孔电连接在该条状样式与该墙结构部之间。
15.根据权利要求8所述的半导体封装,其特征在于,该导电屏蔽元件进一步包括板状部,该板状部覆盖该第一区域中该模塑料的顶部表面、连接到该间隔部并且与该三维天线的该墙结构部分离。
16.一种半导体封装组件,包括:
印刷电路板,具有禁止区域;以及
如权利要求1-15中任一项所述的半导体封装,其中该半导体封装中的该封装基板设置在该印刷电路板上,并且该封装基板的该第二区域与该禁止区域对应。
17.根据权利要求16所述的半导体封装组件,其特征在于,该禁止区域位于该印刷电路板的边缘附近。
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US9881882B2 (en) | 2018-01-30 |
US20170194271A1 (en) | 2017-07-06 |
EP3190614B1 (en) | 2021-07-28 |
TW201725693A (zh) | 2017-07-16 |
US20180108624A1 (en) | 2018-04-19 |
CN111415912A (zh) | 2020-07-14 |
US10340235B2 (en) | 2019-07-02 |
CN106971989B (zh) | 2020-04-28 |
TWI624925B (zh) | 2018-05-21 |
EP3190614A1 (en) | 2017-07-12 |
CN111415912B (zh) | 2022-10-14 |
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