CN107644851A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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Publication number
CN107644851A
CN107644851A CN201710536646.5A CN201710536646A CN107644851A CN 107644851 A CN107644851 A CN 107644851A CN 201710536646 A CN201710536646 A CN 201710536646A CN 107644851 A CN107644851 A CN 107644851A
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CN
China
Prior art keywords
semiconductor package
semiconductor
layer structure
layer
conductive layer
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CN201710536646.5A
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English (en)
Inventor
林岷臻
周哲雅
陈南诚
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MediaTek Inc
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MediaTek Inc
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Publication of CN107644851A publication Critical patent/CN107644851A/zh
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Abstract

本发明实施例提供了一种半导体封装结构，具有更好的集成度。其中该半导体封装结构包括：重分布层结构，具有第一表面及相对于该第一表面的第二表面，其中该重分布层结构包括：金属间介电层和设置于该金属间介电层的第一层级处的第一导电层；模塑料，覆盖该重分布层结构的该第一表面；第一半导体晶粒，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构；以及多个凸块结构，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构。

Description

半导体封装结构
技术领域
本发明涉及半导体封装技术，尤其涉及一种半导体封装结构。
背景技术
为了确保电子产品及通信装置的持续小型化及多功能性，具有小尺寸、支持多引脚连接、高速操作以及具有高功能性的半导体封装受到期待。另外，在高频应用中，诸如RF(Radio Frequency，射频)SIP(System-in-Package，系统级封装)结构，天线一般用于实现无线通信。
在传统的SiP结构中，分离的天线元件被独立地密封或者安装于PCB(PrintedCircuit Board，印刷电路板)或封装上。另外，半导体晶粒，元件，以及无源器件并排(sideby side)布置。但是，现有技术要求提供额外的区域来供天线元件安装于其上。另外，现有技术要求提供大的区域来布置这些半导体晶粒，元件和无源器件。
如此，难以减小SiP结构的封装大小(footprint)，即平面尺寸。另外，由于SiP结构包含密封或安装在封装上的天线元件，以及放在下面的并排布置的半导体晶粒、元件以及无源器件，因此SiP结构的整体高度也难以降低。
因此，创新的半导体封装结构备受期待。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装结构。
本发明实施例提供了一种半导体封装结构，包括：重分布层结构，具有第一表面及相对于该第一表面的第二表面，其中该重分布层结构包括：金属间介电层和设置于该金属间介电层的第一层级处的第一导电层；模塑料，覆盖该重分布层结构的该第一表面；第一半导体晶粒，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构；以及多个凸块结构，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构。
其中，进一步包括：底部填充层，插入在该重分布层结构的该第二表面和该第一半导体晶粒之间。
其中，进一步包括：第二半导体晶粒及电子元件，设置在该模塑料中并且并排布置，以及电性耦接至该重分布层结构。
其中，该电子元件包括：电容、电感、电阻或者他们的组合。
其中，该第二半导体晶粒包括：射频前端元件，整合无源器件，或者他们的组合。
其中，该第一导电层具有天线图案，并且俯视时该天线图案与该第一半导体晶粒、该第二半导体晶粒及该电子元件横向隔开。
其中，该第一导电层具有接地屏蔽图案。
其中，该重分布层结构进一步包括：设置于该金属间介电层的第二层级处的第二导电层，其中该第二层级位于该第一层级的下方
其中，该第一导电层具有天线图案，该第二导电层具有接地屏蔽图案；该重分布层结构进一步包括：第三导电层，设置在该金属间介电层的第三层级处，其中该第三层级位于该第二层级的下方。
其中，该接地屏蔽图案设置在该天线图案的下方，并且俯视时该天线图案，该接地屏蔽图案完合覆盖该第一半导体晶粒的表面，并且该天线图案与该第一半导体晶粒横向隔开。
本发明实施例的有益效果是：
本发明实施例中，半导体晶粒与多个凸块结构均设置在重分布层结构的同一表面上，因此可以提高半导体封装结构的集成度。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例，可以更全面地理解本发明，其中：
图1为根据本发明实施例的半导体封装结构的横截面示意图；
图2为根据本发明实施例的半导体封装结构的横截面示意图；
图2-1为图2所示的半导体封装结构中的天线图案的布置的平面示意图；
图3为根据本发明实施例的半导体封装结构的横截面示意图；
图4为根据本发明实施例的半导体封装结构的横截面示意图；
图4-1为图4所示的半导体封装结构中的天线图案与接地屏蔽图案的布置的平面示意图；
图5为根据本发明实施例的半导体封装结构的横截面示意图；
图5-1为图5所示的半导体封装结构中的天线图案与接地屏蔽图案的布置的平面示意图；
图6为根据本发明实施例的半导体封装结构的横截面示意图；
图6-1为图6所示的半导体封装结构中的天线图案与接地屏蔽图案的布置的平面示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述为实现本发明的较佳预期模式。该描述仅是出于说明本发明的一般原理的目的，并且不意味着限制。本发明的范围参考所附的权利要求。
本发明以参考特定实施例以及参考确定附图的方式来描述，但是本发明不限制于此并且本发明仅受权利要求的限制。描述的附图仅为原理图并且不是限制。在附图中，出于说明目的和非按比例绘制，夸大了某些元件的尺寸。附图中的尺寸和相对尺寸不对应本发明实践中的真实尺寸。
图1为根据本发明实施例的半导体封装结构10的横截面示意图。在一些实施例中，该半导体封装结构10为晶圆级半导体封装结构，例如，倒装芯片半导体封装结构。
参考图1，该半导体封装结构10可以为安装于基底(未示出)上的晶圆级半导体封装结构。在一些实施例中，该半导体封装结构10可以为SoC(System-on-Chip，片上系统)封装结构。另外，该基底可以包括：PCB(Printed Circuit Board，印刷电路板)，并且可以由聚丙烯(polypropylene，PP)形成。在一些实施例中，该基底可以包括：封装基板。该半导体封装结构10通过接合(bonding)工艺安装于该基底上。例如，该半导体封装结构10包括：凸块结构160(诸如导电球结构、导电柱结构、或者导电膏结构)，通过接合工艺安装并电性耦接至该基底。
在本实施例中，该半导体封装结构10包括：RDL(Redistribution Layer，重分布层)结构110，并且上述凸块结构160电性耦接至该RDL结构110。该RDL结构110，也被称为扇出(fan-out)结构，具有第一表面101和相对于该第一表面101的第二表面103。在一些实施例中，该RDL结构110包括：一个或更多的导电层，设置在IMD(inter-metal dielectric，金属间介电)层100中。例如，单个的第一导电层102设置在IMD层100的第一层级处。在此情形中，该IMD层100可以包括：第一和第二次介电层100a和100b，从该RDL结构110的第一表面101向该RDL结构110的第二表面103依序堆叠，使得该第一导电层102位于该第一和第二次介电层100a和100b之间。在一些实施例中，IMD层100可以由有机材料形成或非有机材料形成，其中有机材料包括：聚合物基(polymer base)材料，非有机材料包括：氮化硅(SiNx)、氧化硅(SiOx)，石墨烯，等等。例如，第一和第二次介电层100a和100b可以由聚合物基材料形成。
另外，凸块结构160设置在RDL结构110的第二表面103上，并且电性耦接至RDL结构110。在一些实施例中，第一导电层102的接垫部分从第二次介电层100b的开口露出，并且通过对应的UBM(Under Bump Metallization，凸块下金属)层160a电性耦接至对应的凸块结构160。
在本实施例中，该半导体封装结构10进一步包括：第一半导体晶粒120，诸如SoC晶粒。该第一半导体晶粒120设置在RDL结构110的第二表面103上，并且第一导电层102电性耦接至该第一半导体晶粒120。如图1所示，该第一半导体晶粒120采用倒装芯片技术来装配。第一半导体晶粒120的凸块结构120a电性连接至第一半导体晶粒120的电路(未示出)。在一些实施例中，第一半导体晶粒120的凸块结构120a被底部填充(underfill)层122围绕，该底部填充层122插入在RDL结构110的第二表面103和第一半导体晶粒120之间。另外，第一半导体晶粒120的凸块结构120a接触对应的导电结构111(如导电凸块、胶或焊膏)，使得第一半导体晶粒120通过导电结构111电性耦接至第一导电层102。需要注意的是，整合进半导体封装结构10中的SoC晶粒的数量不限于本实施例公开的数量。
在本实施例中，该半导体封装结构10进一步包括：一个或更多的第二半导体晶粒130以及一个或更多的电子元件140，设置在RDL结构110的第一表面101上。为了简化示意图，仅描绘了一个第二半导体晶粒130和三个电子元件140。另外，需要注意的是，半导体封装结构10中整合的半导体晶粒或电子元件的数量不限制于本实施公开的数量。
在一些实施例中，第二半导体晶粒130和电子元件140并排布置，并且通过第一导电层102电性耦接至RDL结构110。在一些实施例中，第二半导体晶粒130为RF前端元件，IPD(Integrated Passive Device，集成无源器件)或者他们的组合。可选地，第二半导体晶粒130可以包括：MCU(microcontroller，微控制器)、MPU(microprocessor，微处理器)、RAM(Random Access Memory，随机存取存储器)、PMIC(Power Management IntegratedCircuit，电源管理集成电路)、闪存、GPS(Global Positioning System，全球定位系统)装置、或者他们的任意组合。在一些实施例中，电子元件140为无源器件，诸如电容、电感、电阻或者他们的组合。
在本实施例中，该半导体封装结构10进一步包括：模塑料150，覆盖RDL结构110的第一表面101。在此情形中，第二半导体晶粒130和电子元件140均设置在模塑料150中。在一些实施例中，模塑料150可以由环氧树脂、树脂、可塑聚合物等形成。模塑料150可在实质为液体时应用，接着通过化学反应固化，诸如在环氧树脂或树脂中。在其他的一些实施例中，模塑料150可以为UV(ultraviolet，紫外)或者热固化聚合物，充当能够设置在第二半导体晶粒130和电子元件140周围的凝胶或者可塑固体来应用，接着通过UV或者热固化工艺来固化。模塑料150可以按照模型(未示出)来固化。
凸块结构160通过RDL结构110与模塑料150隔开。换言之，凸块结构160免于与模塑料150接触。
图2为根据本发明一些实施例的半导体封装结构20的横截面示意图，以及图2-1为图2中所示的半导体封装结构20中的天线图案的布置的平面示意图。以下实施例描述的元件，有相同或者类似于先前已参考图1描述了的，出于简洁而省略。
在本实施例中，除了第一导电层102具有一个或更多的天线图案102a之外，半导体封装结构20类似于图1所示的半导体封装结构10。具有天线图案102a的第一导电层102能够实现半导体封装结构20的无线通信。另外，为了简化示图，仅描绘了一个第二半导体晶粒130和一个电子元件140。另外，需要注意的是，整合进半导体封装结构20中的半导体晶粒或电子元件的数量不限制于本实施例公开的数量。
如图2-1所示，例如，第一导电层102具有四个天线图案102a，并且从俯视图中可知看出，该四个天线图案102a排列为阵列。在此情形中，第一导电层102的天线图案102a与第一半导体晶粒120、第二半导体晶粒130和电子元件140(未示出)横向隔开，如从俯视图方面看。另外，第一导电层102的每个天线图案102a均为矩形，如从俯视图方面看。
但是，本领域技术人员可以理解的是，各种各样的形状可以用于第一导电层102的天线图案102a。另外，可以理解的是，半导体封装结构20中整合的天线图案的数量以及这些天线图案的布置均不限制于本实施例所公开的内容。
在本实施例中，由于天线元件整合在RDL结构110中，因此可以降低半导体封装结构20的整体高度。
在一些实施例中，第一导电层102可以具有一代替该天线图案的接地屏蔽(groundshielding)图案(未示出)。在此情形中，天线图案可以安装于半导体封装结构20上。接地屏蔽元件可以降低电噪声对信号的影响，以及减少会干扰其他装置的电磁辐射。
图3为根据本发明实施例的半导体封装结构30的横截面示意图。以下实施例描述的元件，有相同或者类似于先前参考图1或2已描述了的，出于简洁而省略。
在本实施例中，除了RDL结构110的配置之外，该半导体封装结构30类似于图2所示的半导体封装结构20。在本实施例中，该RDL结构110包括：两层导电层，设置在IMD层100的不同层级处。例如，第一导电层102设置在IMD层100的第一层级处，以及第二导电层104设置在IMD层100的低于第一层级的第二层级处。在此情形中，IMD层100可以包括：第一、第二和第三次介电层100a，100b和100c，从RDL结构110的第一表面101向RDL结构110的第二表面103依序堆叠，使得第一导电层102设置在第一和第二次介电层100a和100b之间。另外，第二导电层104设置在第二和第三次介电层100b和100c之间。
在一些实施例中，第二导电层104的接垫从第三次介电层100c的开口中露出，并且通过对应的UBM层160a连接至对应的凸块结构160。
在本实施例中，第一导电层102的天线图案102a可以具有相同或者不同于图2-1所示的天线图案的形状和布置。本领域技术人员可以理解的是，各种各样的形状可以用于第一导电层102的天线图案102a。另外，可以理解的是，半导体封装结构30中整合的天线图案的数量以及天线图案的布置不限制于本实施例公开的内容。
在一些实施例中，半导体封装结构30的第一导电层102可以具有接地屏蔽图案(未示出)来代替该天线图案。在此情形中，天线图案可以安装在半导体封装结构30上。
图4为根据本发明实施例的半导体封装结构40的示意图，以及图4-1为图4中所示的半导体封装结构40中的天线图案与接地屏蔽图案的布置的平面示意图。以下实施例描述的元件，有相同或者类似于先前参考图3已描述了的，出于简洁而省略。
在本实施例中，除了RDL结构110的配置之外，半导体封装结构40类似于图3所示的半导体封装结构30。在本实施例中，第一导电层102具有一个或更多的天线图案102a，以及第二导电层104具有一接地屏蔽图案104a，布置在天线图案102a的下方。具有接地屏蔽图案104a的第二导电层104可以降低天线图案102a与第一半导体晶粒120之间的电噪声，以及降低会干扰其他装置的电磁辐射。
另外，在本实施例中，RDL结构110包括：三个导电层，设置在IMD层100的不同层级处。例如，第一导电层102设置在IMD层100的第一层级处；第二导电层104，设置在IMD层100的位于第一层级下的第二层级处；以及第三导电层106，设置在IMD层100的位于第二层级下的第三层级处。在此情形中，IMD层100可以包括：第一，第二，第三和第四次介电层100a，100b，100c和100d，自RDL结构100的第一表面101向RDL结构110的第二表面103依序堆叠，使得第一导电层102位于第一和第二次介电层100a和100b之间。另外，第二导电层104位于第二和第三次介电层100b和100c之间。另外，第三导电层106位于第三和第四次介电层100c和100d之间。
在一些实施例中，第三导电层106的接垫部分从第四次介电层100d的开口中露出，并且通过对应的UBM层160a连接至对应的凸块结构160。
如图4-1所示，例如，第一导电层102具有四个天线图案102a，从俯视图可以看出该四个天线图案102a布置在阵列中。在此情形中，第一半导体晶粒120的表面完全被接地屏蔽图案104a覆盖，如从俯视图方面所见。另外，第一导电层102的天线图案102a与第二半导体晶粒130和电子元件140(未示出)横向隔开，如从俯视图方面所见。第一导电层102的每个天线图案102a均为矩形，如从俯视图方面所见。
但是，本领域技术人员可以理解的是，各种各样的形状可以用于第一导电层102的天线图案102a。另外，可以理解的是，整合于半导体封装结构40中的天线图案的数量与天线图案的布置不限制于本实施例公开的内容。
在本实施例中，由于天线元件整合于RDL结构110中，因此可以降低半导体封装结构100的整体高度。另外，由于接地屏蔽元件整合于RDL结构110中，因此接地屏蔽元件可以阻止天线图案102a和第一半导体晶粒120之间的电噪声。如此，第一半导体晶粒120可以布置在天线元件的下方，如图4-1所示，从而降低半导体封装结构40的封装大小(即平面尺寸)。
图5为根据本发明实施例的半导体封装结构50的横截面示意图，以及图5-1为图5所示的半导体封装结构50中的天线图案和接地屏蔽图案的布置的平面示意图。以下实施例描述的元件，有相同或者类似于先前参考图4或4-1已描述了的，出于简洁而省略。
在本实施例中，该半导体封装结构50类似于图4所示的半导体封装结构40。不同于半导体封装结构40，第二半导体晶粒130和电子元件140(如图4所示)没有设置在半导体封装50中。
如图5-1所示，在半导体封装结构50中，第一导电层102的天线图案102a可以具有相同或者类似于图4-1所示的天线图案的形状和布置。另外，接地屏蔽图案104a和第一半导体晶粒120的布置相同于图4-1所示的情形。但是，本领域技术人员能够理解的是，各种各样的形状可以用于第一导电层102的天线图案102a。另外，可以理解的是，半导体封装结构50中整合的天线图案的数量和天线图案的布置不限于本实施例公开的内容。
图6为根据本发明实施例的半导体封装结构60的横截面示意图，以及图6-1为图6所示的半导体封装结构60的天线图案和接地屏蔽图案的布置的平面示意图。以下实施例描述的元件，有相同或者类似于参考图4或4-1已描述了的，出于简洁而省略。
在本实施例中，半导体封装结构60类似于图4所示的半导体封装结构40。在半导体封装结构60中，不同于半导体封装结构40，第二半导体晶粒130和电子元件140设置在RDL结构110的第二表面103上，使得第一半导体晶粒120，第二半导体晶粒130和电子元件140并排布置。
如图6-1所示，在半导体封装结构60中，第一导电层102的天线图案102a可以具有与图4-1中所示的天线图案相同的形状和布置。但是，本领域技术人员可以理解的是，各种各样的形状可以用于第一导电层102的天线图案102a。另外，需要注意的是，半导体封装结构60中整合的天线图案的数量以及天线图案的布置不限制于本实施例公开的内容。
在本实施例中，不同于半导体封装结构40，第一半导体晶粒120，第二半导体晶粒130和电子元件140的表面均被接地屏蔽图案104a完全覆盖，如从俯视图方面所见。
在本实施例中，由于天线元件(图案)整合于RDL结构110中，因此可以降低半导体封装结构60的整体高度。另外，由于接地屏蔽元件(图案)整合于RDL结构110中，天线图案102a和第一半导体晶粒120之间的电噪声可以被接地屏蔽元件所阻止。如此，第一半导体晶粒120，第二半导体晶粒130和电子元件140(未示出)可以布置在天线元件的下方，如图6-1所示。如此，相比于半导体封装结构40，半导体封装结构60的封装大小(即平面尺寸)可以进一步降低。
根据前述实施例，半导体封装结构被设计为制造整合于半导体封装中的天线元件和接地屏蔽元件。这些元件可以由RDL工艺来形成。相应地，无需执行额外的工艺来形成天线元件和接地屏蔽元件。如此，增加了半导体封装结构的可靠性、良品率和生产量，以及降低了半导体封装结构的制造成本。另外，整合的天线和接地屏蔽元件可以为半导体封装结构的系统整合提供灵活设计，以及有效地降低封装尺寸。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种半导体封装结构，其特征在于，包括：
重分布层结构，具有第一表面及相对于该第一表面的第二表面，其中该重分布层结构包括：金属间介电层和设置于该金属间介电层的第一层级处的第一导电层；
模塑料，覆盖该重分布层结构的该第一表面；
第一半导体晶粒，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构；以及
多个凸块结构，设置在该重分布层结构的该第二表面上，并且电性耦接至该重分布层结构。
2.如权利要求1所述的半导体封装结构，其特征在于，进一步包括：底部填充层，插入在该重分布层结构的该第二表面和该第一半导体晶粒之间。
3.如权利要求1所述的半导体封装结构，其特征在于，进一步包括：第二半导体晶粒及电子元件，设置在该模塑料中并且并排布置，以及电性耦接至该重分布层结构。
4.如权利要求3所述的半导体封装结构，其特征在于，该电子元件包括：电容、电感、电阻或者他们的组合。
5.如权利要求3所述的半导体封装结构，其特征在于，该第二半导体晶粒包括：射频前端元件，集成无源器件，或者他们的组合。
6.如权利要求3所述的半导体封装结构，其特征在于，该第一导电层具有天线图案，并且俯视时该天线图案与该第一半导体晶粒、该第二半导体晶粒及该电子元件横向隔开。
7.如权利要求3所述的半导体封装结构，其特征在于，该第一导电层具有接地屏蔽图案。
8.如权利要求1所述的半导体封装结构，其特征在于，该重分布层结构进一步包括：设置于该金属间介电层的第二层级处的第二导电层，其中该第二层级位于该第一层级的下方。
9.如权利要求8所述的半导体封装结构，其特征在于，该第一导电层具有天线图案，该第二导电层具有接地屏蔽图案；该重分布层结构进一步包括：第三导电层，设置在该金属间介电层的第三层级处，其中该第三层级位于该第二层级的下方。
10.如权利要求9所述的半导体封装结构，其特征在于，该接地屏蔽图案设置在该天线图案的下方，并且俯视时该天线图案，该接地屏蔽图案完合覆盖该第一半导体晶粒的表面，并且该天线图案与该第一半导体晶粒横向隔开。
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