CN106961800A - 一种pcb上双排ic夹线制作方法 - Google Patents

一种pcb上双排ic夹线制作方法 Download PDF

Info

Publication number
CN106961800A
CN106961800A CN201710168155.XA CN201710168155A CN106961800A CN 106961800 A CN106961800 A CN 106961800A CN 201710168155 A CN201710168155 A CN 201710168155A CN 106961800 A CN106961800 A CN 106961800A
Authority
CN
China
Prior art keywords
double
clamps
compensation
clamp
pcb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710168155.XA
Other languages
English (en)
Other versions
CN106961800B (zh
Inventor
李雄仔
文国堂
黄勇
贺波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aoshikang Precision Circuit Huizhou Co Ltd
Original Assignee
Aoshikang Precision Circuit Huizhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aoshikang Precision Circuit Huizhou Co Ltd filed Critical Aoshikang Precision Circuit Huizhou Co Ltd
Priority to CN201710168155.XA priority Critical patent/CN106961800B/zh
Publication of CN106961800A publication Critical patent/CN106961800A/zh
Application granted granted Critical
Publication of CN106961800B publication Critical patent/CN106961800B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/067Etchants
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09254Branched layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0789Aqueous acid solution, e.g. for cleaning or etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Weting (AREA)

Abstract

一种PCB上双排IC处夹线制作方法,包括以下步骤:(1)对双排IC处夹线进行补偿设计;(2)用蚀刻药水对补偿后的双排IC处夹线进行蚀刻。变更传统的一条直线只能一种数值统一补偿的方法,采用分段补偿的方法,对双排IC处夹线进行分段补偿,严格控制好蚀刻药水参数及蚀刻压力、温度,蚀刻后双排IC处夹线为一条平整的直线,满足客户成品线宽要求。

Description

一种PCB上双排IC夹线制作方法
技术领域
本发明涉及印制电路板领域,具体涉及一种PCB上双排IC夹线制作方法。
背景技术
随着电子产品的不断发展创新,印制电路板(PCB)也在逐渐向高密度、高集成、细线路、小孔径、大容量、轻薄化的方向发展,技术含量和复杂程度不断提高。双排IC夹线设计是现有PCB板常有图形设计类型之一,其夹线细,且夹线到IC的间距小,制作相当困难,严重影响到PCB企业的制程能力。而传统的一条直线一种数值统一补偿的方法使得蚀刻后同一条夹线线宽偏差大,连接IC处线细,影响PCB品质。如何进行双排IC及夹线补偿和调节生产参数从而满足双排IC及夹线的生产品质需求,提高企业的制程能力,增强PCB企业的竞争力,已经成为PCB企业急待解决的问题。
发明内容
本发明所要解决的技术问题是提供一种PCB上双排IC夹线制作方法,克服现有技术的缺点,且方法易于操作,过程简洁,花费少。
本发明所要解决的技术问题通过以下技术方案予以实现:
一种PCB上双排IC夹线制作方法,包括以下步骤:
(1)对双排IC处夹线进行菲林补偿设计;
(2)用蚀刻药水对补偿后的双排IC夹线进行蚀刻;
所述双排IC夹线由头部(1)、尾部(5)、中部(3)、二个颈部(2)组成,其中一个颈部连接于头部与中部之间,另一个颈部连接于尾部和中部之间;PCB上设有分别位于双排IC夹线两侧并与双排IC夹线平行的两排IC(4);
所述的菲林补偿设计包括:对头部(1)和尾部(5)的宽度补偿1.2-2.0mil;颈部(2)的位于其与头部(1)或尾部(5)的交界处的顶边,与两侧IC(4)的顶边平齐,颈部(2)的长度为3.5-4.5mil, 颈部的两侧边设计为弧形;对中部(3)宽度补偿0.4-0.8mil。所述的IC(integrated circuit)为集成电路。
进一步的,所述的双排IC夹线到两侧的任意一排IC的最小距离为2.4mil。
进一步的,所述蚀刻药水中包括当量浓度20-30的NaClO3,当量浓度2.0-2.8的HCl,且Cu2+浓度控制在130-140g/L,药水比重控制在1.25-1.35。
进一步的,所述的蚀刻的温度控制在50±2℃,压力控制在2.6-3.0Kg/cm2。
本发明具有如下有益效果:
变更传统的一条直线只能一种数值统一补偿的方法,采用分段补偿的方法,对双排IC处夹线进行分段补偿,严格控制好蚀刻药水参数及蚀刻压力、温度,蚀刻后双排IC处夹线为一条平整的直线,满足客户成品线宽要求。
附图说明
图1是本发明的一较优实施例中补偿后的双排IC处夹线的结构示意图。
具体实施方式
下面结合附图说明及具体实施方式对发明作进一步说明。
图1中的附图标号为:头部1 ;颈部2 ;中部3 ;IC4 ;尾部5。
一较优实施例中公开了一种PCB上双排IC夹线制作方法,包括以下步骤:
(1)对双排IC夹线进行菲林补偿设计;
(2)用蚀刻药水对补偿后的双排IC夹线进行蚀刻;蚀刻的温度控制在50±2℃,压力控制在2.6-3.0Kg/cm2。
如图1所示,所述双排IC夹线由头部1、尾部5、中部3、二个颈部2组成,其中一个颈部连接于头部与中部之间,另一个颈部连接于尾部和中部之间;PCB上设有分别位于双排IC夹线两侧并与双排IC处夹线平行的两排IC4;
本实施例中,其中,双排IC处夹线到两侧的任意一排IC的最小距离为2.4mil。所述的菲林补偿设计包括:对头部(1)和尾部(5)的宽度补偿1.6mil;颈部(2)的位于其与头部(1)或尾部(5)的交界处的顶边,与两侧IC(4)的顶边平齐,这是根据线路与IC的距离来作为依据的,以所述的颈部(2)与头部(1)交界处的顶边为分界线,分界线以上为空旷区域,菲林可按正常补偿,分界线以下为IC夹线,线与IC间的距离不满足生产的能力,故以此作为分界进行分段补偿,保证蚀刻间距,从而避免蚀刻后有蚀刻不净的缺陷;此外,颈部(2)的长度为3.5mil, 颈部的两侧边设计为弧形;对中部(3)宽度补偿0.6mil。可以理解的,在其他实施例中,对头部(1)和尾部(5)的宽度补偿为1.2-2.0mil,颈部(2)的长度为3.5-4.5mil, 对中部(3)宽度补偿0.4-0.8mil。
本实施例中,所述的蚀刻药水中,NaClO3的当量浓度控制在20-30N, HCl的当量浓度控制在2.0-2.8N,Cu2+浓度控制在130-140g/L,药水比重控制在1.25-1.35。
按照传统的一条直线只能一种数值统一补偿的方法,会出现夹线处合格而连接IC处线细报废,或者连接IC出合格而夹线处蚀刻不净,因双排IC夹线异常导致的报废率约为0.15%。
双排IC夹线进行分段补偿,因双排IC夹线异常导致的报废率为0。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。

Claims (4)

1.一种PCB上双排IC夹线制作方法,包括以下步骤:
(1)对双排IC处夹线进行菲林补偿设计;
(2)用蚀刻药水对补偿后的双排IC夹线进行蚀刻;
所述双排IC处夹线由头部(1)、尾部(5)、中部(3)、二个颈部(2)组成,其中一个颈部连接于头部与中部之间,另一个颈部连接于尾部和中部之间;PCB上设有分别位于双排IC夹线两侧并与双排IC夹线平行的两排IC(4);
所述的菲林补偿设计包括:对头部(1)和尾部(5)的宽度补偿1.2-2.0mil;颈部(2)的位于其与头部(1)或尾部(5)的交界处的顶边,与两侧IC(4)的顶边平齐,颈部(2)的长度为3.5-4.5mil, 颈部的两侧边设计为弧形;对中部(3)宽度补偿0.4-0.8mil。
2.根据权利要求1所述的PCB上双排IC夹线制作方法,其特征在于,所述的双排IC夹线到两侧的任意一排IC的最小距离为2.4mil。
3.根据权利要求1所述的PCB上双排IC夹线制作方法,其特征在于,所述蚀刻药水中包括当量浓度20-30的NaClO3,当量浓度2.0-2.8的HCl,且Cu2+浓度控制在130-140g/L,药水比重控制在1.25-1.35。
4.根据权利要求3所述的PCB上双排IC夹线制作方法,其特征在于,所述的蚀刻的温度控制在50±2℃,压力控制在2.6-3.0Kg/cm2
CN201710168155.XA 2017-03-21 2017-03-21 一种pcb上双排ic夹线制作方法 Expired - Fee Related CN106961800B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710168155.XA CN106961800B (zh) 2017-03-21 2017-03-21 一种pcb上双排ic夹线制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710168155.XA CN106961800B (zh) 2017-03-21 2017-03-21 一种pcb上双排ic夹线制作方法

Publications (2)

Publication Number Publication Date
CN106961800A true CN106961800A (zh) 2017-07-18
CN106961800B CN106961800B (zh) 2019-03-29

Family

ID=59470398

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710168155.XA Expired - Fee Related CN106961800B (zh) 2017-03-21 2017-03-21 一种pcb上双排ic夹线制作方法

Country Status (1)

Country Link
CN (1) CN106961800B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108650798A (zh) * 2018-06-29 2018-10-12 奥士康精密电路(惠州)有限公司 一种酸性蚀刻的厚铜板的生产方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046953A (en) * 1990-05-25 1991-09-10 Hewlett-Packard Company Method and apparatus for mounting an integrated circuit on a printed circuit board
JPH0414497A (ja) * 1990-05-07 1992-01-20 Mitsubishi Electric Corp Icカード
CN102752963A (zh) * 2011-04-21 2012-10-24 日本梅克特隆株式会社 集合基板的单元电路板替换方法和集合基板
CN103533756A (zh) * 2013-09-29 2014-01-22 胜宏科技(惠州)股份有限公司 一种印刷线路板蚀刻方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414497A (ja) * 1990-05-07 1992-01-20 Mitsubishi Electric Corp Icカード
US5046953A (en) * 1990-05-25 1991-09-10 Hewlett-Packard Company Method and apparatus for mounting an integrated circuit on a printed circuit board
CN102752963A (zh) * 2011-04-21 2012-10-24 日本梅克特隆株式会社 集合基板的单元电路板替换方法和集合基板
CN103533756A (zh) * 2013-09-29 2014-01-22 胜宏科技(惠州)股份有限公司 一种印刷线路板蚀刻方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108650798A (zh) * 2018-06-29 2018-10-12 奥士康精密电路(惠州)有限公司 一种酸性蚀刻的厚铜板的生产方法

Also Published As

Publication number Publication date
CN106961800B (zh) 2019-03-29

Similar Documents

Publication Publication Date Title
CN102981356A (zh) 一种减小掩膜版拼接误差的方法
CN206711922U (zh) 一种柔性显示面板和柔性显示母板
US10319924B2 (en) Method for manufacturing flexible substrate, flexible substrate and display device
TW201814368A (zh) 一種柔性折疊顯示幕及製備方法
US20170084640A1 (en) Array Substrate and Manufacturing Method Thereof, and Display Apparatus Thereof
JP2007142103A (ja) 配線基板およびそれを用いた半導体装置
CN106961800A (zh) 一种pcb上双排ic夹线制作方法
WO2020077800A1 (zh) 柔性 oled 显示装置及制备方法
TW201915562A (zh) 液晶顯示器及其製造方法
JP4976089B2 (ja) 多面取り薄膜トランジスタアレイ基板および液晶表示装置
WO2020077742A1 (zh) 一种tft阵列基板的断线修复方法
CN104270903B (zh) 一种实现pcb上锡的方法和装置
US9437621B2 (en) Method of manufacturing components of display panel assembly from same mother substrate
WO2020133786A1 (zh) 切割设备及切割方法
US10820423B2 (en) Fabrication method of circuit board
WO2020258452A1 (zh) 一种显示面板及其制备方法
TWI745823B (zh) 軟性電路板之補強結構
CN106550555A (zh) 一种奇数层封装基板及其加工方法
CN106159070A (zh) 一种高密显示屏单元板及其制作方法
CN204206598U (zh) 一种单面复合板
TWI564950B (zh) 基板運送方法
WO2020228165A1 (zh) 显示面板
JP2015216256A (ja) 搬送パレット、プリント基板製造装置およびプリント基板製造方法
WO2020093464A1 (zh) 一种显示面板的制作方法及其显示面板
WO2015035651A1 (zh) 切割装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190329

CF01 Termination of patent right due to non-payment of annual fee