CN106960844B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106960844B
CN106960844B CN201610015488.4A CN201610015488A CN106960844B CN 106960844 B CN106960844 B CN 106960844B CN 201610015488 A CN201610015488 A CN 201610015488A CN 106960844 B CN106960844 B CN 106960844B
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dielectric
substrate
hole
opening
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CN106960844A (zh
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张智能
洪雅娟
蔡滨祥
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法，该制作半导体元件的方法。首先提供一基底，然后形成一介电层于基底上，并形成一开口于介电层中且该介电层包含一受损层(damaged layer)设于开口旁。接着形成一介电保护层于开口内，形成一金属层于开口内，最后再去除受损层及介电保护层。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种去除镶嵌于介电层中的一受损层(damaged layer)的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体制作工艺在进入10纳米世代后接触插塞的接触面积会大幅降低，造成阻值的增加。除此之外，在制作接触插塞的过程中，特别是利用蚀刻形成接触洞时容易损伤周边的介电层而形成受损区域并影响元件的运作。因此如何在现今场效晶体管的架构下改良此问题即为现今一重要课题。
发明内容
本发明揭露一种制作半导体元件的方法。首先提供一基底，然后形成一介电层于基底上，并形成一开口于介电层中且该介电层包含一受损层(damaged layer)设于开口旁。接着形成一介电保护层于开口内，形成一金属层于开口内，最后再去除受损层及介电保护层。
本发明另一实施例揭露一种半导体元件，其包含：一基底；一介电层设于基底上；一金属层设于基底中以及一孔洞设于金属层及介电层之间。在本实施例中，孔洞优选包含一第一下表面切齐基底的一上表面以及一第二下表面高于基底的上表面。
附图说明
图1至图8为本发明优选实施例制作一半导体元件的方法示意图；
图9至图10为本发明另一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 停止层
16 低介电常数介电层 18 介电层
20 硬掩模 22 图案化光致抗蚀剂
24 开口 26 受损层
28 介电保护层 30 金属层
32 接触插塞 34 孔洞
36 第一下表面 38 第二下表面
40 遮盖层 42 上表面
44 第一介电保护层 46 第二介电保护层
具体实施方式
请参照图1至图8，图1至图8为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，基底12上可包含例如金属氧化物半导体(metal-oxidesemiconductor,MOS)晶体管等主动元件以及/或其他被动元件。更具体而言，基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件，其中MOS晶体管可包含金属栅极、源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件。由于平面型或非平面型晶体管元件等相关制作工艺均为本领域所熟知技术，在此不另加赘述。
然后形成一介电堆叠结构于基底上，例如可依序覆盖一停止层14、一低介电常数介电层16、另一介电层18与一硬掩模20于主动元件以及/或被动元件上，其中停止层14优选为一蚀刻停止层(etch stop layer,ESL)，其可包含氮掺杂碳化物层(nitrogen dopedcarbide,NDC)或氮碳化硅(silicon carbon nitride,SiCN)，介电层18可包含氮氧化硅(silicon oxynitride,SiON)，硬掩模20则优选由氮化钛(TiN)所构成，但不局限于此。另外低介电常数介电层16可选自由含碳介电材料、含氮介电材料、含氢介电材料以及多孔介电结构所构成的群组，例如含碳二氧化硅、含氟二氧化硅、多孔二氧化硅或多孔含碳二氧化硅。
如图2所示，接着进行一光刻暨蚀刻制作工艺，例如先形成一图案化光致抗蚀剂22于硬掩模20上，然后利用图案化光致抗蚀剂22为掩模进行一蚀刻制作工艺，去除部分硬掩模20、部分介电层18、部分低介电常数介电层16、以及部分停止层14，以形成开口24暴露基底12表面与基底12上的主动元件(图未示)。值得注意的是，形成开口24所使用的等离子体蚀刻制作工艺通常会损伤部分的介电层结构，例如位于开口24旁的部分低介电常数介电层16而形成损伤部位或受损层26。
随后如图3所示，进行一灰化制作工艺去除图案化光致抗蚀剂22并暴露硬掩模20表面。
如图4所示，然后沉积一介电保护层28于开口24内并同时覆盖硬掩模20上表面、硬掩模20侧壁、介电层18侧壁、受损层26侧壁、停止层14侧壁以及部分基底12表面。在本实施例中，介电保护层28优选为一单层结构，其优选包含氮化硅(SiN)，但不局限于此。
接着如图5所示，进行一干蚀刻制作工艺，例如一各向异性蚀刻去除位于硬掩模20上表面的介电保护层28与基底12表面的介电保护层28，使剩余的介电保护层28仍设于硬掩模20、介电层18、受损层26以及停止层14侧壁。
如图6所示，然后进行一接触插塞或金属内连线制作工艺，以于开口24中形成接触插塞分别连接并接触原本设于基底12表面的主动元件或被动元件。在本实施例中，形成接触插塞的方式可依序沉积一阻隔层(图未示)与一金属层30于基底12上、介电保护层28侧壁表面以及硬掩模20上表面并填满开口24，然后利用一平坦化制作工艺，例如一化学机械研磨(chemical mechanical polishing,CMP)制作工艺去除部分金属层30、部分阻隔层、部分介电保护层28、硬掩模20以及介电层18，以于开口24中形成接触插塞32并同时暴露出镶嵌于低介电常数介电层16中的受损层26，其中接触插塞32上表面优选与受损层26、低介电常数介电层16以及介电保护层28上表面切齐。在本实施例中，阻隔层优选选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层30优选选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。
如图7所示，接着依序进行一第一蚀刻制作工艺去除受损层26以及一第二蚀刻制作工艺去除介电保护层28，以于原本受损层26与介电保护层28的位置形成孔洞34。在本实施例中，各孔洞34的下半部分呈现具有阶梯状的不规则形状，其至少包含一第一下表面36切齐基底12上表面以及一第二下表面38高于基底12上表面或切齐停止层14上表面。
另外在本实施例中，用来去除受损层26与介电保护层28的第一蚀刻制作工艺与第二蚀刻制作工艺优选选用不同蚀刻剂，其中第一蚀刻制作工艺优选选用包含氢氟酸(HF)的蚀刻剂来去除受损层26，第二蚀刻制作工艺用来去除介电保护层28的蚀刻剂则选自由磷酸及水所构成的群组。需注意的是，本实施例虽选择先利用包含氢氟酸(HF)的第一蚀刻制作工艺来去除受损层26后才利用包含磷酸与水所构成的第二蚀刻制作工艺来去除介电保护层28，但去除这两者的顺序不局限于此，又可选择先去除介电保护层28之后才去除受损层26，此实施例也属本发明所涵盖的范围。
随后如图8所示，形成一遮盖层40并覆盖低介电常数介电层16、孔洞34及金属层30，使孔洞34被包围在基底12、停止层14、低介电常数介电层16、金属层30及遮盖层40中。在本实施例中，遮盖层40优选包含一氮掺杂碳化物层，但不局限于此。至此即完成本发明优选实施例的半导体元件的制作。
请再参照图8，其另揭露本发明优选实施例的一半导体元件结构。如图8所示，本发明的半导体元件主要包含一基底12、一介电层或低介电常数介电层16设于基底12上、一停止层14设于低介电常数介电层16与基底12之间、金属层30设于基底12中、孔洞34设于金属层30与低介电常数介电层16之间以及一遮盖层40设于低介电常数介电层16与金属层30上。
更具体而言，设于金属层30与低介电常数介电层16之间的各孔洞34优选包含一第一下表面36切齐基底12上表面，一第二下表面38高于基底12上表面或切齐停止层14上表面，以及一上表面42与低介电常数介电层16上表面以及金属层30上表面切齐。从另一角度来看，各孔洞34的下半部分优选呈现具有阶梯部的不规则形状，而非一般矩形或圆形。
另外在本实施例中，金属层30虽优选为一直接连接设于基底12上主动元件的接触插塞，但不局限于此，又可依据制作工艺需求为任何电连接其他金属层的金属内连线，此实施例也属本发明所涵盖的范围。
请接着参照图9至图10，图9至图10为本发明另一实施例制作一半导体元件的方法示意图。如图9所示，相较于图4所沉积的介电保护层28为单层结构，本实施例所沉积的介电保护层28优选为双层结构。举例来说，本发明可先于图3去除图案化光致抗蚀剂22后依序沉积一由SiN所构成的第一介电保护层44与一由SiCN所构成的第二介电保护层46于开口24内，其中由SiN所构成的第一介电保护层44优选接触硬掩模20、介电层18、受损层26以及停止层14侧壁。然后如图10所示，先比照图5以各向异性蚀刻去除位于硬掩模20上表面的介电保护层28与基底12表面的介电保护层28、再比照图6填入金属层30于开口24内并以CMP去除部分金属层30、部分阻隔层、部分介电保护层28、硬掩模20以及介电层18。此时构成介电保护层28的第一介电保护层44与第二介电保护层46上表面均同时切齐金属层30、受损层26以及低介电常数介电层16。
接着依序进行一第一蚀刻制作工艺去除受损层26与一第二蚀刻制作工艺去除部分介电保护层28，以于原本受损层26与介电保护层28的位置形成孔洞34。值得注意的是，由于本实施例的介电保护层28为复合层结构，因此在去除受损层26之后优选仅去除部分介电保护层28，亦即仅去除由SiN所构成的第一介电保护层44，使第二介电保护层46仍设于金属层30侧壁或金属层30与孔洞34之间。在本实施例中，第一蚀刻制作工艺与第二蚀刻制作工艺所使用的蚀刻剂优选比照前述实施例，例如第一蚀刻制作工艺优选选用包含氢氟酸(HF)的蚀刻剂来去除受损层26，第二蚀刻制作工艺用来去除第一介电保护层44的蚀刻剂则选自由磷酸及水所构成的群组。
综上所述，本发明主要于介电层中形成接触洞或开口后先沉积一介电保护层于开口内，然后填入金属层于开口内，以平坦化制作工艺去除部分介电层与部分金属层后暴露出原本镶嵌于介电层中的受损层，再依序以两道蚀刻制作工艺去除受损层与介电保护层形成孔洞。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (14)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一介电层于该基底上，该介电层包含低介电常数介电层；
形成一开口于该介电层中，该介电层包含一受损层(damaged layer)设于该开口旁；
形成一介电保护层于该开口内，该介电保护层包含氮化硅；
形成一金属层于该开口内；
进行一第一蚀刻制作工艺去除该受损层；以及
进行一第二蚀刻制作工艺去除该介电保护层。
2.如权利要求1所述的方法，还包含：
形成一停止层于该基底上；
形成该介电层于该停止层上；
形成该开口于该停止层及该介电层内；
形成该介电保护层于该介电层及该停止层的侧壁；以及
形成该金属层于该开口内。
3.如权利要求2所述的方法，还包含去除该受损层及该介电保护层以形成一孔洞，该孔洞包含：
第一下表面切齐该基底的一上表面；以及
第二下表面切齐该停止层的一上表面。
4.如权利要求1所述的方法，其中该第一蚀刻制作工艺包含氢氟酸。
5.如权利要求1所述的方法，其中该第二蚀刻制作工艺是选自由磷酸及水所构成的群组。
6.如权利要求2所述的方法，其中该介电保护层包含一第一介电保护层以及一第二介电保护层，该方法包含：
去除该受损层及该第一介电保护层以形成一孔洞，该孔洞包含：
第一下表面切齐该基底的一上表面切齐；以及
第二下表面切齐该停止层的一上表面。
7.如权利要求6所述的方法，其中该第二介电保护层及该停止层包含相同材料。
8.如权利要求6所述的方法，其中该第一介电保护层包含氮化硅且该第二介电保护层包含氮碳化硅。
9.一种半导体元件，包含：
基底；
介电层，设于该基底上；
停止层，设于该介电层及该基底之间；
金属层，设于该基底上，且位于该介电层和该停止层中；以及
孔洞，设于该金属层及该介电层之间并显露出该停止层的部分上表面，该孔洞包含：
第一下表面，切齐该基底的一上表面；以及
第二下表面，高于该基底的该上表面，且与该停止层被该介电层覆盖的部分的上表面切齐。
10.如权利要求9所述的半导体元件，其中该孔洞的一上表面与该介电层的一上表面切齐。
11.如权利要求9所述的半导体元件，另包含一介电保护层设于该金属层旁。
12.如权利要求11所述的半导体元件，其中该介电保护层的一上表面与该孔洞的一上表面切齐。
13.如权利要求11所述的半导体元件，其中该介电保护层的一下表面与该孔洞的该第一下表面切齐。
14.如权利要求9所述的半导体元件，还包含一遮盖层设于该介电层、该孔洞及该金属层上。
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