CN106960826A - A kind of encapsulation chip and processing technology with ledge structure - Google Patents
A kind of encapsulation chip and processing technology with ledge structure Download PDFInfo
- Publication number
- CN106960826A CN106960826A CN201710179727.4A CN201710179727A CN106960826A CN 106960826 A CN106960826 A CN 106960826A CN 201710179727 A CN201710179727 A CN 201710179727A CN 106960826 A CN106960826 A CN 106960826A
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- CN
- China
- Prior art keywords
- layer
- chip
- ink
- copper foil
- circuit copper
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
The present invention provides a kind of encapsulation chip and processing technology with ledge structure, including epoxy resin basic unit and the insulating oil layer of ink that is formed in the epoxy resin basic unit；Epoxy resin basic unit, which is internally provided with chip die, and insulating oil layer of ink, is formed with insulating glass fibers layer and circuit copper foil layer；The two ends of insulating oil layer of ink and insulating glass fibers layer form two step surfaces with epoxy resin substrate surface respectively, the design can realize that nothing undermines anhydrous processing, ensure the high intensity and precision of whole process, and reach the purpose for reducing operating personnel, reduce production cost, as the Cyberspaces such as smart mobile phone and panel computer are more and more compacter, most devices are gradually toward ultra-thin, extra small direction is developed, especially in process successively using the molding mode such as local reduction or middle hollow out, also or from the processing of 2D planes change toward the direction of 3D multidimensional, the design can preferably cater to the demand for development of industry, and final obtains preferably process and using effect.
Description
[technical field]
The present invention relates to encapsulation chip manufacture technical field, more particularly to a kind of machining accuracy are high, be conducive to saving into
This, and whole process realizes the encapsulation chip and processing technology with ledge structure of Non-aqueous processing.
[background technology]
In recent years, intelligent artifact market underwent an unusual development burning hot, and it is very big convenient that the life given people is brought, also significantly
Degree improves the living standard of people, however, because the Cyberspaces such as smart mobile phone and panel computer are more and more compacter, its body
Internal device is also required to constantly toward ultra-thin, and development is gone in extra small direction, and realize it is local be thinned with middle hollow out etc. into
Type requirement, or even the processing for having 2D planes go development toward the direction of 3D multidimensional, and such situation is just to actual product component
Layout is set, and specific processing technology brings very big challenge, and technology at present in this respect is ripe not enough, some precision machinings
Degree is not high enough, it is impossible to adapt to the processing in smaller space, and some process need to wash or cooled, and indirectly improve difficult processing
Degree.
Based on above mentioned problem, the accurate and production efficiency of Product processing how could is effectively improved, actual need are met
Ask, those skilled in the art has carried out substantial amounts of research and development and experiment, and achieves preferable achievement.
[content of the invention]
To overcome the problems of prior art, the present invention provides a kind of machining accuracy height, is conducive to saving cost,
And whole process realizes the encapsulation chip and processing technology with ledge structure of Non-aqueous processing.
The scheme that the present invention solves technical problem is to provide a kind of encapsulation chip and processing technology with ledge structure,
Including epoxy resin basic unit and the insulating oil layer of ink being formed in the epoxy resin basic unit；Inside the epoxy resin basic unit
Chip die is provided with, and is formed with insulating oil layer of ink insulating glass fibers layer and circuit copper foil layer；The insulation glass
Glass fibrous layer is arranged at the middle part of circuit copper foil layer, and circuit copper foil layer is connected with chip die by gold thread；The insulation
The two ends of ink layer and insulating glass fibers layer form two step surfaces with epoxy resin substrate surface respectively.
Preferably, the dielectric ink layer surface and the difference in height scope of epoxy resin substrate surface are 0.15-0.3mm.
Preferably, an extension is extended upward close to chip die position on the upside of the epoxy resin basic unit, the extension
Portion is contacted after passing through insulating oil layer of ink with circuit copper foil layer, and the gold thread of connection circuit copper foil layer and chip die passes through epoxy resin
Extension on the upside of basic unit is contacted with circuit copper foil layer.
Preferably, the circuit copper foil layer is divided into circuit copper foil layer and lower circuit copper foil layer, insulating glass fibers layer
It is formed on this between circuit copper foil layer and lower circuit copper foil layer；The insulating oil layer of ink is divided into insulating oil layer of ink and lower exhausted
Edge ink layer, and insulating glass fibers layer and circuit copper foil layer be formed on this between insulating oil layer of ink and lower insulating oil layer of ink.
A kind of processing technology that chip is encapsulated with ledge structure, comprises the following steps,
S1：To be processed PCB of the preparation with several chip units being set up in parallel, and in the PCB
It is upper to attach diaphragm manually；
S2：Radium-shine raceway groove around each chip unit in PCB, and the width range of raceway groove is controlled in 250-
Between 350 microns；Remove cutting bits；
S3：The PCB of the radium-shine completion of cleaning S2 raceway grooves, and mill out and set along the raceway groove around each chip unit
The step surface of depthkeeping degree；The width of step surface is controlled to be more than step depth 0.15mm；
S4：The PCB of cleaning S3 completion of processing, one single chip unit is molded using laser cutting；Prepare
Into.
Preferably, the thickness range of diaphragm is 195-205 microns in the step S1.
Preferably, in the step S2, the margin of tolerance of radium-shine channel depth is +/- 0.02mm；And it is radium-shine after the completion of
The drift rate margin of tolerance of PCB ink area size is +/- 0.03mm.
Preferably, in the step S4, when using laser cutting shaping one single chip, the sized central of PCB
Degree drift rate is +/- 0.035mm.
Compared with prior art, the present invention a kind of encapsulation chip and processing technology with ledge structure passes through in insulation
The two ends of ink layer and insulating glass fibers layer form two step surfaces corresponding with epoxy resin substrate surface, actual production
In process, using the CNC millings step surface with higher accuracy, higher technological requirement can be met, the design is real
The effect that border can reach undermines anhydrous processing for realization nothing, it is ensured that the high intensity and high accuracy of whole process, and reaches
The purpose of operating personnel is preferably reduced, production cost is reduced, as the Cyberspaces such as current smart mobile phone and panel computer are got over
Come compacter, most devices gradually develop toward ultra-thin, extra small direction, especially subtracted successively using local in process
The molding modes such as thin or middle hollow out, also or from the processing of 2D planes change, the design can be preferable toward the direction of 3D multidimensional
The demand for development for catering to industry, and final obtain preferably processing and using effect.
[brief description of the drawings]
Fig. 1 is the layer structure schematic diagram that traditional structure encapsulates chip.
Fig. 2 is a kind of layer structure schematic diagram of the encapsulation chip with ledge structure of the present invention.
Fig. 3 is the support plate dimensional structure diagram corresponding to a kind of encapsulation chip with ledge structure of the present invention.
Fig. 4 is a kind of processing process figure that chip is encapsulated with ledge structure of the present invention.
[embodiment]
To make the purpose of the present invention, technical scheme and advantage are more clearly understood, below in conjunction with drawings and Examples, to this
Invention is further elaborated.It should be appreciated that specific embodiment described herein is used only for explaining the present invention, not
For limiting this invention.
Refer to Fig. 1 to Fig. 4, a kind of encapsulation chip 1 with ledge structure of the present invention including epoxy resin basic unit 11 with
And it is formed at the insulating oil layer of ink 13 in the epoxy resin basic unit 11；It is brilliant that chip is internally provided with the epoxy resin basic unit 11
Circle 12, and it is formed with insulating oil layer of ink 13 insulating glass fibers layer 14 and circuit copper foil layer 15；The insulating glass is fine
Dimension layer 14 is arranged at the middle part of circuit copper foil layer 15, and circuit copper foil layer 15 is connected with chip die 12 by gold thread 121；Institute
The two ends for stating insulating oil layer of ink 13 and insulating glass fibers layer 14 form two step surfaces with epoxy resin basic unit 11 surface respectively
111。
The present invention at the two ends of insulating oil layer of ink 13 and insulating glass fibers layer 14 by forming and epoxy resin basic unit
In two corresponding step surfaces 111 of 11 surfaces, actual production process, using the CNC millings step with higher accuracy
Face 111, can meet higher technological requirement, and the effect that the design can actually reach is protected to realize without anhydrous processing is undermined
The high intensity and high accuracy of whole process are demonstrate,proved, and reaches the purpose for preferably reducing operating personnel, production cost is reduced, with
That the Cyberspaces such as current smart mobile phone and panel computer are more and more compacter, most devices are gradually toward ultra-thin, extra small direction
Development, especially in process successively using the molding mode such as local reduction or middle hollow out, also or from 2D planes
The direction for processing past 3D multidimensional changes, and the design can preferably cater to the demand for development of industry, and final obtain preferably adds
Work and using effect.
Preferably, the surface of insulating oil layer of ink 13 and the difference in height scope on the surface of epoxy resin basic unit 11 are 0.15-
0.3mm.Size design is reasonable, long service life.
Preferably, the upside of epoxy resin basic unit 11 extends upward an extension close to the position of chip die 12, should
Extension is contacted after passing through insulating oil layer of ink 13 with circuit copper foil layer 15, connection circuit copper foil layer 15 and the gold thread of chip die 12
121 contact by the extension of the upside of epoxy resin basic unit 11 with circuit copper foil layer 15.
Preferably, 15 points of the circuit copper foil layer is upper circuit copper foil layer and lower circuit copper foil layer, insulating glass fibers
Layer 14 is formed on this between circuit copper foil layer and lower circuit copper foil layer；13 points of the insulating oil layer of ink be upper insulating oil layer of ink with
And lower insulating oil layer of ink, and insulating glass fibers layer 14 and circuit copper foil layer 15 are formed at insulating oil layer of ink and lower insulating oil on this
Between layer of ink.
A kind of processing technology that chip is encapsulated with ledge structure, comprises the following steps,
S1：To be processed PCB of the preparation with several chip units being set up in parallel, and in the PCB
It is upper to attach diaphragm manually；Need to check that bubble must not occur in the PCB back side after pad pasting；
S2：Radium-shine raceway groove around each chip unit in PCB, and the width range of raceway groove is controlled in 250-
Between 350 microns；Remove cutting bits；During reality processing, the width of raceway groove can arbitrarily adjust that (channel width carefully understands very much shadow
Rehearse with musical accompaniment bits, cause the depth uncontrollable)；The purpose of cutting raceway groove is the step edge that cutter directly encounters product when avoiding CNC,
To prevent PCB spring side and damaged, the glass fibre layering of PCB and burr；
S3：The PCB of the radium-shine completion of cleaning S2 raceway grooves, and mill out and set along the raceway groove around each chip unit
The step surface 111 of depthkeeping degree；The width of step surface 111 is controlled to be more than step depth 0.15mm；During reality processing, per tour is made
Need to process three with false piece before industry, measure at least nine test point, depth error value scope control is between +/- 0.02mm, test
After the completion of carry out formal operation, while every product measures at least eight point depth data；
S4：The PCB of cleaning S3 completion of processing, one single chip unit is molded using laser cutting；Prepare
Into.Without dispergation in reality processing, adhesive tension grammes per square metre 100G, (needed according to CNC with the sticky glue of more than 1KG, it is solid to ensure
Fixed, single of subsequent artefacts take off, can cause slight fracture, and outward appearance is difficult to discover)；Using laser formation, product can be avoided to exist
During with CNC excision formings, adhesive force of single PCB on film diminishes, so as to cause product to be shifted, causes size to produce change
Change, cause not in management and control scope；
Preferably, the thickness range of diaphragm is 195-205 microns in the step S1.
Preferably, in the step S2, the margin of tolerance of radium-shine channel depth is +/- 0.02mm；And it is radium-shine after the completion of
The drift rate margin of tolerance of PCB ink area size is +/- 0.03mm.Size design is reasonable.
Preferably, in the step S4, when using laser cutting shaping one single chip, the sized central of PCB
Degree drift rate is +/- 0.035mm.
Compared with prior art, the present invention a kind of encapsulation chip and processing technology with ledge structure passes through in insulation
The two ends of ink layer 13 and insulating glass fibers layer 14 form two step surfaces corresponding with epoxy resin basic unit 11 surface
111, in actual production process, using the step surface 111 of the CNC millings with higher accuracy, higher work can be met
Skill requirement, the effect that the design can actually reach undermines anhydrous processing for realization nothing, it is ensured that the high intensity of whole process
And high accuracy, and the purpose for preferably reducing operating personnel is reached, production cost is reduced, with current smart mobile phone and flat board electricity
The Cyberspaces such as brain are more and more compacter, and most devices gradually develop toward ultra-thin, extra small direction, especially in process
Successively using the molding mode such as local reduction or middle hollow out, also or from the processing of 2D planes change toward the direction of 3D multidimensional,
The design can preferably cater to the demand for development of industry, and final obtains preferably process and using effect.
Invention described above embodiment, is not intended to limit the scope of the present invention..It is any in the present invention
Spirit and principle within modification, equivalent and the improvement made etc., should be included in the claim protection model of the present invention
Within enclosing.
Claims (8)
1. a kind of encapsulation chip with ledge structure, it is characterised in that：Including epoxy resin basic unit and it is formed at the epoxy
Insulating oil layer of ink in base layer of resin；Chip die is internally provided with the epoxy resin basic unit, and in insulating oil layer of ink
It is formed with insulating glass fibers layer and circuit copper foil layer；The insulating glass fibers layer is arranged at the pars intermedia of circuit copper foil layer
Position, circuit copper foil layer is connected with chip die by gold thread；The two ends point of the insulating oil layer of ink and insulating glass fibers layer
Not with epoxy resin substrate surface two step surfaces of formation.
2. a kind of encapsulation chip with ledge structure as claimed in claim 1, it is characterised in that：The insulating oil layer of ink table
Face is 0.15-0.3mm with the difference in height scope of epoxy resin substrate surface.
3. a kind of encapsulation chip with ledge structure as claimed in claim 1, it is characterised in that：The epoxy resin basic unit
Upside extends upward an extension close to chip die position, and the extension connects after passing through insulating oil layer of ink with circuit copper foil layer
Touch, the gold thread of connection circuit copper foil layer and chip die connects by the extension on the upside of epoxy resin basic unit with circuit copper foil layer
Touch.
4. a kind of encapsulation chip with ledge structure as claimed in claim 1, it is characterised in that：The circuit copper foil layer point
For upper circuit copper foil layer and lower circuit copper foil layer, insulating glass fibers layer is formed at circuit copper foil layer and lower circuit Copper Foil on this
Between layer；The insulating oil layer of ink is divided into insulating oil layer of ink and lower insulating oil layer of ink, and insulating glass fibers layer and circuit
Copper foil layer is formed on this between insulating oil layer of ink and lower insulating oil layer of ink.
5. a kind of processing technology that chip is encapsulated with ledge structure, it is characterised in that：Comprise the following steps,
S1：To be processed PCB of the preparation with several chip units being set up in parallel, and in the PCB left-hand seat
It is dynamic to attach diaphragm；
S2：Radium-shine raceway groove around each chip unit in PCB, and the width range of control raceway groove is micro- in 250-350
Between rice；Remove cutting bits；
S3：The PCB of the radium-shine completion of cleaning S2 raceway grooves, and mill out setting deeply along the raceway groove around each chip unit
The step surface of degree；The width of step surface is controlled to be more than step depth 0.15mm；
S4：The PCB of cleaning S3 completion of processing, one single chip unit is molded using laser cutting；Prepare and complete.
6. a kind of processing technology that chip is encapsulated with ledge structure as claimed in claim 5, it is characterised in that：The step
The thickness range of diaphragm is 195-205 microns in S1.
7. a kind of processing technology that chip is encapsulated with ledge structure as claimed in claim 5, it is characterised in that：The step
In S2, the margin of tolerance of radium-shine channel depth is +/- 0.02mm；And it is radium-shine after the completion of PCB ink area size
The drift rate margin of tolerance is +/- 0.03mm.
8. a kind of processing technology that chip is encapsulated with ledge structure as claimed in claim 5, it is characterised in that：The step
In S4, when using laser cutting shaping one single chip, the sized central degree drift rate of PCB is +/- 0.035mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710179727.4A CN106960826B (en) | 2017-03-23 | 2017-03-23 | A kind of encapsulation chip and processing technology with ledge structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710179727.4A CN106960826B (en) | 2017-03-23 | 2017-03-23 | A kind of encapsulation chip and processing technology with ledge structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106960826A true CN106960826A (en) | 2017-07-18 |
| CN106960826B CN106960826B (en) | 2018-03-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710179727.4A Active CN106960826B (en) | 2017-03-23 | 2017-03-23 | A kind of encapsulation chip and processing technology with ledge structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111770627A (en) * | 2020-07-02 | 2020-10-13 | 中科芯集成电路有限公司 | Flexible rigid PCB circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750736A (en) * | 2004-09-15 | 2006-03-22 | 三星电机株式会社 | Printed circuit board including embedded passive component and method of fabricating same |
| CN102271469A (en) * | 2011-07-08 | 2011-12-07 | 深圳市精诚达电路有限公司 | Method for processing rigid-flexible printed circuit board (PCB) |
| CN104427765A (en) * | 2013-08-20 | 2015-03-18 | 深圳崇达多层线路板有限公司 | Processing method of PTFE copper-clad plate |
| CN105392283A (en) * | 2015-10-16 | 2016-03-09 | 广州杰赛科技股份有限公司 | Process for realizing no carbon black on pattern in laser edge-milling |
-
2017
- 2017-03-23 CN CN201710179727.4A patent/CN106960826B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750736A (en) * | 2004-09-15 | 2006-03-22 | 三星电机株式会社 | Printed circuit board including embedded passive component and method of fabricating same |
| CN102271469A (en) * | 2011-07-08 | 2011-12-07 | 深圳市精诚达电路有限公司 | Method for processing rigid-flexible printed circuit board (PCB) |
| CN104427765A (en) * | 2013-08-20 | 2015-03-18 | 深圳崇达多层线路板有限公司 | Processing method of PTFE copper-clad plate |
| CN105392283A (en) * | 2015-10-16 | 2016-03-09 | 广州杰赛科技股份有限公司 | Process for realizing no carbon black on pattern in laser edge-milling |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111770627A (en) * | 2020-07-02 | 2020-10-13 | 中科芯集成电路有限公司 | Flexible rigid PCB circuit board |
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| Publication number | Publication date |
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| CN106960826B (en) | 2018-03-06 |
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