CN106935648A - 作为高压装置的栅极电介质的凹陷浅沟槽隔离 - Google Patents

作为高压装置的栅极电介质的凹陷浅沟槽隔离 Download PDF

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CN106935648A
CN106935648A CN201610815080.5A CN201610815080A CN106935648A CN 106935648 A CN106935648 A CN 106935648A CN 201610815080 A CN201610815080 A CN 201610815080A CN 106935648 A CN106935648 A CN 106935648A
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gate
semiconductor substrate
top surface
dielectric
area
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CN106935648B (zh
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陈奕寰
范富杰
郑光茗
霍克孝
陈奕升
刘思贤
林国树
叶力瑄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect

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Abstract

本发明涉及作为高压装置的栅极电介质的凹陷浅沟槽隔离。具体的，本发明揭示一种方法，其包含：形成延伸到半导体衬底中的隔离区；蚀刻所述隔离区的顶部部分，以在所述隔离区中形成凹陷部；和形成延伸到所述凹陷部中且与所述隔离区的下部分重叠的栅极堆叠。在所述栅极堆叠的相对侧上形成源极区和漏极区。所述栅极堆叠、所述源极区和所述漏极区为金属氧化物半导体装置MOS的部分。

Description

作为高压装置的栅极电介质的凹陷浅沟槽隔离
技术领域
本发明涉及一种半导体元件和其制造方法。
背景技术
高压金属氧化物半导体(HVMOS)装置广泛用于许多电气装置(例如中央处理单元(CPU)电源供应器、电力管理系统、AC/DC转换器等)中。
HVMOS装置具有不同于中压金属氧化物半导体(MVMOS)装置和低压金属氧化物半导体(LVMOS)装置的结构。为维持在HVMOS装置的栅极与漏极之间施加的高压，HVMOS装置的栅极电介质比MVMOS装置的栅极电介质和LVMOS装置的栅极电介质厚。另外，高压阱区的掺杂浓度低于MVMOS装置和LVMOS装置的阱区的掺杂浓度以便维持更高的栅极-漏极电压。
发明内容
本发明的实施例具有一些有利特征。期望使HV MOS装置和LV/MV装置共享用于形成替换栅极的程序以便降低制造成本。然而，HV MOS装置具有厚栅极电介质，且因此HV MOS装置的栅极电介质的顶部表面可与LV/MV MOS装置的虚设栅极电极的顶部表面基本上等高，或甚至更高。因此，用于暴露LV/MV MOS装置的虚设栅极电极的平坦化可导致HV MOS装置的虚设栅极电极的完全移除。此意谓，对于HV MOS装置，无法通过共享用于形成LV/MVMOS装置的替换栅极的相同程序形成替换栅极。通过使STI区凹陷且在所述凹陷部中形成HVMOS装置的栅极电极，减小HV MOS装置与LV/MV MOS装置的顶部表面之间的高度差，且可在不完全移除HV MOS装置的虚设栅极电极的情况下执行平坦化。另外，根据本发明的实施例，STI区用作HV MOS装置的栅极电介质，且因此降低生产成本。
根据本发明的一些实施例，一种方法包含：形成延伸到半导体衬底中的隔离区；蚀刻隔离区的顶部部分，以在隔离区中形成凹陷部；和形成延伸到凹陷部中且与隔离区的下部分重叠的栅极堆叠。在栅极堆叠的相对侧上形成源极区和漏极区。栅极堆叠、源极 区和漏极区为MOS装置的部分。
根据本发明的一些实施例，一种方法包含：形成从半导体衬底的顶部表面延伸到半导体衬底中的第一和第二STI区；和蚀刻第一STI区以形成从第一STI区的顶部表面延伸到第一STI区中的凹陷部。第一STI区包含位于凹陷部之下的下部分。所述方法进一步包含：形成与第一STI区的下部分重叠的第一栅极堆叠；形成在半导体衬底的顶部表面上方且与之接触的第二栅极堆叠；在第一栅极堆叠的相对侧上形成第一源极/漏极区；和在第二栅极堆叠的相对侧上形成第二源极/漏极区。第二源极/漏极区的一者与第二STI区的侧壁接触。在第一源极/漏极区和第二源极/漏极区上方形成ILD。执行平坦化以使第一栅极堆叠的顶部表面与第二栅极堆叠的顶部表面共面。
根据本发明的一些实施例，一种集成电路结构包含半导体衬底。HVMOS装置包含具有低于半导体衬底的顶部表面的部分的栅极电介质。栅极电极在所述栅极电介质上方，其中栅极电极具有低于半导体衬底的顶部表面的部分。源极区和漏极区在栅极电介质的相对侧上。
附图说明
当结合附图阅读时自下列实施方式最佳地理解本发明的方面。注意，根据业界中的标准实践，各种特征未按比例绘制。事实上，为讨论清晰起见，各种特征的尺寸可任意增大或减小。
图1到18描绘根据一些实施例的形成n型高压金属氧化物半导体(HVMOS)装置和n型中压金属氧化物半导体(MVMOS)(或低压金属氧化物半导体(LVMOS))装置的中间阶段的横截面图。
图19描绘根据一些实施例的n型HVMOS装置的俯视图。
图20描绘根据一些实施例的p型HVMOS装置和p型MV/LV MOS装置的横截面图。
图21描绘根据一些实施例的形成HVMOS装置和MV/LV MOS装置的程序流程。
具体实施方式
下列揭示内容提供许多不同实施例或实例以用于实施本发明的不同特征。下文中描述组件和布置的特定实例以简化本发明。当然，这些仅为实例且不意在为限制性的。举例来说，在下列描述中，在第二特征部上方或上形成第一特征部可包含所述第一特征部和所述第二特征部直接接触形成的实施例，且也可包含额外特征部可形成在所述第一特 征部与所述第二特征部之间，使得所述第一特征部和所述第二特征部可不直接接触的实施例。另外，本发明可在各种实例中重复元件符号和/或字母。此重复出于简化和清晰的目的，且本身不规定所讨论的各种实施例和/或配置之间的关系。
此外，为便于描述，可在本文中使用例如“在……下层”、“在……下”、“下”、“上覆”、“上”和类似者的空间相对术语以描述一个元件或特征部与另一元件或特征部(诸元件或特征部)的关系(如在图式中描绘)。所述空间相对术语意在涵盖除在图中描绘的定向以外的装置在使用或操作中的不同定向。设备可经另外定向(旋转90度或按其它定向)且也可相应地解释本文中使用的空间相对描述符。
根据各种例示性实施例提供高压(HV)金属氧化物半导体(MOS)装置和其形成方法。描绘形成所述HV MOS装置的中间阶段。讨论一些实施例的一些变体。遍及各种视图和描绘性实施例，相同元件符号用来指定相同元件。
图1到18描绘根据一些实施例的形成HV MOS装置的中间阶段的横截面图。在图1到18中展示的步骤也在图21中展示的程序流程300中示意性描绘。
图1描绘晶片10，其包含半导体衬底20和形成于半导体衬底20的顶部表面处的特征部。根据本发明的一些实施例，半导体衬底20包括晶体硅、晶体锗、硅锗、III-V族化合物半导体，例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP和/或类似物。半导体衬底20也可为块体半导体衬底或绝缘体上半导体(SOI)衬底。根据一些例示性实施例，半导体衬底20为p型，且具有低于约1015/cm2的掺杂浓度。
半导体衬底20包含在装置区100的第一部分和在装置区200的第二部分。装置区100为其中待形成HV MOS装置186(图18)的HV装置区。装置区200为其中待形成MOS装置286(图18)的装置区。MOS装置286经配置以在低于HV MOS装置186的各自操作电压(和电源电压)的操作电压(和电源电压)下操作。根据一些例示性实施例，装置区200为低压(LV)MOS装置区或中压(MV)MOS装置区。应了解，HV、MV和LV的概念是相对于彼此来说的。HV MOS装置经配置以在高于MV MOS装置的操作电压的操作电压下操作(且具有高于MV MOS装置的电源电压的电源电压)，且MV MOS装置经配置以在高于LV MOS装置的操作电压的操作电压下操作(且具有高于LV MOS装置的电源电压的电源电压)。同样地，MV装置可耐受(而不受损)的最大电压低于HV装置可耐受(而不受损)的最大电压，且LV装置可耐受(而不受损)的最大电压低于MV装置可耐受(而不受损)的最大电压。根据一些例示性实施例，HV MOS装置的操作电压在约3.0V与约3.3V之间，MV MOS装置的操作电压和电源电压在约1.5V与约2.0V之间，且LV MOS装置的操作电压和电源电压在约0.7V与约1.0V之间。
图1到4描绘浅沟槽隔离(STI)区的形成。各自步骤在图21中展示的程序流程中展示为步骤302。参考图1，垫层22和掩模层24经形成于半导体衬底20上。垫层22可包含由氧化硅形成的薄膜，其可(例如)使用热氧化程序形成。垫层22可充当半导体衬底20与掩模层24之间的粘合层。垫层22也可充当用于蚀刻掩模层24的蚀刻停止层。根据本发明的一些实施例，(例如)使用低压化学气相沉积(LPCVD)由氮化硅形成掩模层24。根据其它实施例，通过硅的热氮化、等离子体增强型化学气相沉积(PECVD)或等离子体阳极氮化形成。掩模层24在后续光刻程序期间用作硬掩模。光致抗蚀剂26经形成于掩模层24上，且接着经图案化以形成开口28。
参考图2，通过开口28蚀刻掩模层24和垫层22，从而暴露下层半导体衬底20。暴露的半导体衬底20接着经蚀刻，从而形成沟槽32。接着移除光致抗蚀剂26。接着，可执行清洗以移除半导体衬底20的原生氧化物。可使用经稀释HF来执行清洗。
接着，如在图3中展示，将(诸)电介质材料34充填到沟槽32中。根据本发明的一些实施例，电介质材料34包含内衬开口32的底部和侧壁的衬氧化物。衬氧化物可为通过氧化暴露的衬底20的表面层形成的热氧化物层。根据本发明的替代实施例，使用现场水汽生成(ISSG)形成衬氧化物。根据其它实施例，使用可形成保形氧化物层的沉积技术(例如原子层沉积(ALD)、选择性区域化学气相沉积(SACVD)或类似物)来形成衬氧化物。衬氧化物的形成使沟槽32的隅角圆化(图2)，此导致电场减弱，且因此改进所得集成电路的性能。
在形成衬氧化物后，使用另一电介质材料充填沟槽32的剩余部分。根据本发明的一些实施例，充填材料包含氧化硅，且也可使用其它电介质材料，例如SiN、SiC、SiON或类似物。充填电介质材料可使用高深宽比程序(HARP)、高密度等离子体化学气相沉积(HDP)、SACVD、大气压化学气相沉积(APCVD)或类似物充填。
接着，可执行蒸汽退火。蒸汽退火可包含使用引入的蒸汽(H2O)在(例如)约600℃与约700℃之间的高温下退火在图3中展示的结构。
接着执行平坦化(例如化学机械抛光(CMP))以移除掩模层24的顶部表面上方的电介质材料34的过量部分，从而导致在图4中展示的结构。掩模层24可充当CMP停止层。电介质材料34的剩余部分形成浅沟槽隔离(STI)区36和38。如在图4中展示，STI区36和38的底部表面基本上彼此齐平，(例如)具有小于STI区36和38的高度的约10％的高度差。
在后续步骤中，移除掩模层24和垫层22，接着进行一些清洗程序，且所得结构在图5中展示。掩模层24(当由氮化硅形成时)可使用热H3PO4通过湿式清洗程序移除，而 垫层22(当由氧化硅形成时)可使用稀释HF在湿式蚀刻程序中移除。
图6到8描绘通过多个布植程序形成多个掺杂区。多个掺杂区包含深n阱区40、高压p阱(HVPW)区42、高压N阱(HVNW)区44和p阱区46。用于形成区40、42、44和46的布植程序可以任何顺序布置。根据一些例示性实施例，光致抗蚀剂(未展示)经形成以覆盖晶片10，其中待形成深n阱区40的区暴露于光致抗蚀剂中的开口。n型掺杂剂(例如磷、砷和/或锑)经布植深入半导体衬底20中以形成深n阱区40。接着移除光致抗蚀剂。
接着，如在图6中展示，形成且图案化光致抗蚀剂48。接着执行p型掺杂剂布植以便形成HVPW区42。各自步骤在图21中展示的程序流程中展示为步骤304。HVPW区42可使用硼和/或铟布植。在布植后，根据一些例示性实施例，HVPW区42可具有在约1015/cm3与约1016/cm3之间的p型掺杂浓度。接着移除光致抗蚀剂48。
接着，如在图7中展示，形成且图案化光致抗蚀剂50。接着执行n型掺杂剂布植以便形成HVNW区44。各自步骤在图21中展示的程序流程中展示为步骤306。HVNW区44可使用磷、砷和/或锑布植。在布植后，根据一些例示性实施例，HVNW区44可具有在约1015/cm3与约1016/cm3之间的n型掺杂浓度。接着移除光致抗蚀剂50。HVNW区44的底部接合到深n阱区40。
图8描绘在装置区200中形成p阱区46。根据本发明的一些实施例，形成且图案化光致抗蚀剂52以覆盖装置区100。接着执行p型掺杂剂布植以便形成p阱区46。p阱区46可使用硼或铟布植。p阱区46具有高于HVNW区44和HVPW区42的掺杂浓度的p型掺杂浓度。举例来说，根据一些例示性实施例，p阱区46可具有在约1016/cm3与约1017/cm3之间的p型掺杂浓度。接着移除光致抗蚀剂52。
在后续步骤中，如在图9中展示，形成且图案化光致抗蚀剂54以形成开口56。STI区36的中间部分通过开口56暴露。STI区38、HVNW区44和一些HVPW区42被光致抗蚀剂54覆盖。
参考图10，蚀刻暴露的STI区36的顶部部分，从而形成延伸到STI区36的凹陷部58。各自步骤在图21中展示的程序流程中展示为步骤310。可使用蚀刻气体通过干式蚀刻程序执行所述蚀刻。根据本发明的一些实施例，STI区36包括氧化硅，且HF用作蚀刻气体。也可使用蚀刻溶液通过湿式蚀刻程序执行所述蚀刻。根据本发明的一些实施例，STI区36包括氧化硅，且使用包含稀释HF的蚀刻溶液。由于所述蚀刻，STI区36的中心上部分被移除，而STI区36的下部分36B保留。另外，归因于光致抗蚀剂54的保护，STI区36的上部分36A保留于凹陷58的一侧(例如漏极侧)上或相对侧上。
STI区36的剩余底部部分36B具有厚度T2。STI区36的剩余上部分36A具有厚度 T1。可调整蚀刻程序以调整所得HV MOS装置的可耐受电压与饱和电流。根据一些实施例，凹陷部58的深度D2可在约与约之间的范围中。最佳深度D2受各种因素影响，例如栅极电介质276的厚度(图18)、栅极堆叠274的最小容许高度等。在蚀刻后，移除光致抗蚀剂54，如在图11中展示。
图19描绘根据本发明的一些实施例的STI区36和对应凹陷部58的俯视图。凹陷部58可由STI部分36A围绕。根据本发明的其它实施例，凹陷部58延伸到STI区36的边缘36'，其中边缘36'可为面向所得HVMOS装置的一侧(例如源极侧)的边缘。
接着，参考图12，栅极堆叠160和260分别形成于装置区100和200中。各自步骤在图21中展示的程序流程中展示为步骤312。栅极堆叠160和260可在后续步骤中被移除且被替换栅极替换。因此，栅极堆叠160和260根据一些实施例为虚设栅极。栅极堆叠160包含栅极电介质164和栅极电极166。栅极堆叠260包含栅极电介质264和栅极电极266。栅极电介质164和264可由氧化硅、氮化硅、碳化硅或类似物形成。栅极电极166和266根据一些实施例可包含多晶硅。栅极电极166和266也可由其它导电材料(例如金属、金属合金、金属硅化物、金属氮化物和/或类似物)形成。根据本发明的一些实施例，栅极堆叠160和260分别进一步包含硬掩模168和268。硬掩模168和268可由(例如)氮化硅形成，同时也可使用其它材料(例如碳化硅、氮氧化硅和类似物)。根据替代性实施例，未形成硬掩模168和268。
栅极间隔件162和262分别形成于栅极堆叠160和260的侧壁上。各自步骤在图21中展示的程序流程中也展示为步骤312。根据一些实施例，栅极间隔件162和262的各者包含氧化硅层和在所述氧化硅层上的氮化硅层。所述形成可包含沉积毯覆式电介质层，且接着执行各向异性蚀刻以移除毯覆式电介质层的水平部分。可用沉积方法包含PECVD、低压化学气相沉积(LPCVD)、次大气压化学气相沉积(SACVD)和其它沉积方法。
参考图13，源极和漏极区(下文中称为源极/漏极区)170形成于HVNW区44中。源极/漏极区170的一者充当源极区，且另一者充当漏极区。通道173正好位于STI区36之下以用于传导源极/漏极区170之间的电流。源极/漏极区270也形成于p阱区46中。各自步骤在图21中展示的程序流程中展示为步骤314。源极/漏极区170和270可在相同布植程序中同时形成。源极/漏极区170和270为n型，且经重度掺杂(例如)到在约1019/cm3与约1021/cm3之间的n型掺杂浓度，且称为N+区。形成光致抗蚀剂(未展示)以界定源极/漏极区170和270的位置。源极/漏极区170可通过HVNW区44与STI区36间隔开。另一方面，源极/漏极区170可具有与栅极间隔件262的边缘对准的边缘。
另外，拾取区171(其为p型)通过额外布植步骤形成于HVPW区42的表面处。P 型拾取区171也可具有在约1019/cm3与约1021/cm3之间的p型掺杂浓度，且称为P+区。
参考图14，接触蚀刻停止层(CESL)72形成于栅极堆叠160和260与源极/漏极区170和270上方。各自步骤在图21中展示的程序流程中展示为步骤316。根据本发明的一些实施例，CESL 72由选自氮化硅、碳化硅或其它电介质材料的材料形成。层间电介质(ILD)74形成于CESL 72上方。各自步骤在图21中展示的程序流程中也展示为步骤316。ILD 74经毯覆式形成达高于栅极堆叠160和260的顶部表面的高度。ILD 74可使用(例如)可流动化学气相沉积(FCVD)由氧化物形成。ILD 74也可为使用旋涂形成的旋涂式玻璃。举例来说，ILD 74可由磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺杂硼的磷硅玻璃(BPSG)、原硅酸四乙酯(TEOS)氧化物、TiN、SiOC或其它低k非多孔电介质材料形成。
图15描绘平坦化步骤，其使用(例如)CMP执行。各自步骤在图21中展示的程序流程中展示为步骤318。执行CMP以移除ILD 74和CESL 72的过量部分，直到栅极堆叠160暴露。因为栅极堆叠160形成于STI区36中的凹陷中，所以栅极堆叠160的顶部表面低于栅极堆叠260的顶部表面。因此，在平坦化中，栅极堆叠260的顶部部分被移除，且剩余的栅极堆叠160的高度低于剩余的栅极堆叠260的高度。平坦化可在硬掩模168(若存在)上停止。替代地，在平坦化中移除硬掩模168，且暴露栅极电极166。
图16描绘根据一些实施例的替换栅极174和274的形成。栅极堆叠160和260(图15)被移除，且分别被替换栅极堆叠174和274替换，如在图16中展示。各自步骤在图21中展示的程序流程中展示为步骤320。栅极堆叠174包含栅极电介质176和栅极电极178。栅极堆叠274包含栅极电介质276和栅极电极278。
栅极电介质176和276可包含高k电介质材料，例如氧化铪、氧化镧、氧化铝或类似物。栅极电极178和278可包含由TiN、TaN或类似物形成的导电扩散障壁层。栅极电极178和278也包含导电层，例如导电扩散障壁层上方的含金属层，其中含金属层可由钴、铝或其多层形成。形成方法包含PVD、CVD或类似物。接着执行平坦化步骤(例如，CMP)以移除栅极电介质和栅极电极的过量部分，从而形成图16中的结构。
图17描绘在替换栅极174和274上方形成ILD 80。各自步骤在图21中展示的程序流程中展示为步骤322。ILD 80可由选自用于形成ILD 74的相同候选材料的材料形成。ILD 74和ILD 80的材料可彼此相同或不同。因为在不同程序步骤中形成ILD 74和ILD 80，所以ILD74和ILD 80之间可存在可区分介面79，而无关乎ILD 74和ILD 80是由相同材料还是不同材料形成。根据其它实施例，ILD 74和ILD 80之间不存在可区分介面。
在图16和图17中描绘的实施例中，通过替换虚设栅极而形成替换栅极，且ILD 80经形成于替换栅极上方。根据替代性实施例，在如在图15中展示的平坦化之后，在不使用替换栅极替换栅极堆叠160和260的情况下形成ILD 80。栅极电介质164和264与栅极电极166和266因此保留于最终结构中。
参考图18，形成源极/漏极硅化物区82和接触柱塞84。各自步骤在图21中展示的程序流程中展示为步骤324。形成程序可包含：在ILD 74和ILD 80中形成接触柱塞开口以暴露源极/漏极区170/270和栅极电极176/276；形成金属层(未展示)以延伸到接触柱塞开口中；执行退火以形成源极/漏极硅化物区82；移除金属层的未反应部分；和充填接触柱塞开口以形成接触柱塞84。在未替换栅极电极166和266(图15)的实施例中，栅极硅化物(未展示)也可形成于栅极电极166和266的顶部上。因此形成MOS装置186和286。MOS装置186包含栅极电极178、栅极电介质(包含36和176)和源极/漏极区170。MOS装置286包含栅极电极278、栅极电介质276和源极/漏极区270。
MOS装置186为HV MOS装置。MOS装置286为MV MOS装置或LV MOS装置，其中选择适合于MOS装置286的操作电压电平的栅极电介质276(和176)的厚度。HV MOS装置186的栅极电介质包含STI区36的剩余部分，其足够厚以维持高压。另外，栅极电介质176也可形成为HVMOS装置186的栅极电介质的部分。MV/LV MOS装置286具有栅极电介质276，其比栅极电介质36的厚度厚。另外，栅极电介质176和276可在相同形成程序中形成，且因此具有相同厚度，且由相同电介质材料形成。
图19描绘HV MOS装置的部分的俯视图，其中描绘源极/漏极区170。源极区170可与STI区360间隔开，或可与STI区360的边缘36'接触。
图20描绘p型HV MOS装置186'和p型MOS装置286'(LV或MV装置)的横截面图，其与n型MOS装置186和286形成于相同的半导体衬底20上。使用与在图18中相同的元件符号标记在图20中所描绘的区，其中添加符号(')以展示其为图18中的对应区。可通过MOS装置186和286的形成(图18)实现材料和形成程序，其中图20中各种描绘区的导电类型与在图18中展示的对应区反转。
本发明的实施例具有一些有利特征。期望使HV MOS装置和LV/MV装置共享用于形成替换栅极的程序以便降低制造成本。然而，HV MOS装置具有厚栅极电介质，且因此HV MOS装置的栅极电介质的顶部表面可与LV/MV MOS装置的虚设栅极电极的顶部表面基本上等高，或甚至更高。因此，用于暴露LV/MV MOS装置的虚设栅极电极的平坦化可导致HV MOS装置的虚设栅极电极的完全移除。此意谓，对于HV MOS装置，无法通过共享用于形成LV/MVMOS装置的替换栅极的相同程序形成替换栅极。通过使STI区凹陷且在所述凹陷部中形成HVMOS装置的栅极电极，减小HV MOS装置与 LV/MV MOS装置的顶部表面之间的高度差，且可在不完全移除HV MOS装置的虚设栅极电极的情况下执行平坦化。另外，根据本发明的实施例，STI区用作HV MOS装置的栅极电介质，且因此降低生产成本。
根据本发明的一些实施例，一种方法包含：形成延伸到半导体衬底中的隔离区；蚀刻隔离区的顶部部分，以在隔离区中形成凹陷部；和形成延伸到凹陷部中且与隔离区的下部分重叠的栅极堆叠。源极区和漏极区形成于栅极堆叠的相对侧上。栅极堆叠、源极区和漏极区为MOS装置的部分。
根据本发明的一些实施例，一种方法包含：形成从半导体衬底的顶部表面延伸到半导体衬底中的第一和第二STI区；和蚀刻第一STI区以形成从第一STI区的顶部表面延伸到第一STI区中的凹陷部。第一STI区包含位于凹陷之下的下部分。所述方法进一步包含：形成与第一STI区的下部分重叠的第一栅极堆叠；形成在半导体衬底的顶部表面上方且与之接触的第二栅极堆叠；在第一栅极堆叠的相对侧上形成第一源极/漏极区；和在第二栅极堆叠的相对侧上形成第二源极/漏极区。第二源极/漏极区的一者与第二STI区的侧壁接触。在第一源极/漏极区和第二源极/漏极区上方形成ILD。执行平坦化以使第一栅极堆叠的顶部表面与第二栅极堆叠的顶部表面共面。
根据本发明的一些实施例，一种集成电路结构包含半导体衬底。HVMOS装置包含具有低于半导体衬底的顶部表面的部分的栅极电介质。栅极电极在所述栅极电介质上方，其中栅极电极具有低于半导体衬底的顶部表面的部分。源极区和漏极区在栅极电介质的相对侧上。
前文概述若干实施例的特征，使得所属领域的技术人员可较好地理解本发明的方面。所属领域的技术人员应了解，其可容易将本发明用作设计或修改用于执行相同目的和/或达成本文引入的实施例的相同优势的其它程序和结构的基础。所属领域的技术人员也应认识到，这些等效构造不脱离本发明的精神和范围，且其可在不脱离本发明的精神和范围的情况下在本文中进行各种改变、替换和更改。
符号说明
10 晶片
20 半导体衬底
22 垫层
24 掩模层
26 光致抗蚀剂
28 开口
32 沟槽
34 电介质材料
36 浅沟槽隔离区
36A 上部分
36B 下部分
36' 边缘
38 浅沟槽隔离区
40 深n阱区
42 高压p阱区
44 高压N阱区
46 p阱区
48 光致抗蚀剂
50 光致抗蚀剂
52 光致抗蚀剂
54 光致抗蚀剂
56 开口
58 凹陷
72 接触蚀刻停止层
74 层间电介质
79 可区分介面
80 ILD
82 源极/漏极硅化物区
84 接触柱塞
100 装置区
160 栅极堆叠
162 栅极间隔件
164 栅极电介质
166 栅极电极
168 硬掩模
170 源极和漏极区
171 拾取区
173 通道
174 替换栅极
176 栅极电介质
178 栅极电极
186 n型HV MOS装置
186' p型HV MOS装置
200 装置区
260 栅极堆叠
262 栅极间隔件
264 栅极电介质
266 栅极电极
268 硬掩模
270 源极/漏极区
274 替换栅极
276 栅极电介质
278 栅极电极
286 HV MOS装置
286' p型MOS装置
300 程序流程
302 步骤
304 步骤
306 步骤
310 步骤
312 步骤
314 步骤
316 步骤
318 步骤
320 步骤
322 步骤
324 步骤
D2 深度
T1 厚度
T2 厚度。

Claims (10)

1.一种方法，其包括：
形成延伸到半导体衬底中的隔离区；
蚀刻所述隔离区的顶部部分以在所述隔离区中形成凹陷部；
形成延伸到所述凹陷部中且与所述隔离区的下部分重叠的栅极堆叠；和
在所述栅极堆叠的相对侧上形成源极区和漏极区，其中所述栅极堆叠、所述源极区和所述漏极区为金属氧化物半导体MOS装置的部分。
2.根据权利要求1所述的方法，其中所述MOS装置为高压HV MOS装置，且所述方法进一步包括：
布植所述半导体衬底以形成HV n阱区和HV p阱区，其中所述HV n阱区和HVp阱区的至少一者包括位于所述隔离区之下的部分。
3.根据权利要求1所述的方法，其中蚀刻所述隔离区的所述顶部部分的中间部分，且在所述蚀刻后，所述隔离区的所述顶部部分进一步包括在所述经蚀刻中间部分的一侧上剩余的额外部分。
4.根据权利要求1所述的方法，其中所述隔离区具有与所述半导体衬底的顶部表面基本上共面的顶部表面。
5.根据权利要求1所述的方法，其包括同时形成所述隔离区和额外隔离区，其中在所述蚀刻期间，不蚀刻所述额外隔离区。
6.根据权利要求1所述的方法，其进一步包括：
当所述栅极堆叠形成时，同时形成额外MOS装置的额外栅极堆叠，其中所述额外栅极堆叠正好在所述半导体衬底的未凹陷部分上方；和
执行平坦化以使所述栅极堆叠的顶部表面与所述额外栅极堆叠齐平。
7.一种方法，其包括：
形成从半导体衬底的顶部表面延伸到所述半导体衬底中的第一和第二浅沟槽隔离STI区；
蚀刻所述第一STI区以形成从所述第一STI区的顶部表面延伸到所述第一STI区中的凹陷部，其中所述第一STI区包括位于所述凹陷部之下的下部分；
形成与所述第一STI区的所述下部分重叠的第一栅极堆叠；
形成在所述半导体衬底的顶部表面上方且与之接触的第二栅极堆叠；
在所述第一栅极堆叠的相对侧上形成第一源极/漏极区；
在所述第二栅极堆叠的相对侧上形成第二源极/漏极区，其中所述第二源极/漏极区的一者与所述第二STI区的侧壁接触；
在所述第一源极/漏极区和所述第二源极/漏极区上方充填层间电介质ILD；和
执行平坦化以使所述第一栅极堆叠的顶部表面与所述第二栅极堆叠的顶部表面共面。
8.根据权利要求7所述的方法，其中所述第一栅极堆叠充当所述平坦化的停止层，且通过所述平坦化移除所述第二栅极堆叠的顶部部分。
9.根据权利要求7所述的方法，其中所述第一栅极堆叠的部分低于所述半导体衬底的所述顶部表面，且整个所述第二栅极堆叠高于所述半导体衬底的顶部表面。
10.一种集成电路结构，其包括：
半导体衬底；
高压金属氧化物半导体HVMOS装置，其包括：
栅极电介质，其包括第一部分，其中所述栅极电介质的顶部表面低于所述半导体衬底的顶部表面；和
栅极电极，其在所述栅极电介质上方，其中所述栅极电极包括低于所述半导体衬底的所述顶部表面的部分；和
源极区和漏极区，其在所述栅极电介质的相对侧上。
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