CN106876366A - Semi-conductor test structure and stress migration test method - Google Patents
Semi-conductor test structure and stress migration test method Download PDFInfo
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- CN106876366A CN106876366A CN201510923178.8A CN201510923178A CN106876366A CN 106876366 A CN106876366 A CN 106876366A CN 201510923178 A CN201510923178 A CN 201510923178A CN 106876366 A CN106876366 A CN 106876366A
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- 238000012360 testing method Methods 0.000 title claims abstract description 259
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000013508 migration Methods 0.000 title claims abstract description 22
- 230000005012 migration Effects 0.000 title claims abstract description 21
- 238000010998 test method Methods 0.000 title claims abstract description 13
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
A kind of semi-conductor test structure and stress migration test method, in wafer Cutting Road along Cutting Road bearing of trend be sequentially arranged the first weld pad, the second weld pad ..., N+2 weld pads, except the first weld pad, the second weld pad, the sub- test structure needed for all arranging a stress migration test between remaining any two adjacent welding-pad；During test, be respectively provided between the first weld pad and the second weld pad, between the first weld pad and N+2 weld pads it is unidirectional conduct structure alternatively make a) the first weld pad to through N+2 weld pads ..., turn on to the first test path of P weld pads, Kelvin's four-wire method obtains the resistance of the individual sub- test structures of common N+1-P in the path；Or b) the first weld pad through the second weld pad ..., to Q weld pads the second test path turn on, Q>(P+1), Kelvin's four-wire method obtains the residue P-1 resistance of sub- test structure.Area size shared by test structure is above configuration reduced, testing efficiency is improve.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of semi-conductor test structure and stress migration
Method of testing.
Background technology
In ic manufacturing process, the stress migration of metal interconnecting layer, especially conductive plunger
(Stress-Migration, SM) phenomenon causes open circuit and the short circuit of metal interconnection structure, makes element leakage
Stream increases.As footprint constantly expands, device size constantly reduces, the line of metal interconnecting wires
Wide constantly to reduce, current density constantly rises, it is easier to which stress is migrated and failed, and has become one
Important integrity problem.
Stress migration is at a certain temperature, because various material thermal expansion coefficients are different, so in difference
Storeroom formed stress so that intercrystalline small space is to stress collection in metal interconnecting wires or through hole
In place aggregation formed cavity physical phenomenon.The cavity that stress migration is formed reaches and just makes to a certain degree
There is open circuit in the metal interconnecting wires in integrated circuit, so as to cause the failure of device.
In the prior art, in order to improve device density, general using multiple layer metal interconnection, every layer of metal is mutual
The stress migration of line all needs test, and this causes test process to take.Additionally, also result in test structure
Shared region is larger, however, utilizing region to improve the effective of wafer, is typically arranged on test structure
In narrow and small Cutting Road, this has been further exacerbated by above-mentioned contradiction.
In view of this, the present invention provides a kind of semi-conductor test structure, and uses above-mentioned semiconductor test knot
Structure carries out the method for testing of stress migration, and to improve testing efficiency, reduction accounts for area size.
The content of the invention
The problem that the present invention is solved is shared by the existing test structure to metal interconnection structure stress migration test
Region is big, test is time-consuming.
To solve the above problems, an aspect of of the present present invention provides a kind of semi-conductor test structure, the test
Structure is formed in the Cutting Road of wafer, and the test structure includes：
The first weld pad for being arranged successively along Cutting Road bearing of trend, the second weld pad, the 3rd weld pad ...,
N+2 weld pads, N >=2；
Realize that first of unilateal conduction between first weld pad and the second weld pad unidirectionally conducts structure；
Realize that unidirectionally conducted between first weld pad and N+2 weld pads second unidirectionally conducts structure,
The second unilateal conduction structure structure that conducts unidirectional with first realizes second weld pad to the first weldering
Pad, the first weld pad select a conducting to N+2 weld pads；
The first sub- test structure for being connected between the second weld pad and the 3rd weld pad, it is connected to the 3rd weld pad and
The second sub- test structure between four weld pads ..., be connected between N+1 weld pads and N+2 weld pads
The sub- test structures of N；
Any one and first weld pad are suitable for use as test signal in second weld pad to N+2 weld pads
Apply end, two neighboring in remaining weld pad is suitable for use as between two test leads correspondence obtains two adjacent welding-pads
The resistance of sub- test structure.
Alternatively, the described first unidirectional structure that conducts is for PN junction, nmos pass transistor or PMOS are brilliant
One kind in body pipe.
Alternatively, the described second unidirectional structure that conducts is for PN junction, nmos pass transistor or PMOS are brilliant
One kind in body pipe.
Alternatively, the described first sub- test structure, the second sub- test structure ..., N test knot
Part is identical in structure.
Alternatively, the described first sub- test structure, the second sub- test structure ..., N test knot
Structure is different.
Alternatively, the semi-conductor test structure be used for stress migration test, the first sub- test structure,
Second test structure ..., the sub- test structures of N be single conductive plunger, the string of single layer of conductive connector
It is coupled the cascaded structure of the stacked structure composition of structure or multilayer conductive connector.
Alternatively, the first weld pad, the second weld pad, the 3rd weld pad ..., N+2 weld pads it is in the same size.
Alternatively, the width of the Cutting Road is only capable of accommodating the first weld pad, the second weld pad, the 3rd weldering
Pad ... or N+2 weld pads.
A kind of method of above-mentioned semi-conductor test structure test stress migration, the semi-conductor test structure with
Processed through stress migration test in same operation with the semiconductor devices in semi-conductive substrate, the survey
Method for testing includes：
Apply end applying test current lead-through first in first weld pad, the test signal of P weld pads two to weld
Pad through N+2 weld pads, N+1 weld pads ..., to the first test path of P weld pads, N >=P
≥2；Choose N+2 weld pads on first test path ..., the phase in P+1 weld pads
Adjacent two weld pads obtain the resistance of the sub- test structure between two test lead as two test leads, correspondence,
Two test lead traversal N+2 weld pads ..., all two neighboring weld pads in P+1 weld pads, it is right
The common N+1-P resistance of sub- test structure should be obtained；
Apply end in first weld pad, the test signal of Q weld pads two and apply the Q welderings of test current lead-through
Pad through Q-1 weld pads ..., to the second test path of the first weld pad, (N+2) >=Q>(P+1)；
Choose and be located in second test path, the second weld pad ..., it is two neighboring in P+1 weld pads
Weld pad obtains the resistance of the sub- test structure between two test lead, described two as two test leads, correspondence
Test lead travel through the second weld pad ..., all two neighboring weld pads in P+1 weld pads, correspondence obtains altogether
The P-1 resistance of sub- test structure.
Alternatively, on first test path resistance of common N+1-P sub- test structures obtain with it is described
The common P-1 resistance of sub- test structure is obtained without sequencing in second test path.
Compared with prior art, technical scheme has advantages below：1) present invention is first in crystalline substance
Circle Cutting Road in along Cutting Road bearing of trend be sequentially arranged the first weld pad, the second weld pad, the 3rd weld pad ...,
The multiple weld pads such as N+2 weld pads, except the first weld pad, the second weld pad the two adjacent welding-pads, remaining is any
The sub- test structure of test needed for a stress migration is all arranged between two adjacent welding-pads, it is adjacent relative to every two
One group of weld pad, arranges a sub- test structure therebetween, and the present invention improves weld pad utilization rate, reduces test
Area size shared by structure；During test, by between the first weld pad and the second weld pad, the first weld pad and
The unidirectional structure that conducts being respectively provided between N+2 weld pads alternatively makes a) the first weld pad be welded to through N+2
Pad, N+1 weld pads ..., to P weld pads the first test path turn on, by the line of Kelvin four
Method of testing (Kelvin Contact) obtains the common N+1-P resistance of sub- test structure in the path；Or b)
Q weld pads through Q-1 weld pads ..., to the first weld pad the second test path turn on, Q>(P+1),
The resistance of remaining P-1 sub- test structure is obtained by 4-Wire Kelvin Test method.
2) in alternative, between the first weld pad and the second weld pad, between the first weld pad and N+2 weld pads respectively
The unidirectional structure that conducts for setting can be PN junction, nmos pass transistor or PMOS transistor or anti-
One kind in phase device, plurality of optional scheme is provided unidirectionally to conduct structure.
3) in alternative, the first sub- test structure, the second sub- test structure ..., N test
Structure can part it is identical, it is also possible to it is different；Specifically, for stress migration test, the first son
Test structure, the second test structure ..., the sub- test structures of N can be single conductive plunger, list
The cascaded structure that the cascaded structure of layer conductive plunger or the stacked structure of multilayer conductive connector are constituted.
4) in alternative, the first weld pad, the second weld pad, the 3rd weld pad ..., N+2 weld pads it is big
It is small consistent, be conducive to simplifying mask blank structure, and the compatibility of semi-conductor test structure can be improved.
5) in alternative, the width of Cutting Road is only capable of accommodating the first weld pad, the second weld pad, the 3rd
Weld pad ... or N+2 weld pads, the utilization ratio due to improve weld pad of the invention, for same
The sub- test structure of number, can reduce area size shared by test structure, thus the width of Cutting Road can
To reduce, the area of device region is improved.
Brief description of the drawings
Fig. 1 is the schematic diagram of the semi-conductor test structure of one embodiment of the invention；
Fig. 2 to Fig. 4 be the first sub- test structure in Fig. 1, the second sub- test structure ..., to N
The cross section structure schematic diagram of any three sub- test structures in test structure；
Fig. 5 and Fig. 6 is respectively semi-conductor test structure the showing during stress migration test in Fig. 1
It is intended to.
Specific embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 1 is the schematic diagram of the semi-conductor test structure of one embodiment of the invention.Fig. 2 to Fig. 4 is Fig. 1
In the first sub- test structure, the second sub- test structure ..., to any three in N test structures
The cross section structure schematic diagram of individual sub- test structure.
Below in conjunction with the semiconductor test knot for shown in Fig. 1 to Fig. 4, introducing one embodiment of the invention offer
Structure.
Shown in reference picture 1, the test structure is formed in the Cutting Road (not shown) of wafer, including：
The first weld pad P1, the second weld pad P2, the 3rd weld pad arranged successively along Cutting Road bearing of trend
P3 ..., N+2 weld pads P (N+2), N >=2；
Realize that first of unilateal conduction between the first weld pad P1 and the second weld pad P2 unidirectionally conducts structure 11；
Realize unidirectional the second unidirectional conductance for conducting between the first weld pad P1 and N+2 weld pads P (N+2)
Logical structure 12, unidirectionally conduct structure 11 realizes the second weld pad P2 to the second unilateal conduction structure 12 with first
Turned on to N+2 weld pads P (N+2) alternatively to the first weld pad P1, the first weld pad P1；
The first sub- test structure A1 for being connected between the second weld pad P2 and the 3rd weld pad P3, it is connected to the 3rd
The second sub- test structure A2 between weld pad P3 and the 4th weld pad P4 ..., be connected to N+1 weld pads
The sub- test structure AN of N between P (N+1) and N+2 weld pads P (N+2)；
Second weld pad P2 is to any one and the first weld pad P1 in N+2 weld pads P (N+2)
It is suitable for use as two test signals and applies end applying test signal F+, F-, it is two neighboring suitable in remaining weld pad
In the resistance as the sub- test structure between two test leads correspondence two adjacent welding-pads of acquisition.
In the present embodiment, first it is unidirectional conduct structure 11 and unidirectionally conduct structure 12 with second be respectively
Two reverse PN junctions.In other embodiments, a) first unidirectional to conduct structure 11 can be NMOS
Transistor, the second unidirectional structure 12 that conducts is for PMOS transistor, or b) first unidirectionally conducts knot
Structure 11, second unidirectionally conducts structure 12 and is respectively PMOS transistor and nmos pass transistor, grid
During high voltage, the first unidirectional structure 11, second that conducts unidirectionally conducts the alternatively of structure 12 conducting.
In specific implementation process, to simplify the lay photoetching mask plate figure of each weld pad and improving test structure
Compatibility, the first weld pad P1, the second weld pad P2, the 3rd weld pad P3 ..., N+2 weld pads P (N+2)
It is in the same size.
In a kind of method of testing, the semi-conductor test structure shown in Fig. 1 is used to test answering for semiconductor structure
Power is migrated.Accordingly, the first sub- test structure A1, the second test structure A2 ..., N survey
Part is identical in examination structure AN, and part is different.Specifically, N number of sub- test structure can be
A) the single conductive plunger V1 shown in Fig. 2, wherein upper and lower double layer of metal layer pattern M1, M2 respectively with
Two adjacent weld pads are connected, or b) single layer of conductive connector V1, V2, V3, V4 shown in Fig. 3
Cascaded structure, positioned at two metal layer pattern Ma, Mb of cascaded structure head and the tail welderings adjacent with two respectively
Pad is connected, or the series connection that c) stacked structure of multilayer conductive connector V1, V2, the V3 shown in Fig. 4 is constituted
Structure, weld pad phase two metal layer pattern Ma, Mb at the top of stacked structure adjacent with two respectively
Even.
It should be noted that in Fig. 2, only with illustrate the first metal layer M1 and second metal layer M2 it
Between conductive plunger V1 as a example by illustrate, the first sub- test structure A1, the second test structure A2 ...,
The sub- test structure AN of N can also be the conduction between second metal layer M2 and the 3rd metal level M3
Connector, the conductive plunger ... between the 3rd metal level M3 and the 4th metal level M4.In Fig. 3, only with
Illustrate conductive plunger V1, V2, V3, the V4 between the first metal layer M1 and second metal layer M2
As a example by illustrate, the first sub- test structure A1, the second test structure A2 ..., N test
Structure AN can also be that some conductive plungers between second metal layer M2 and the 3rd metal level M3 are constituted
Cascaded structure, the string that some conductive plungers between the 3rd metal level M3 and the 4th metal level M4 are constituted
It is coupled structure ....In Fig. 4, only led between the first metal layer M1 for illustrating and the 4th metal level M4
Illustrated as a example by the cascaded structure that electric plug V1, V2, the stacked structure of V3 are constituted, the first son test
Structure A1, the second test structure A2 ..., the sub- test structure AN of N can also be the first metal
Layer M1 and the 3rd metal level M3 between some conductive plungers stacked structure into cascaded structure, second
The tandem junction that the stacked structure of some conductive plungers between metal level M2 and the 4th metal level M4 is constituted
Structure ....
Based on above-mentioned semi-conductor test structure, in the semi-conductor test structure and same semi-conductive substrate
Semiconductor devices is processed in same operation through stress migration test, for example, heat same temperature high, this
Invention provides a kind of method of testing of test stress migration, including：
First, shown in reference picture 5, tested in the first weld pad P1, P weld pads PP two by probe and believed
Number apply end F+, F- and apply first to test electric current I1, second it is unidirectional conduct structure 12 and turn on, first is single
End to structure 11 is conducted, now, the first weld pad P1 is through N+2 weld pads P (N+2), N+1
Weld pad P (N+1) ..., to P weld pads PP the first test path be switched on, N >=P >=2.
Because each pad is smaller, stitch of its size substantially with probe is suitable, if thus each pad is selected
After applying end for test signal, it is impossible to be chosen as another test signal again and apply end or test lead.
Choose N+2 weld pads P (N+2) on the first test path ..., P+1 weld pads P
(P+1) the two neighboring weld pad in obtains two and tests as two test lead S+, S- by two probes correspondence
Voltage V1, test electric current I1 that test voltage V1/ applied of the end between S+, S-, can obtain two tests
The resistance of sub- test structure of the end between S+, S-；Two test leads S+, S- traversal N+2 weld pads P
(N+2) ..., all two neighboring weld pads in P+1P (P+1) weld pad, can correspond to and obtain P
The resistance RP of sub- test structure AP, the resistance R (P+1) of P+1 test structures A (P+1) ...,
The common N+1-P of the resistance RN resistance of sub- test structure of the sub- test structure AN of N.
It is understood that in said process, the resistance R1 of the first sub- test structure A1, the second son are surveyed
The resistance R2 of examination structure A2 ..., the resistance R (P-1) of P-1 test structures A (P-1) altogether
The resistance of P-1 sub- test structure is not obtained.
Then, shown in reference picture 6, end is applied in the first weld pad P1, the test signals of Q weld pads PQ two
F-, F+ apply second and test electric current I2, and first unidirectionally conducts structure 11 turns on, and second unidirectionally conducts
Structure 12 is ended, now, Q weld pads PQ through Q-1 weld pads P (Q-1) ..., to first weldering
The second test path for padding P1 is switched on, (N+2) >=Q>(P+1).
Q>(P+1), i.e. Q weld pads PQ is on the first test path, except P weld pads PP,
P+1 weld pads P (P+1) any weld pad outward.
Choose and be located in the second test path, the second weld pad P2 ..., in P+1 weld pads P (P+1)
Two neighboring weld pad as two test lead S+, S-, two test lead S+, S- are obtained by two probes correspondence
Between voltage V2, the test electric current I2 that test voltage V2/ is applied, two test lead S+, S- can be obtained
Between sub- test structure resistance；Two test lead S+, S- travel through the second weld pad P2 ..., P+1 weldering
All two neighboring weld pads in pad P (P+1), can correspond to obtain the first sub- test structure A1 resistance R1,
The resistance R2 of the second sub- test structure A2 ..., the resistance R of P-1 test structures A (P-1)
(P-1) the common P-1 resistance of sub- test structure.
In above-mentioned two testing procedure, the first test electric current I1 with second test electric current I2 sizes can with equal,
Can not also wait.
As can be seen that in said process, the resistance R1 of the first sub- test structure A1, the second son test knot
The resistance R2 of structure A2 ..., the resistance RN of the sub- test structure AN of N use the line of Kelvin four
Method of testing (Kelvin Contact) is obtained, thus each resistance for being obtained is more accurate.
In other embodiments, it is also possible to first carry out the step shown in Fig. 6, in the first weld pad P1, Q weldering
Pad PQ two test signals apply end F-, F+ and apply the second test electric current I2, are unidirectionally conducted by first
Structure 11 is turned on, and second unidirectionally conducts structure 12 ends so that Q weld pads PQ is welded through Q-1
Pad P (Q-1) ..., to the first weld pad P1 the second test path be switched on, (N+2) >=Q >=4；
Two test lead S-, S+ travel through the second weld pad P2 ..., it is all adjacent in Q-1 weld pads P (Q-1)
Two weld pads, can correspond to resistance R1, the second sub- test structure A2 for obtaining the first sub- test structure A1
Resistance R2 ..., the common Q-3 son of the resistance R (Q-3) of Q-3 test structures A (Q-3)
The resistance of test structure.
Then the step shown in Fig. 5 is performed, is applied in the first weld pad P1, the test signals of P weld pads PP two
Plus end F+, F- apply first and test electric current I1, unidirectionally conducting structure 12 by second turns on, and first is single
End to structure 11 is conducted so that the first weld pad P1 is welded through N+2 weld pads P (N+2), N+1
Pad P (N+1) ..., to P weld pads PP the first test path be switched on, (Q-1)>P≥2.
P<(Q-1), i.e., P weld pads are on the first test path, except Q weld pads, Q-1 are welded
Any weld pad outside pad.
Two test lead S+, S- traversals N+2 weld pads ..., all two neighboring welderings in Q-1 weld pads
Pad, can correspond to resistance R (Q-2), Q-1 the test for obtaining Q-2 test structures A (Q-2)
The resistance R (Q-1) of structure A (Q-1) ..., the resistance RN of the sub- test structure AN of N is total to
The N+3-Q resistance of sub- test structure.
In other words, some resistance of sub- test structure are obtained and the second test path on the first test path
In the resistance of some sub- test structures obtain without sequencing.
As can be seen that in said structure and method of testing, a son being arranged between any two adjacent welding-pad and being surveyed
Examination structure.It is same using the line method of testing of Calvin four in order to resistance test is accurate, it is adjacent relative to every two
One group of weld pad, therebetween arrange a sub- test structure, such as the second weld pad P2, mono- group of the 3rd weld pad P3, it
Between a sub- test structure is set, the first weld pad P1 is connected with the second weld pad P2, the 3rd weld pad P3 and the 4th
Weld pad P4 is connected, and the second weld pad P2, the 3rd weld pad P3 are used as two test signals and apply end F+, F-, the
One weld pad P1, the 4th weld pad P4 are used as the situation of two test lead S+, S-, if every Cutting Road arrangement 25
Individual weld pad, then the present invention can realize 23 tests of sub- test structure, and the latter can only test 6 sons
Test structure.In other words, for same number of sub- test structure, the solution of the present invention can reduce whole
Region area size shared by individual test structure, reduces the width of the Cutting Road shared by pad, i.e. Cutting Road
Width only accommodate a first weld pad P1, the second weld pad P2, the 3rd weld pad P3 ... or N+2
Weld pad P (N+2), while above-mentioned test structure and method of testing can improve testing efficiency.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (10)
1. a kind of semi-conductor test structure, the test structure is formed in the Cutting Road of wafer, it is characterised in that
The test structure includes：
The first weld pad for being arranged successively along Cutting Road bearing of trend, the second weld pad, the 3rd weld pad ...,
N+2 weld pads, N >=2；
Realize that first of unilateal conduction between first weld pad and the second weld pad unidirectionally conducts structure；
Realize that second of unilateal conduction between first weld pad and N+2 weld pads unidirectionally conducts structure, institute
Stating the second unidirectional structure structure that conducts unidirectional with first that conducts realizes second weld pad to the first weldering
Pad, the first weld pad select a conducting to N+2 weld pads；
The first sub- test structure for being connected between the second weld pad and the 3rd weld pad, it is connected to the 3rd weld pad and
The second sub- test structure between four weld pads ..., be connected between N+1 weld pads and N+2 weld pads
The sub- test structures of N；
Any one and first weld pad are suitable for use as test signal in second weld pad to N+2 weld pads
Apply end, two neighboring in remaining weld pad is suitable for use as between two test leads correspondence obtains two adjacent welding-pads
The resistance of sub- test structure.
2. semi-conductor test structure according to claim 1, it is characterised in that the first unidirectional conductance
Logical structure is the one kind in PN junction, nmos pass transistor or PMOS transistor.
3. semi-conductor test structure according to claim 1 and 2, it is characterised in that described second is unidirectional
It is the one kind in PN junction, nmos pass transistor or PMOS transistor to conduct structure.
4. semi-conductor test structure according to claim 1, it is characterised in that the first son test knot
Structure, the second sub- test structure ..., part is identical in the sub- test structures of N.
5. semi-conductor test structure according to claim 1, it is characterised in that the first son test knot
Structure, the second sub- test structure ..., the sub- test structures of N it is different.
6. the semi-conductor test structure according to claim 1 or 4 or 5, it is characterised in that described partly to lead
Body test structure be used for stress migration test, the first sub- test structure, the second test structure ...,
The sub- test structures of N are the cascaded structure or multilayer conductive of single conductive plunger, single layer of conductive connector
The cascaded structure that the stacked structure of connector is constituted.
7. semi-conductor test structure according to claim 1, it is characterised in that the first weld pad, the second weldering
Pad, the 3rd weld pad ..., N+2 weld pads it is in the same size.
8. semi-conductor test structure according to claim 1, it is characterised in that the width of the Cutting Road
Be only capable of accommodating first weld pad, the second weld pad, the 3rd weld pad ... or N+2 weld pads.
9. the method that the semi-conductor test structure test stress described in a kind of use claim 1 is migrated, described half
Semiconductor devices in conductor test structure and same semi-conductive substrate is in same operation through stress migration
Test processes, it is characterised in that the method for testing includes：
Apply end applying test current lead-through first in first weld pad, the test signal of P weld pads two to weld
Pad through N+2 weld pads, N+1 weld pads ..., to the first test path of P weld pads, N >=P
≥2；Choose N+2 weld pads on first test path ..., the phase in P+1 weld pads
Adjacent two weld pads obtain the resistance of the sub- test structure between two test lead as two test leads, correspondence,
Two test lead traversal N+2 weld pads ..., all two neighboring weld pads in P+1 weld pads, it is right
The common N+1-P resistance of sub- test structure should be obtained；
Apply end in first weld pad, the test signal of Q weld pads two and apply the Q welderings of test current lead-through
Pad through Q-1 weld pads ..., to the second test path of the first weld pad, (N+2) >=Q>(P+1)；
Choose and be located in second test path, the second weld pad ..., it is two neighboring in P+1 weld pads
Weld pad obtains the resistance of the sub- test structure between two test lead, described two as two test leads, correspondence
Test lead travel through the second weld pad ..., all two neighboring weld pads in P+1 weld pads, correspondence obtains altogether
The P-1 resistance of sub- test structure.
10. method of testing according to claim 9, it is characterised in that on first test path altogether
The N+1-P resistance of sub- test structure obtains the common P-1 son test knot with second test path
The resistance of structure is obtained without sequencing.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766957A (en) * | 2018-06-20 | 2018-11-06 | 上海华虹宏力半导体制造有限公司 | Semi-conductor test structure and semiconductor structure |
| CN109904091A (en) * | 2019-02-21 | 2019-06-18 | 长江存储科技有限责任公司 | The test method of wafer test structure, wafer and wafer |
| WO2022156203A1 (en) * | 2021-01-22 | 2022-07-28 | 长鑫存储技术有限公司 | Chip testing method and apparatus, and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105856B1 (en) * | 2005-03-31 | 2006-09-12 | United Microelectronics Corp. | Test key having a chain circuit and a kelvin structure |
| CN101398457A (en) * | 2007-09-25 | 2009-04-01 | 奇景光电股份有限公司 | Wafer, test system thereof, test method thereof, and test fixture thereof |
| CN104465617A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor testing structure |
| CN204720446U (en) * | 2015-06-12 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | Electro-migration testing structure |
-
2015
- 2015-12-11 CN CN201510923178.8A patent/CN106876366B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105856B1 (en) * | 2005-03-31 | 2006-09-12 | United Microelectronics Corp. | Test key having a chain circuit and a kelvin structure |
| CN101398457A (en) * | 2007-09-25 | 2009-04-01 | 奇景光电股份有限公司 | Wafer, test system thereof, test method thereof, and test fixture thereof |
| CN104465617A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor testing structure |
| CN204720446U (en) * | 2015-06-12 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | Electro-migration testing structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766957A (en) * | 2018-06-20 | 2018-11-06 | 上海华虹宏力半导体制造有限公司 | Semi-conductor test structure and semiconductor structure |
| CN109904091A (en) * | 2019-02-21 | 2019-06-18 | 长江存储科技有限责任公司 | The test method of wafer test structure, wafer and wafer |
| CN109904091B (en) * | 2019-02-21 | 2022-07-01 | 长江存储科技有限责任公司 | Wafer test structure, wafer and test method of wafer |
| WO2022156203A1 (en) * | 2021-01-22 | 2022-07-28 | 长鑫存储技术有限公司 | Chip testing method and apparatus, and electronic device |
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