JP2014183136A - Silicon carbide chip, silicon carbide wafer, test method for silicon carbide chip, and test method for silicon carbide wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide chip, a silicon carbide wafer, a test method for a silicon carbide chip, and a test method for a silicon carbide wafer, to which a current conduction test can be applied even when a chip has a large area.SOLUTION: A silicon carbide chip 4 includes a product chip region 1 in which a silicon carbide semiconductor element performing an actual action is crated, and a PN diode 3 which is disposed around the product chip region 1 and which is not involved in an actual action of a smaller area than the product chip region 1.

Description

  The present invention relates to a technique for determining a defect of a silicon carbide chip.

  A wide gap semiconductor material such as silicon carbide has higher dielectric breakdown resistance than silicon, and thus can increase the impurity concentration of the substrate and reduce the resistance of the substrate as compared to silicon material. This reduction in resistance can reduce the loss in the switching operation of the power element. In addition, it has high thermal conductivity and excellent mechanical strength, and is expected to realize a small, low-loss, high-efficiency power device.

  Regarding a PN diode composed of silicon carbide, a reliability problem is known that if a forward current continues to flow, triangular stacking faults occur in the crystal and the forward voltage shifts (for example, Non-patent document 1). This is because triangular stacking faults, which are surface defects, start from basal plane dislocations existing in the silicon carbide substrate due to recombination energy when minority carriers injected into the PN diode recombine with the majority carriers. (For example, refer nonpatent literature 2). Since this triangular stacking fault hinders the flow of current, the flowing current is reduced, the forward voltage is increased, and reliability is deteriorated.

  There is a report that such a forward voltage shift also occurs in a MOSFET (SiC-MOSFET) using silicon carbide (see, for example, Non-Patent Document 3). The MOSFET structure has a parasitic diode (body diode) between the source and the drain, and when a forward current flows through the body diode, the same reliability degradation as that of the PN diode occurs. In general, a Schottky barrier diode having a low forward voltage is used as a freewheeling diode in a switching circuit. However, when a body diode of a SiC-MOSFET is used as a freewheeling diode, it causes a shift in MOSFET characteristics, and a large reliability. It becomes a problem.

  As a test method for this problem, as shown in Patent Document 1, there is a method (hereinafter referred to as a current conduction test) in which a forward current is passed through a PN diode structure for a long time and a forward voltage is measured.

JP 2004-289023 A

Journal of ELECTRONIC MATERIALS, Vol. 39, No. 6, 2010 “Electrical and Optical Properties of Stacking Faults in 4H-SiC Devices” Physical Review Letters vol.92, 175504 (2004) “Driving Force of Stacking-Fault Formation in SiC p-i-n Diodes” IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 7, JULY 2007 "A New Degradation Mechanism in High-Voltage SiC Power MOSFETs"

  However, the above-described current conduction test takes a very long time. In addition, when the device size (chip size) becomes large, the contact pin generates heat when stress is applied at a high current density in order to shorten the stress time. There was a problem that it could not be applied to a large area device.

  In view of the above problems, the present invention provides a silicon carbide chip, a silicon carbide wafer, a test method for the silicon carbide chip, a test method for the silicon carbide wafer, and a test method for the silicon carbide wafer, to which a current conduction test can be applied even if the chip size is a large area. For the purpose of provision.

  The silicon carbide chip of the present invention includes a product chip region in which a silicon carbide semiconductor element that performs actual operation is formed, and a PN diode that is provided around the product chip region and does not participate in actual operation in a smaller area than the product chip region. .

  In addition, the silicon carbide wafer of the present invention has a plurality of product chip regions in which silicon carbide semiconductor elements that perform actual operations are formed, and an actual operation with a smaller area than the product chip regions provided around each product chip region. A PN diode not involved.

  The silicon carbide chip testing method of the present invention includes (a) a step of preparing the silicon carbide chip of the present invention, and (b) applying a forward current to the PN diode region of the silicon carbide chip, A step of measuring the amount of change, and (c) a step of determining the silicon carbide chip as a defective chip when the amount of change in the forward voltage is equal to or greater than a predetermined value.

  Further, the silicon carbide wafer testing method of the present invention includes (a) a step of preparing the silicon carbide wafer of the present invention, (b) applying a forward current to each PN diode of the silicon carbide wafer, And (c) determining a product chip region of the silicon carbide wafer corresponding to the PN diode whose forward voltage change amount is equal to or greater than a predetermined value as a defective chip.

  The silicon carbide chip of the present invention includes a product chip region in which a silicon carbide semiconductor element that performs actual operation is formed, and a PN diode that is provided around the product chip region and does not participate in actual operation in a smaller area than the product chip region. . Therefore, it is possible to expand the triangular stacking fault by flowing a forward current through the PN diode. If the shift amount of the forward voltage at that time is measured, it is possible to detect a defective chip having a large density of triangular stacking faults. Furthermore, since the PN diode has a smaller area than the product chip region, the triangular stacking fault can be expanded with a smaller current, so that the contact pin can be prevented from being broken due to heat generation.

  In addition, the silicon carbide wafer of the present invention has a plurality of product chip regions in which silicon carbide semiconductor elements that perform actual operations are formed, and an actual operation with a smaller area than the product chip regions provided around each product chip region. A PN diode not involved. Therefore, it is possible to expand the triangular stacking fault by flowing a forward current through the PN diode. If the shift amount of the forward voltage at that time is measured, it is possible to detect a defective chip having a large density of triangular stacking faults. Furthermore, since the PN diode has a smaller area than the product chip region, the triangular stacking fault can be expanded with a smaller current, so that the contact pin can be prevented from being broken due to heat generation.

  The silicon carbide chip testing method of the present invention includes (a) a step of preparing the silicon carbide chip of the present invention, and (b) applying a forward current to the PN diode region of the silicon carbide chip, A step of measuring the amount of change, and (c) a step of determining the silicon carbide chip as a defective chip when the amount of change in the forward voltage is equal to or greater than a predetermined value. Since the PN diode region of the silicon carbide chip of the present invention has a smaller area than the product chip region, the forward direction is applied in step (b) by applying a forward current smaller than that for the product chip region. It is possible to cause a change in voltage. Therefore, it is possible to detect a defective chip having a high density of triangular stacking faults without applying a forward current for a long time and without damaging the contact pins due to heat generation.

  Further, the silicon carbide wafer testing method of the present invention includes (a) a step of preparing the silicon carbide wafer of the present invention, (b) applying a forward current to each PN diode of the silicon carbide wafer, And (c) determining a product chip region of the silicon carbide wafer corresponding to the PN diode whose forward voltage change amount is equal to or greater than a predetermined value as a defective chip. Since the PN diode region of the silicon carbide chip of the present invention has a smaller area than the product chip region, the forward direction is applied in step (b) by applying a forward current smaller than that for the product chip region. It is possible to cause a change in voltage. Therefore, it is possible to detect a defective chip having a high density of triangular stacking faults without applying a forward current for a long time and without damaging the contact pins due to heat generation.

It is a lineblock diagram of the silicon carbide chip of the present invention. It is a block diagram of the silicon carbide wafer of this invention. It is sectional drawing of the PN diode of the silicon carbide chip of this invention. It is a figure which shows the triangular stacking fault which generate | occur | produces in a PN diode. It is a figure which shows the relationship between the area of a stacking fault, and the amount of shifts of a forward voltage. It is a flowchart of the testing method of the silicon carbide wafer of a base technology. It is a flowchart of the test method of the silicon carbide wafer of this invention. It is a top view which shows the silicon carbide chip | tip and electrode of this invention. It is a top view which shows the silicon carbide chip | tip and electrode of this invention.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 shows a chip layout of silicon carbide chip 4 of the first embodiment. Silicon carbide chip 4 includes a product chip layout area (product chip area 1) and a PN diode arrangement area 2 in which a plurality of PN diodes 3 are discretely arranged. The product chip area 1 shown in FIG. 1 is square, and the PN diode arrangement area 2 is provided along the right side and the lower side of the layout area 1. The PN diode 3 has a smaller area than the product chip region 1.

  FIG. 2 shows a state where the chip layout of FIG. 1 is created through a wafer process. The PN diode arrangement region 2 is provided along either the right side or the left side of the layout region 1 and either the upper side or the lower side. By forming the PN diode arrangement region 2 along only two sides of the layout region 1, as shown in FIG. 2, when the silicon carbide chip 4 is formed on the silicon carbide wafer 5 without a gap, the product chip region A grid pattern is formed by 1 and the diode arrangement region 2.

  However, the product chip region 1 can take various shapes such as a circle and an arbitrary polygon in addition to the square shown in FIGS. Regardless of the shape of product chip region 1, PN diode placement region 2 is formed to surround PN diode placement region 2 when silicon carbide chips 4 are arranged.

  FIG. 3 is a cross-sectional view of the PN diode 3. The PN diode 3 includes a SiC substrate 11, an N + epitaxial layer 12, a P + diffusion region 14, a high concentration P + diffusion region 15, and an interlayer insulating film 18. N + epitaxial layer 12 is formed on SiC substrate 11, and P + diffusion region 14 is formed in the surface layer of N + epitaxial layer 12. A high concentration P + diffusion region 15 is formed on the P + diffusion region 14 in the surface layer of the N + epitaxial layer 12. On the high concentration P + diffusion region 15, an electrode pad 19 such as aluminum connected to the plurality of PN diodes 3 is formed, and an interlayer insulating film 18 is formed between the electrode pad 19 and the N + epitaxial layer 12. When a forward voltage exceeding the PN junction barrier formed by the N + epitaxial layer 12 and the P + diffusion region 14 is applied between the electrode pad 19 and the SiC substrate 11, a forward current flows. That is, the electrode pad 19 operates as a first electrode pad for applying a forward current to the plurality of PN diodes 3.

  FIG. 4 is a plan view of the PN diode 3 and shows the triangular stacking fault 16 that expands due to forward current stress. When a forward current is passed through the SiC substrate 11, triangular stacking faults are expanded starting from basal plane dislocations.

  FIG. 5 shows the ratio (%) of the shift amount from the initial value at which the forward current starts to flow to the value after the lapse of a fixed period from the initial value at which the forward current starts flowing for the forward voltage Vf of the PN diode 3. It is the graph shown by the relationship with the area of a stacking fault. The horizontal axis indicates the area ratio (%) of stacking faults with respect to the P + diffusion region 14, and the vertical axis indicates the shift amount (%) of the forward voltage Vf.

  The area of the triangular stacking fault is determined by the thickness Te of the N + epitaxial layer 12 and the OFF angle θ of the wafer. That is, the width Wsf of the triangular stacking fault in the step flow direction is

The height Hsf of the triangular stacking fault in the direction perpendicular to the step flow direction is

Determined by. Therefore, for example, when a 10 μm epitaxial film is formed on a 4H—SiC substrate off by 4 ° in the <11-20> direction from the (0001) plane, the area of the triangular stacking fault is about 0.018 mm ² . In order to monitor the stacking fault extension, it is desirable that the shift amount of Vf is 2% or more. Therefore, from FIG. 5, the area of the stacking fault to be assumed is 10% or more of the effective area of the PN diode 3. Is desirable. Therefore, the area of the PN diode 3 is desirably 0.18 mm ² or less, which is 10 times the area of the triangular stacking fault to be detected. If the area of the PN diode is too large with respect to the stacking fault, the shift amount of the forward voltage Vf after flowing the forward current becomes small, and the detection sensitivity of the stacking fault is lowered.

<A-2. Operation>
A silicon carbide chip testing method according to the premise technique of the present invention will be described along the flowchart of FIG. First, a semiconductor device (silicon carbide wafer) is manufactured by a semiconductor process (step S1), and then a current test is performed through a wafer test process (step S2), a dicing process (step S3), and a chip test process (step S4). (Step S5). In the current-carrying test, a forward current is passed through the product chip to expand the stacking fault, and the fluctuation of the forward voltage Vf due to this is measured. Product chips whose forward voltage Vf variation is less than the threshold are selected as non-defective chips (step S6).

  By the way, when the product chip has a large area, the forward current stress increases as the chip area increases, and the stress time is prolonged due to the limitation of the forward current stress due to heat generation. In addition, since the probe and the product chip itself are damaged by heat generation, it is difficult to evaluate the characteristic variation by applying a forward current stress having a large current density in a short time to expand the stacking fault.

  FIG. 7 shows a flowchart of the test method of the present invention that solves this problem. Hereinafter, the test method for the silicon carbide wafer (or silicon carbide chip) of the present invention will be described with reference to FIG. First, a semiconductor device (silicon carbide wafer 5) is created by a semiconductor process (step S11). Next, a predetermined wafer test is performed (step S12). Thereafter, a current conduction test is performed before dicing silicon carbide wafer 5. Here, a forward current is applied to all the PN diodes 3 on the wafer surface in a batch or in units of groups (step S13), and the shift amount of the forward voltage Vf in a predetermined time from the beginning of the forward current application is measured. To do.

  At this time, for example, the forward current is applied from the electrode pad 19 using the configuration of a modified example (FIG. 8) to be described later, and the shift amount of the forward voltage Vf of each PN diode 3 is measured. 3 is performed by the measurement pad 20 (second electrode pad) connected to the third electrode.

  Then, among the PN diodes 3 on the wafer surface, the PN diode 3 whose forward voltage Vf shift amount is equal to or larger than the threshold value is detected as a region where the extended stacking fault density is large (step S14).

  Then, product chips included in the detected area are selected as excluded chips (step S15). Thereafter, dicing is performed (step S16), and a chip test is performed (step S17). Finally, chips other than the chips selected as excluded chips in step S15 are selected as non-defective chips (step S18).

As described above, in the test method of the present invention, a high current density stress is applied to the PN diode 3 that is smaller in area than the product chip (product chip region 1) and can apply a high current density current stress. It is possible to extend the stacking faults in a short time and determine the product chip. The temperature and stress conditions necessary to expand the stacking fault are preferably higher than the rated current, particularly 300 A / cm ² or higher, and are performed under high temperature conditions of 180 ° C. to 350 ° C. Under this accelerated condition, the stacking fault expands in a stress application time of 1 minute or less.

<A-3. Modification>
In order to improve the measurement accuracy of the extended stacking fault density, it is necessary to mount a large number of PN diodes 3 on the silicon carbide semiconductor wafer 4. However, when current is sequentially applied to the PN diode 3, the time required for the test becomes longer. Therefore, the time required for the current conduction test can be shortened by applying current from the electrode pad 19 to the plurality of PN diodes 3 arranged in parallel (FIG. 8). The shift amount of the forward voltage Vf after applying the forward current stress is evaluated by each PN diode 3 using the measurement pad 20.

  Thus, the stress application time can be shortened by applying the stress forward current to the plurality of diodes at once.

  In the above description, the current conduction test is performed after the silicon carbide semiconductor wafer is formed and before dicing. However, the current conduction test may be performed in a state where the silicon carbide semiconductor chip is formed after dicing.

  Further, as shown in FIG. 9, each silicon carbide semiconductor chip 4 may be surrounded by a temperature control wiring 22 made of polysilicon or the like. The temperature control wiring 22 is connected to a metal pad 21 such as aluminum by a contact 23. By applying a voltage to the metal pad 21, the temperature control wiring 22 is energized to generate heat. Thus, the uniformity of temperature is improved by drawing the wiring body around with good control without applying long-term temperature stress to the product device.

<A-4. Effect>
Silicon carbide chip 4 (silicon carbide wafer 5) according to the first embodiment includes product chip region 1 in which a silicon carbide semiconductor element that performs actual operation is formed, and product chip region 1 provided around product chip region 1 Is provided with a PN diode 3 that does not participate in actual operation in a small area. Therefore, the triangular stacking fault 16 can be expanded by flowing a forward current through the PN diode 3. By measuring the shift amount of the forward voltage at that time, it is possible to detect a defective chip having a high density of triangular stacking faults 16. Further, since the PN diode 3 has a smaller area than the product chip region 1, the triangular stacking fault 16 can be expanded with a smaller current, and therefore, destruction of the contact pin due to heat generation can be suppressed.

  In addition, the area of the PN diode 3 is 10 times or less than the area of one triangular stacking fault 16 generated in the PN diode 3. As a result, the shift amount of the forward voltage Vf accompanying the expansion of the triangular stacking defect 16 is 2% or more, and therefore it can be detected with high accuracy.

  Further, the silicon carbide chip 4 is provided around the PN diode 3 and includes a temperature control wiring 22 that generates heat when energized, and the temperature control of the silicon carbide chip 4 can be easily performed. The time required for the energization test can be shortened.

  In addition, silicon carbide wafer 5 of the first embodiment is provided on electrode pad 19 (first electrode pad) for applying a forward current to a plurality of PN diodes 3 and each PN diode 3, And a measurement pad 20 (second electrode pad) for measuring a forward voltage shift amount of the PN diode 3. Therefore, by applying a forward current from the electrode pad 19 to each PN diode 3 and measuring the shift amount of the forward voltage with the measurement pad 20 at that time, the density of the triangular stacking faults 16 in each PN diode 3 can be measured. Therefore, it is possible to determine whether the silicon carbide chip 4 is good or bad.

  Moreover, since the electrode pad 19 is connected to the plurality of PN diodes 3 at once, a forward current can be applied to the plurality of PN diodes 3 at a time, and the energization test time can be shortened.

  The test method for silicon carbide chip 4 of the first embodiment includes (a) a step of preparing silicon carbide chip 4 of the first embodiment, and (b) applying a forward current to PN diode region 3 of silicon carbide chip 4. And measuring the amount of change in the forward voltage Vf, and (c) determining that the silicon carbide chip 4 is a defective chip when the amount of change in the forward voltage Vf is greater than or equal to a predetermined value. Since the PN diode region 3 has a smaller area than the product chip region 1, the triangular stacking fault 16 can be expanded with a smaller current than when a direct current test is performed on the product chip region 1. Contact pin breakage can be suppressed.

  The test method of silicon carbide wafer 5 of the first embodiment includes (a) a step of preparing silicon carbide wafer 5 of the first embodiment, and (b) applying a forward current to each PN diode 3 of silicon carbide wafer 5. A step of measuring the change amount of the forward voltage Vf, and (c) the product chip region 1 of the silicon carbide wafer 5 corresponding to the PN diode 3 whose change amount of the forward voltage Vf is a predetermined value or more is defined as a defective chip. Determining. Since the PN diode region 3 has a smaller area than the product chip region 1, the triangular stacking fault 16 can be expanded with a smaller current than when a direct current test is performed on the product chip region 1. Contact pin breakage can be suppressed.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention.

  1 Product chip region, 2 PN diode placement region, 3 PN diode, 4 Silicon carbide chip, 5 Silicon carbide wafer, 11 SiC substrate, 12 Epitaxial layer, 14 P + diffusion region, 15 High concentration P + diffusion region, 16 Triangular stacking fault, 18 Interlayer insulation film, 19 Electrode pad, 20 Measurement pad, 21 Metal pad, 22 Temperature control wiring, 23 Contact.

Claims (10)

A product chip region in which a silicon carbide semiconductor element performing actual operation is formed;
A PN diode that is provided around the product chip region and has a smaller area than the product chip region and does not participate in the actual operation.
Silicon carbide chip. The area of the PN diode is not more than 10 times the area of one triangular stacking fault occurring in the PN diode.
The silicon carbide chip according to claim 1. A temperature control wiring provided around the PN diode and generating heat when energized;
The silicon carbide chip according to claim 1 or 2. A plurality of product chip regions in which silicon carbide semiconductor elements that perform actual operation are formed;
A PN diode that is provided around each of the product chip regions and has a smaller area than the product chip region and does not participate in the actual operation.
Silicon carbide wafer. The area of the PN diode is not more than 10 times the area of one triangular stacking fault occurring in the PN diode.
The silicon carbide wafer according to claim 4. A first electrode pad for applying a forward current to the plurality of PN diodes;
A second electrode pad provided in each of the PN diodes for measuring a shift amount of a forward voltage of the PN diode when the current is applied.
The silicon carbide wafer according to claim 4 or 5. The first electrode pad is collectively connected to a plurality of the PN diodes.
The silicon carbide wafer according to claim 6. A temperature control wiring provided around each of the PN diodes and generating heat when energized;
The silicon carbide wafer in any one of Claims 4-7. (A) preparing the silicon carbide chip according to any one of claims 1 to 3;
(B) applying a forward current to the PN diode region of the silicon carbide chip and measuring a forward voltage change amount;
(C) A step of determining the silicon carbide chip as a defective chip when the amount of change in the forward voltage is equal to or greater than a predetermined value. (A) preparing the silicon carbide wafer according to any one of claims 4 to 8;
(B) applying a forward current to each of the PN diodes of the silicon carbide wafer and measuring the amount of change in the forward voltage;
(C) determining the product chip region of the silicon carbide wafer corresponding to the PN diode whose amount of change in the forward voltage is a predetermined value or more as a defective chip,
Test method for silicon carbide wafer.

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