CN106876366B - Semi-conductor test structure and stress migration test method - Google Patents
Semi-conductor test structure and stress migration test method Download PDFInfo
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Abstract
A kind of semi-conductor test structure and stress migration test method, in wafer Cutting Road along Cutting Road extending direction be sequentially arranged the first weld pad, the second weld pad ..., N+2 weld pad, except the first weld pad, the second weld pad, son needed for all arranging a stress migration test between remaining any two adjacent welding-pad tests structure；When test, between first weld pad and the second weld pad, the first weld pad between N+2 weld pad it is respectively arranged unidirectionally conduct structure alternatively and make a) the first weld pad to through N+2 weld pad ..., be connected to the first test path of P weld pad, Kelvin's four-wire method obtains the total N+1-P sub resistance for testing structure in the path；Or b) the first weld pad through the second weld pad ..., be connected to the second test path of Q weld pad, Q > (P+1), Kelvin's four-wire method obtains the resistance that remaining P-1 son tests structure.Above configuration reduce area sizes shared by test structure, improve testing efficiency.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semi-conductor test structure and stress migration test sides
Method.
Background technique
In ic manufacturing process, the stress migration (Stress- of metal interconnecting layer, especially conductive plunger
Migration, SM) phenomenon causes the open circuit and short circuit of metal interconnection structure, and increase device creepage.As integrated circuit is advised
Mould constantly expands, and device size constantly reduces, and the line width of metal interconnecting wires constantly reduces, and current density constantly rises, it is easier to
Stress is migrated and is failed, and has become an important integrity problem.
Stress migration is at a certain temperature, since a variety of materials thermal expansion coefficient is different, so in different storerooms
Stress is formed, so that the place aggregation that intercrystalline small gap is concentrated to stress in metal interconnecting wires or through-hole be made to form cavity
Physical phenomenon.The cavity that stress migration is formed reaches just makes the metal interconnecting wires in integrated circuit that open circuit occur to a certain degree,
To cause the failure of device.
In the prior art, it in order to improve device density, is generally interconnected using multiple layer metal, the stress of every layer of metal interconnecting wires
Migration all needs to test, this causes test process time-consuming.In addition, it is larger to also result in region shared by test structure, however, to improve
The effective use region of wafer, generally by test structure setting in narrow Cutting Road, this has been further exacerbated by above-mentioned contradiction.
In view of this, the present invention provides a kind of semi-conductor test structure, and answered using above-mentioned semi-conductor test structure
The test method of power migration, to improve testing efficiency, reduction accounts for area size.
Summary of the invention
Problems solved by the invention be region shared by the existing test structure to metal interconnection structure stress migration test it is big,
Test is time-consuming.
To solve the above problems, an aspect of of the present present invention provides a kind of semi-conductor test structure, the test structure is formed
In the Cutting Road of wafer, the test structure includes:
The first weld pad for successively arranging along Cutting Road extending direction, the second weld pad, third weld pad ..., N+2 weld pad, N
≥2；
Realize that first of unilateal conduction between first weld pad and the second weld pad unidirectionally conducts structure；
Realize that unidirectionally conduct between first weld pad and N+2 weld pad second unidirectionally conducts structure, described second
Unilateal conduction structure unidirectionally conducts structure with first and realizes that second weld pad is welded to the first weld pad, the first weld pad to N+2
Pad selects a conducting；
The first son test structure for being connected between the second weld pad and third weld pad, be connected to third weld pad and the 4th weld pad it
Between the second son test structure ..., N that is connected between N+1 weld pad and N+2 weld pad test structure；
Second weld pad any one and first weld pad into N+2 weld pad are suitable as test signal and apply end,
The two neighboring resistance for being suitable as the corresponding son test structure obtained between two adjacent welding-pads of two test leads in remaining weld pad.
Optionally, described first structure is conducted unidirectionally as one of PN junction, NMOS transistor or PMOS transistor.
Optionally, described second structure is conducted unidirectionally as one of PN junction, NMOS transistor or PMOS transistor.
Optionally, the first son test structure, the second son test structure ..., part phase in N test structure
Together.
Optionally, it is described first son test structure, second son test structure ..., N test structure it is different.
Optionally, the semi-conductor test structure is used for stress migration test, the first son test structure, the second test
Structure ..., N test structure be single conductive plunger, the cascaded structure of single layer of conductive plug or multilayer conductive plug
The cascaded structure that stacked structure is constituted.
Optionally, the first weld pad, the second weld pad, third weld pad ..., N+2 weld pad it is in the same size.
Optionally, the width of the Cutting Road be only capable of accommodate first weld pad, the second weld pad, third weld pad ... or
N+2 weld pad.
A kind of method of above-mentioned semi-conductor test structure test stress migration, the semi-conductor test structure are led with same half
Semiconductor devices in body substrate is handled through stress migration test in the same process, and the test method includes:
Signal, which is tested, in first weld pad, P weld pad two applies end application test the first weld pad of current lead-through through N+2
Weld pad, N+1 weld pad ..., to the first test path of P weld pad, N >=P >=2；It chooses and is located at first test path
On N+2 weld pad ..., the two neighboring weld pad in P+1 weld pad as two test leads, it is corresponding to obtain two test lead
Between son test structure resistance, two test lead traversal N+2 weld pad ..., all two neighboring welderings in P+1 weld pad
Pad, the corresponding resistance for obtaining total N+1-P son test structure；
Signal, which is tested, in first weld pad, Q weld pad two applies end application test current lead-through Q weld pad through Q-1
Weld pad ..., to the second test path of the first weld pad, (N+2) >=Q > (P+1)；It chooses and is located in second test path,
Second weld pad ..., the two neighboring weld pad in P+1 weld pad as two test leads, it is corresponding to obtain between two test lead
The resistance of son test structure, two test lead traverse the second weld pad ..., all two neighboring weld pads in P+1 weld pad, it is right
The resistance of total P-1 son test structure should be obtained.
Optionally, the resistance of total N+1-P son test structure obtains and second test on first test path
The resistance of total P-1 son test structure is obtained without sequencing in path.
Compared with prior art, technical solution of the present invention has the advantage that 1) present invention is first in wafer Cutting Road
It is interior along Cutting Road extending direction be sequentially arranged the first weld pad, the second weld pad, third weld pad ..., multiple welderings such as N+2 weld pad
Pad all arranges a stress migration institute between remaining any two adjacent welding-pad except the first weld pad, the second weld pad the two adjacent welding-pads
The son test structure that need to be tested arranges that a son test structure, the present invention improve weldering relative to one group of every two adjacent welding-pad therebetween
Utilization rate is padded, area size shared by test structure is reduced；When test, by between the first weld pad and the second weld pad, first weldering
Pad N+2 weld pad between it is respectively arranged unidirectionally conduct structure alternatively and make a) the first weld pad to through N+2 weld pad, N+1
Weld pad ..., to P weld pad the first test path be connected, obtained by 4-Wire Kelvin Test method (Kelvin Contact)
Take the resistance of total N+1-P son test structure in the path；Or b) Q weld pad through Q-1 weld pad ..., to the first weld pad
The conducting of second test path, Q > (P+1) obtain the resistance of remaining P-1 son test structure by 4-Wire Kelvin Test method.
2) in optinal plan, between the first weld pad and the second weld pad, respectively arranged unidirectional between the first weld pad and N+2 weld pad
Conducting structure can be PN junction, NMOS transistor or one of PMOS transistor or phase inverter, unidirectionally to conduct structure
Provide plurality of optional scheme.
3) in optinal plan, first son test structure, second son test structure ..., N test structure can part
It is identical, it can also be different；Specifically, for stress migration test, the first son test structure, the second test structure ...,
N tests the stacking knot that structure can be single conductive plunger, the cascaded structure of single layer of conductive plug or multilayer conductive plug
The cascaded structure that structure is constituted.
4) in optinal plan, the first weld pad, the second weld pad, third weld pad ..., N+2 weld pad it is in the same size, be conducive to
Simplify mask blank structure, and the compatibility of semi-conductor test structure can be improved.
5) in optinal plan, the width of Cutting Road be only capable of accommodate first weld pad, the second weld pad, third weld pad ...,
Or N+2 weld pad, utilization efficiency of the present invention due to improving weld pad can reduce same number of sub- test structure
Area size shared by structure is tested, thus the width of Cutting Road can reduce, and improve the area of device region.
Detailed description of the invention
Fig. 1 is the schematic diagram of the semi-conductor test structure of one embodiment of the invention；
Fig. 2 to Fig. 4 be in Fig. 1 first son test structure, second son test structure ..., to N test structure in
The cross section structure schematic diagram of any three sons test structure；
Fig. 5 and Fig. 6 is schematic diagram of semi-conductor test structure during stress migration test in Fig. 1 respectively.
Specific embodiment
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 is the schematic diagram of the semi-conductor test structure of one embodiment of the invention.Fig. 2 to Fig. 4 is that the first son in Fig. 1 is surveyed
Try structure, second son test structure ..., to N test structure in it is any three son test structures cross section structures signal
Figure.
Below in conjunction with the semi-conductor test structure for shown in Fig. 1 to Fig. 4, introducing one embodiment of the invention offer.
Shown in referring to Fig.1, which is formed in the Cutting Road (not shown) of wafer, comprising:
The first weld pad P1 for successively arranging along Cutting Road extending direction, the second weld pad P2, third weld pad P3 ..., N+2
Weld pad P (N+2), N >=2；
Realize that first of unilateal conduction between the first weld pad P1 and the second weld pad P2 unidirectionally conducts structure 11；
Realize that unidirectionally conduct between the first weld pad P1 and N+2 weld pad P (N+2) second unidirectionally conducts structure 12,
Two unilateal conduction structures 12 and first unidirectionally conduct structure 11 realize the second weld pad P2 to the first weld pad P1, the first weld pad P1 to
N+2 weld pad P (N+2) alternatively conducting；
The first son test structure A1 for being connected between the second weld pad P2 and third weld pad P3, it is connected to third weld pad P3 and the
The second son test structure A2 between four weld pad P4 ..., be connected to N+1 weld pad P (N+1) and N+2 weld pad P (N+2) it
Between N test structure AN；
Second weld pad P2 any one and the first weld pad P1 into N+2 weld pad P (N+2) are suitable as two tests
Signal applies end and applies test signal F+, F-, and two neighboring two test leads that are suitable as in remaining weld pad correspond to acquisition two-phase
The resistance of son test structure between adjacent weld pad.
In the present embodiment, first, which unidirectionally conducts structure 11 and second, unidirectionally conducts the respectively two reversed PN of structure 12
Knot.In other embodiments, a) the first unidirectional structure 11 that conducts can be NMOS transistor, and second, which unidirectionally conducts structure 12, is
PMOS transistor or b) first unidirectionally conduct structure 11, second unidirectionally conduct structure 12 be respectively PMOS transistor with
NMOS transistor, when grid high voltage, first, which unidirectionally conducts structure 11, second, unidirectionally conducts 12 alternatively of structure and leads
It is logical.
It in the specific implementation process, is the lay photoetching mask plate figure of each weld pad of simplification and the compatibility of raising test structure,
First weld pad P1, the second weld pad P2, third weld pad P3 ..., N+2 weld pad P (N+2) it is in the same size.
In a kind of test method, semi-conductor test structure shown in FIG. 1 is used to test the stress migration of semiconductor structure.It is right
Ying Di, the first son test structure A1, the second test structure A2 ..., part is identical in N test structure AN, part
It is different.Specifically, which can be a) single conductive plunger V1 shown in Fig. 2, wherein upper layer and lower layer metal layer
Pattern M1, M2 are connected respectively with two adjacent weld pads or the b) series connection of single layer of conductive plug V1, V2, V3, V4 shown in Fig. 3
Structure is connected respectively or c) shown in Fig. 4 with two adjacent weld pads positioned at two metal layer pattern Ma, Mb of cascaded structure head and the tail
Multilayer conductive plug V1, V2, V3 stacked structure constitute cascaded structure, two metal layer patterns at the top of stacked structure
Ma, Mb are connected with two adjacent weld pads respectively.
It should be noted that in Fig. 2, only to illustrate the conductive plunger between the first metal layer M1 and second metal layer M2
Be illustrated for V1, the first son test structure A1, the second test structure A2 ..., N test structure AN may be the
Conductive plunger between two metal layer M2 and third metal layer M3, the conduction between third metal layer M3 and the 4th metal layer M4 are inserted
Plug ....In Fig. 3, only it is with conductive plunger V1, V2, V3, V4 for illustrating between the first metal layer M1 and second metal layer M2
Example be illustrated, first son test structure A1, second test structure A2 ..., N test structure AN may be the second gold medal
Belong to the cascaded structure that several conductive plungers between layer M2 and third metal layer M3 are constituted, third metal layer M3 and the 4th metal layer
The cascaded structure ... that several conductive plungers between M4 are constituted.In Fig. 4, the only the first metal layer M1 and the 4th gold medal to illustrate
It is illustrated for the cascaded structure that the stacked structure of conductive plunger V1, V2, V3 are constituted between category layer M4, the first son test structure
A1, second test structure A2 ..., N test structure AN may be between the first metal layer M1 and third metal layer M3
Several conductive plungers stacked structure at cascaded structure, several conductions between second metal layer M2 and the 4th metal layer M4
The cascaded structure ... that the stacked structure of plug is constituted.
Based on above-mentioned semi-conductor test structure, the semi-conductor test structure and with the semiconductor device in semi-conductive substrate
Part is handled through stress migration test in the same process, such as the same high temperature of heating, the present invention provide a kind of test stress
The test method of migration, comprising:
Firstly, referring to Figure 5, testing signal in the first weld pad P1, P weld pad PP two by probe and applying end F+, F-
Apply the first test electric current I1, second unidirectionally conducts the conducting of structure 12, and first unidirectionally conducts the cut-off of structure 11, at this point, the
One weld pad P1 through N+2 weld pad P (N+2), N+1 weld pad P (N+1) ..., led to the first test path of P weld pad PP
It is logical, N >=P >=2.
Since each pad is smaller, size is substantially suitable with the stitch of probe, if thus each pad be chosen as test letter
After number applying end, it cannot be chosen as another test signal application end or test lead again.
Choose the N+2 weld pad P (N+2) being located on the first test path ..., it is adjacent in P+1 weld pad P (P+1)
Two weld pads pass through the corresponding voltage V1 obtained between two test lead S+, S- of two probes, test voltage as two test lead S+, S-
The test electric current I1 that V1/ is applied can obtain the resistance of the son test structure between two test lead S+, S-；The two test leads S
+, S- traversal N+2 weld pad P (N+2) ..., all two neighboring weld pads in P+1P (P+1) weld pad, can correspond to and obtain P
The resistance R (P+1) of resistance RP, P+1 the test structure A (P+1) of son test structure AP ..., N test structure AN
The resistance of the total N+1-P son test structure of resistance RN.
It is understood that in the above process, the electricity of the resistance R1 of the first son test structure A1, the second son test structure A2
Resistance R2 ..., resistance R (P-1) the total P-1 sub resistance for testing structure of P-1 test structure A (P-1) has not been obtained.
Then, referring to shown in Fig. 6, apply end F-, F+ in the first weld pad P1, Q weld pad PQ two test signal and apply second
Electric current I2 is tested, first unidirectionally conducts the conducting of structure 11, and second unidirectionally conducts the cut-off of structure 12, at this point, Q weld pad PQ is passed through
Q-1 weld pad P (Q-1) ..., to the first weld pad P1 the second test path be switched on, (N+2) >=Q > (P+1).
Q > (P+1), i.e. Q weld pad PQ are on the first test path, in addition to P weld pad PP, P+1 weld pad P (P+1)
Any weld pad.
Choose and be located in the second test path, the second weld pad P2 ..., the two neighboring weldering in P+1 weld pad P (P+1)
Pad is used as two test lead S+, S-, is applied by the corresponding voltage V2 obtained between two test lead S+, S- of two probes, test voltage V2/
The test electric current I2 added can obtain the resistance of the son test structure between two test lead S+, S-；Two test lead S+, S- traversal the
Two weld pad P2 ..., all two neighboring weld pads in P+1 weld pad P (P+1), can correspond to and obtain the first son test structure A1's
Resistance R1, the second son test structure A2 resistance R2 ..., resistance R (P-1) total P-1 of P-1 test structure A (P-1) it is a
The resistance of son test structure.
In above-mentioned two testing procedure, the first test electric current I1 can be equal with the second test electric current I2 size, can also not
Deng.
As can be seen that in the above process, the resistance of the resistance R1 of the first son test structure A1, the second son test structure A2
R2 ..., N test structure AN resistance RN be all made of 4-Wire Kelvin Test method (Kelvin Contact) acquisition, because
And each resistance obtained is more accurate.
In other embodiments, step shown in fig. 6 can also be first carried out, tests and believes in the first weld pad P1, Q weld pad PQ two
Number applying end F-, F+ applies the second test electric current I2, unidirectionally conducts structure 11 by first and is connected, second unidirectionally conducts knot
Structure 12 ends so that Q weld pad PQ through Q-1 weld pad P (Q-1) ..., led to the second test path of the first weld pad P1
It is logical, (N+2) >=Q >=4；Two test lead S-, S+ traverse the second weld pad P2 ..., it is all two neighboring in Q-1 weld pad P (Q-1)
Weld pad, can correspond to obtain first son test structure A1 resistance R1, second son test structure A2 resistance R2 ..., Q-3
Test the resistance of the total Q-3 son test structure of resistance R (Q-3) of structure A (Q-3).
Then step shown in fig. 5 is executed, applies end F+, F- in the first weld pad P1, P weld pad PP two test signal and applies
First test electric current I1 unidirectionally conducts structure 12 by second and is connected, and first unidirectionally conducts the cut-off of structure 11, so that first
Weld pad P1 through N+2 weld pad P (N+2), N+1 weld pad P (N+1) ..., to P weld pad PP the first test path be switched on,
(Q-1)>P≥2。
P < (Q-1), i.e. P weld pad are on the first test path, any weldering in addition to Q weld pad, Q-1 weld pad
Pad.
Two test lead S+, S- traverse N+2 weld pad ..., all two neighboring weld pads in Q-1 weld pad, can correspond to and obtain
Take resistance R (Q-2), Q-1 the test structure A (Q-1) of Q-2 test structure A (Q-2) resistance R (Q-1) ..., the
N tests the resistance of the total N+3-Q son test structure of resistance RN of structure AN.
In other words, the resistance of several height test structures obtains and several in the second test path on the first test path
The resistance of son test structure is obtained without sequencing.
As can be seen that arranging a son test structure between any two adjacent welding-pad in above structure and test method.For
Resistance test is accurate, equally uses Calvin four line method of testing, relative to one group of every two adjacent welding-pad, arranges that a son is surveyed therebetween
Try structure, such as the second weld pad P2, mono- group of third weld pad P3, between one son test structure of setting, the first weld pad P1 welds with second
It pads P2 to be connected, third weld pad P3 is connected with the 4th weld pad P4, and the second weld pad P2, third weld pad P3 are used as two test signals and apply end
The case where F+, F-, the first weld pad P1, the 4th weld pad P4 are used as two test lead S+, S-, if every Cutting Road arranges 25 weld pads,
Then the test of 23 son test structures may be implemented in the present invention, and the latter can only test 6 son test structures.In other words, for
Same number of sub- test structure, the solution of the present invention can reduce region area size shared by entire test structure, reduce weldering
The width of Cutting Road shared by disk, the i.e. width of Cutting Road only accommodate a first weld pad P1, the second weld pad P2, third weld pad
P3 ... or N+2 weld pad P (N+2), while above-mentioned test structure and test method can improve testing efficiency.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of semi-conductor test structure, the test structure is formed in the Cutting Road of wafer, which is characterized in that the test
Structure includes:
The first weld pad for successively arranging along Cutting Road extending direction, the second weld pad, third weld pad ..., N+2 weld pad, N >=2；
Realize that first of unilateal conduction between first weld pad and the second weld pad unidirectionally conducts structure；
Realize that second of unilateal conduction between first weld pad and N+2 weld pad unidirectionally conducts structure, the described second unidirectional electricity
Conducting structure unidirectionally conducts structure with first and realizes that second weld pad is selected to the first weld pad, the first weld pad to N+2 weld pad
One conducting；
The first son being connected between the second weld pad and third weld pad is tested structure, is connected between third weld pad and the 4th weld pad
Second son test structure ..., N that is connected between N+1 weld pad and N+2 weld pad test structure；
Second weld pad any one and first weld pad into N+2 weld pad are suitable as test signal and apply end, remaining weldering
The two neighboring resistance for being suitable as the corresponding son test structure obtained between two adjacent welding-pads of two test leads in pad；
Wherein, the width of the Cutting Road be only capable of accommodating first weld pad, the second weld pad, third weld pad ... or N+2
Weld pad.
2. semi-conductor test structure according to claim 1, which is characterized in that described first conducts structure unidirectionally as PN
One of knot, NMOS transistor or PMOS transistor.
3. semi-conductor test structure according to claim 1 or 2, which is characterized in that described second unidirectionally conducts structure
For one of PN junction, NMOS transistor or PMOS transistor.
4. semi-conductor test structure according to claim 1, which is characterized in that the first son test structure, the second son
Test structure ..., part is identical in N test structure.
5. semi-conductor test structure according to claim 1, which is characterized in that the first son test structure, the second son
Test structure ..., N test structure it is different.
6. semi-conductor test structure according to claim 1 or 4 or 5, which is characterized in that the semi-conductor test structure is used
In stress migration test, the first son test structure, the second test structure ..., N test structure be single conductive insert
The cascaded structure that the stacked structure of plug, the cascaded structure of single layer of conductive plug or multilayer conductive plug is constituted.
7. semi-conductor test structure according to claim 1, which is characterized in that the first weld pad, the second weld pad, third weldering
Pad ..., N+2 weld pad it is in the same size.
8. a kind of method of test stress migration, using semi-conductor test structure described in claim 1, the semiconductor test
Structure is handled through stress migration test in the same process with the semiconductor devices in same semi-conductive substrate, which is characterized in that
The test method includes:
Signal, which is tested, in first weld pad, P weld pad two applies end application test the first weld pad of current lead-through through N+2 weldering
Pad, N+1 weld pad ..., to the first test path of P weld pad, N >=P >=2；It chooses and is located on first test path
N+2 weld pad ..., the two neighboring weld pad in P+1 weld pad as two test leads, it is corresponding to obtain between two test lead
Son test structure resistance, two test lead traversal N+2 weld pad ..., all two neighboring welderings in P+1 weld pad
Pad, the corresponding resistance for obtaining total N+1-P son test structure；
Signal, which is tested, in first weld pad, Q weld pad two applies end application test current lead-through Q weld pad through Q-1 weldering
Pad ..., to the second test path of the first weld pad, (N+2) >=Q > (P+1)；It chooses and is located in second test path, the
Two weld pads ..., the two neighboring weld pad in P+1 weld pad is as two test leads, the corresponding son obtained between two test lead
Test the resistance of structure, two test lead traverse the second weld pad ..., all two neighboring weld pads in P+1 weld pad, it is corresponding
Obtain the resistance of total P-1 son test structure.
9. the method for test stress migration according to claim 8, which is characterized in that total N+ on first test path
The resistance of 1-P son test structure, which is obtained, to be obtained with the resistance of P-1 son test structure total in second test path without elder generation
Sequence afterwards.
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| CN108766957A (en) * | 2018-06-20 | 2018-11-06 | 上海华虹宏力半导体制造有限公司 | Semi-conductor test structure and semiconductor structure |
| CN109904091B (en) * | 2019-02-21 | 2022-07-01 | 长江存储科技有限责任公司 | Wafer test structure, wafer and test method of wafer |
| CN112904179B (en) * | 2021-01-22 | 2022-04-26 | 长鑫存储技术有限公司 | Chip testing method and device and electronic equipment |
| US12044724B2 (en) | 2021-01-22 | 2024-07-23 | Changxin Memory Technologies, Inc. | Chip testing method and apparatus, and electronic equipment |
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| CN104465617A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor testing structure |
| CN204720446U (en) * | 2015-06-12 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | Electro-migration testing structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105856B1 (en) * | 2005-03-31 | 2006-09-12 | United Microelectronics Corp. | Test key having a chain circuit and a kelvin structure |
| CN101398457A (en) * | 2007-09-25 | 2009-04-01 | 奇景光电股份有限公司 | Wafer, test system thereof, test method thereof, and test fixture thereof |
| CN104465617A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor testing structure |
| CN204720446U (en) * | 2015-06-12 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | Electro-migration testing structure |
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