CN114325288A - Method for evaluating power cycle capability of semiconductor module and semiconductor module - Google Patents
Method for evaluating power cycle capability of semiconductor module and semiconductor module Download PDFInfo
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- CN114325288A CN114325288A CN202210011740.XA CN202210011740A CN114325288A CN 114325288 A CN114325288 A CN 114325288A CN 202210011740 A CN202210011740 A CN 202210011740A CN 114325288 A CN114325288 A CN 114325288A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012360 testing method Methods 0.000 claims abstract description 72
- 238000003466 welding Methods 0.000 claims abstract description 38
- 230000008859 change Effects 0.000 claims abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- 230000001351 cycling effect Effects 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 238000006731 degradation reaction Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 30
- 229910010271 silicon carbide Inorganic materials 0.000 description 28
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000005022 packaging material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The application relates to a method for evaluating power cycle capability of a semiconductor module and the semiconductor module, wherein the method comprises the following steps: arranging a drain electrode auxiliary electrode and a source electrode auxiliary electrode on the semiconductor module to be tested; carrying out power cycle test on the semiconductor module; obtaining test data through the drain electrode auxiliary electrode and the source electrode auxiliary electrode, and determining the resistance of a source electrode bonding wire and the resistance of a welding layer; and (4) counting the resistance of each part to obtain the change relation between the resistance of the source bonding wire and the resistance of the welding layer along with the power cycle period. According to the scheme, the auxiliary electrode is added to each chip, so that the degradation phenomenon of the chip bonding wire and the welding layer can be evaluated in an online manner in a lossless manner, and the change relation of the resistance of the chip bonding wire and the welding layer along with the power cycle number is obtained; the resistance test and the power cycle test are integrated, the original power cycle test process is not required to be changed, and the test result is not influenced.
Description
Technical Field
The application relates to the technical field of power semiconductors, in particular to a method for evaluating power cycle capability of a semiconductor module and the semiconductor module.
Background
The application of the silicon carbide (SiC) power device can greatly improve the performance of the power electronic converter, and the silicon carbide (SiC) power device is initially applied to various occasions such as industrial frequency conversion, electric automobiles, rail traction, renewable energy power generation and the like. With the gradual maturity of SiC materials and process technologies, SiC power devices are expected to replace the traditional Si-based power devices, and are widely applied and developed in future power electronic converters.
SiC chip operating temperatures can exceed 250 ℃, which presents significant challenges to chip bond wire and solder layer life. In recent years, researchers have significantly improved the power cycling capability of modules by matching the thermal expansion coefficients between the packaging materials, optimizing the process parameters. However, the current testing method cannot evaluate the change conditions of the chip bonding wire and the solder layer respectively, and brings difficulty to the selection of further packaging materials and process optimization.
In the related art, the module life needs to be evaluated by a power cycle test. In the power cycle test, the SiC MOSFET chip is heated to a certain temperature under the action of self load current and is naturally cooled to a certain temperature after being turned off, and the process enables the chip to generate a certain junction temperature difference (delta Tj). After many cycles, the difference between the thermal expansion coefficients of the packaging materials can cause the phenomena of bonding point cracking and welding layer separation, the resistance on a chip conduction loop is increased, and the saturation voltage drop of the module is increased.
The power cycle test has the following disadvantages: the resistance change conditions of the chip bonding wire and the welding layer cannot be respectively calibrated; for SiC MOSFET chips, the problem of gate degradation after multiple switching can lead to inaccurate life assessment.
Disclosure of Invention
To overcome, at least to some extent, the problems in the related art, the present application provides a method of evaluating power cycling capability of a semiconductor module and a semiconductor module.
According to a first aspect of embodiments of the present application, there is provided a method of evaluating power cycling capability of a semiconductor module, comprising:
arranging a drain electrode auxiliary electrode and a source electrode auxiliary electrode on the semiconductor module to be tested;
carrying out power cycle test on the semiconductor module;
obtaining test data through the drain electrode auxiliary electrode and the source electrode auxiliary electrode, and determining the resistance of a source electrode bonding wire and the resistance of a welding layer;
and (4) counting the resistance of each part to obtain the change relation between the resistance of the source bonding wire and the resistance of the welding layer along with the power cycle period.
Further, the power cycle testing of the semiconductor module includes:
and applying a reference power supply on the source electrode main electrode, and grounding the drain electrode main electrode to enable current to sequentially pass through the source electrode main electrode, the copper layer, the source bonding wire, the semiconductor chip, the semiconductor welding layer, the copper layer, the drain bonding wire and the drain electrode main electrode.
Further, the semiconductor module performs a power cycle test, including:
carrying out power cycle test on the semiconductor module, carrying out resistance test on each part after testing for a plurality of periods, and recording the obtained resistance value;
and repeating the power cycle test and the resistance test until the service life of the semiconductor module is failed.
Further, when the saturation voltage drop of the semiconductor module increases by 5%, the semiconductor module fails.
Further, the plurality of periods are preset fixed test periods.
Further, the acquiring of the test data through the drain auxiliary electrode and the source auxiliary electrode includes:
measuring a first voltage, a second voltage and a third voltage respectively;
wherein the first voltage is a voltage between the drain auxiliary electrode and the drain main electrode, the second voltage is a voltage between the source auxiliary electrode and the drain main electrode, and the third voltage is a voltage between the source main electrode and the drain main electrode.
Further, the determining the source bond wire resistance and the solder layer resistance comprises:
and determining the resistance of the source bonding wire and the resistance of the welding layer according to the voltage division relation among the first voltage, the second voltage and the third voltage.
According to a second aspect of embodiments of the present application, there is provided a semiconductor module capable of applying the method according to any one of the above embodiments. The semiconductor module includes: the semiconductor chip is connected to the first copper layer through the chip welding layer; the semiconductor module further includes: a source main electrode, a drain main electrode, a source auxiliary electrode, a drain auxiliary electrode disposed on the first copper layer;
the source main electrode and the source auxiliary electrode are respectively connected with the semiconductor chip through bonding wires, and the drain main electrode and the drain auxiliary electrode are respectively connected with the semiconductor chip through bonding wires; the source auxiliary electrode and the drain auxiliary electrode are each connected to the outside through a bonding wire.
Furthermore, the bonding point connected to the drain auxiliary electrode is close to the semiconductor chip, and the bonding point connected to the source main electrode and the drain main electrode is far away from the semiconductor chip.
Further, the semiconductor chip is a SiC MOSFET chip.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
according to the scheme, the auxiliary electrode is added to each chip, so that the degradation phenomenon of the chip bonding wire and the welding layer can be evaluated in an online manner in a lossless manner, and the change relation of the resistance of the chip bonding wire and the welding layer along with the power cycle number is obtained; the resistance test and the power cycle test are integrated, the original power cycle test process is not required to be changed, and the test result is not influenced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart illustrating a method of evaluating power cycling capability of a semiconductor module according to an exemplary embodiment.
Fig. 2 is one of schematic structural diagrams of a semiconductor module according to an exemplary embodiment.
Fig. 3 is a second schematic diagram of a semiconductor module according to an exemplary embodiment.
Fig. 4 is an equivalent circuit diagram of a semiconductor module according to an exemplary embodiment.
FIG. 5 is a flowchart illustrating an exemplary implementation of a loop test, according to an example embodiment.
Reference numerals: 101-a semiconductor chip; 102-a die solder layer; 103-a first copper layer; 104-DBC ceramic; 105-a second copper layer; 106-DBC welding layer; 107-a bottom plate;
201-source main electrode; 202-a gate; 203-drain main electrode; 204-source auxiliary electrode; 205-drain auxiliary electrode.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of methods and modules consistent with aspects of the present application, as detailed in the appended claims.
In the relevant standards, a 5% increase in module saturation pressure drop is defined as failure. The equipment monitors the saturation voltage drop and the thermal resistance of the module in the power cycle test, wherein the saturation voltage drop test can detect the resistance change condition of a bonding wire and a welding layer, and the thermal resistance test can evaluate the thermal resistance change condition of the welding layer of the chip. In this way, the module power cycling capability is evaluated.
A method capable of evaluating the degradation of a bonding wire and a welding layer of a SiC MOSFET chip on line does not exist. The invention provides a structure for evaluating the power cycle capability of a SiC MOSFET module, which can be used for testing the change conditions of a chip bonding wire and a welding layer on line when evaluating the capability of a power module, provides support for module life research and provides suggestions for the optimization of packaging materials and processes.
FIG. 1 is a flow chart illustrating a method of evaluating power cycling capability of a semiconductor module according to an exemplary embodiment. The method may comprise the steps of:
step S1, arranging a drain electrode auxiliary electrode and a source electrode auxiliary electrode on the semiconductor module to be tested;
step S2, performing power cycle test on the semiconductor module;
step S3, test data are obtained through the drain electrode auxiliary electrode and the source electrode auxiliary electrode, and the resistance of a source electrode bonding wire and the resistance of a welding layer are determined;
and step S4, counting the resistance of each part to obtain the variation relation between the resistance of the source bonding wire and the resistance of the solder layer along with the power cycle period.
According to the scheme, the auxiliary electrode is added to each chip, so that the degradation phenomenon of the chip bonding wire and the welding layer can be evaluated in an online manner in a lossless manner, and the change relation of the resistance of the chip bonding wire and the welding layer along with the power cycle number is obtained; the resistance test and the power cycle test are integrated, the original power cycle test process is not required to be changed, and the test result is not influenced.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
To further detail the technical solution of the present application, a semiconductor module to which the method of the present application can be applied is first introduced.
As shown in fig. 2 and 3, the semiconductor module includes: the semiconductor chip is connected to the first copper layer through the chip welding layer; the semiconductor module further includes: a source main electrode, a drain main electrode, a source auxiliary electrode, a drain auxiliary electrode disposed on the first copper layer. In some embodiments, the semiconductor chip may be a SiC chip.
The source main electrode and the source auxiliary electrode are respectively connected with the semiconductor chip through bonding wires, and the drain main electrode and the drain auxiliary electrode are respectively connected with the semiconductor chip through bonding wires; the source auxiliary electrode and the drain auxiliary electrode are each connected to the outside through a bonding wire. An equivalent circuit of the semiconductor module is shown in fig. 4.
The following describes the scheme of the present application in an expanded manner with reference to a specific application scenario.
As shown in fig. 5, the specific implementation flow of the present application is as follows:
1. and when the SiC MOSFET module is designed, a drain auxiliary electrode and a source auxiliary electrode are added to each SiC MOSFET chip. The auxiliary electrode is connected with the outside through a bonding wire, a bonding point connected with the drain auxiliary electrode is as close to the chip as possible, and a bonding point connected with the source and drain main electrodes is as far away from the chip as possible.
2. And a constant current source is added at the main electrode of the source electrode, the main electrode of the drain electrode is grounded, and the current flows to the ground through the main electrode of the source electrode, the copper layer, the bonding wire of the source electrode, the body diode of the MOSFET, the resistance of the welding layer, the copper layer, the bonding wire of the drain electrode and the main electrode of the drain electrode. The voltage between the drain auxiliary electrode and the drain main electrode, the voltage between the source auxiliary electrode and the drain main electrode, and the voltage between the source auxiliary electrode and the drain main electrode are measured, respectively. The resistance value of each portion is obtained by calculation.
As shown in fig. 4, in some embodiments, the performing the power cycle test on the semiconductor module includes: a reference power is applied to the source main electrode, the drain main electrode is grounded, and a current passes through the source main electrode R33, the copper layer R32, the source bonding wire R31, the semiconductor chip, the semiconductor solder layer R2, the copper layer R13, the drain bonding wire R12, and the drain main electrode R11 in this order.
In some embodiments, the acquiring test data through the drain auxiliary electrode and the source auxiliary electrode includes: the first voltage, the second voltage and the third voltage are measured, respectively.
As shown in fig. 4, the first voltage is a voltage U1 between the drain auxiliary electrode and the drain main electrode, the second voltage is a voltage (U2+ U1) between the source auxiliary electrode and the drain main electrode, and the third voltage is a voltage (U3+ U2+ U1) between the source main electrode and the drain main electrode.
In some embodiments, the determining the source bond wire resistance and the solder layer resistance comprises: and determining the resistance of the source bonding wire and the resistance of the welding layer according to the voltage division relation among the first voltage, the second voltage and the third voltage.
3. And carrying out power cycle test on the SiC MOSFET module, and testing and recording the resistance value of each part after testing for a certain period.
In some embodiments, the semiconductor module performs power cycle testing, comprising: carrying out power cycle test on the semiconductor module, carrying out resistance test on each part after testing for a plurality of periods, and recording the obtained resistance value; and repeating the power cycle test and the resistance test until the service life of the semiconductor module is failed.
In some embodiments, the number of periods is a preset fixed test period. For example, if the preset test period is 10 times, the power test is performed 10 times per cycle, and the resistance is measured once.
As shown in fig. 4, in the power cycle test, the resistance values of the source main electrode R33, the copper layers (R32, R13), the drain bonding wire R12, and the drain main electrode R11 do not change, and the saturation voltage drop of the MOSFET body diode does not change at a constant current; the source bonding wire R31 and the welding layer R2 have cracking and delamination phenomena due to the difference of the thermal expansion coefficients of the packaging materials, and the resistance is increased.
4. And repeating the power cycle test and the resistance test until the service life of the module is failed. In some embodiments, when the saturation voltage drop of the semiconductor module (SiC chip) increases by 5%, the semiconductor module fails.
5. And (4) counting the variation relation of each part of resistance along with the power cycle period to obtain the variation relation of the resistance of the source bonding wire R31 and the resistance of the solder layer R2 along with the power cycle period.
Compared with the traditional power cycle test mode, the method has the following advantages:
1. and calibrating the degradation phenomenon of each SiC MOSFET chip bonding wire and welding layer respectively.
2. And calibrating the degradation phenomenon of each SiC MOSFET chip bonding wire and welding layer respectively in a lossless mode.
3. The change condition of saturation voltage drop of the SiC MOSFET chip body diode is used as a judgment basis, so that the degradation phenomenon of the grid electrode of the SiC MOSFET chip caused by multiple switching is avoided, and the test accuracy is improved.
4. The layout design of the module chips is guided by measuring each chip, so that the problem of early service life failure of some chips when multiple chips are connected in parallel is avoided.
As shown in fig. 3, an embodiment of the present application also provides a semiconductor module including: the semiconductor chip is connected to the first copper layer through the chip welding layer; the semiconductor module further includes: a source main electrode, a drain main electrode, a source auxiliary electrode, a drain auxiliary electrode disposed on the first copper layer.
The source main electrode and the source auxiliary electrode are respectively connected with the semiconductor chip through bonding wires, and the drain main electrode and the drain auxiliary electrode are respectively connected with the semiconductor chip through bonding wires; the source auxiliary electrode and the drain auxiliary electrode are each connected to the outside through a bonding wire.
In some embodiments, the bonding point connected to the drain auxiliary electrode is close to the semiconductor chip, and the bonding point connected to the source main electrode and the drain main electrode is far away from the semiconductor chip.
In some embodiments, the semiconductor chip is a SiC MOSFET chip.
According to the invention, the degradation phenomena of the bonding wire and the welding layer of the chip are respectively evaluated on line by adding the auxiliary electrode to each SiC MOSFET chip, and meanwhile, the voltage drop change of the body diode of the SiC MOSFET is used as a failure judgment standard, so that the problem of degradation of the grid electrode of the SiC MOSFET chip is avoided, and the test accuracy is improved.
The module structure of this application is the same with traditional welded type SiC module, and the chip drain electrode is connected through the welding mode with DBC, and the source electrode is connected through the bonding wire mode with DBC. The invention tests the resistance change conditions of the chip bonding wire and the welding layer by adding the auxiliary electrode to each SiC MOSFET chip, and respectively calibrates the degradation of the chip bonding wire and the welding layer. The test result can be used for module life research on one hand, and can be used for optimizing chip layout on the other hand, so that early life failure of part of chips caused by thermal coupling and stress distribution is avoided. Meanwhile, the saturation voltage drop change of the parasitic body diode of the SiC MOSFET is used as a judgment basis in failure, so that the grid degradation phenomenon of the SiC MOSFET chip caused by multiple switching processes is avoided, and the test accuracy is improved.
The scheme of the invention combines the module power cycle test, and can carry out online nondestructive evaluation on the degradation phenomenon of the bonding wire and the welding layer of the chip by adding the auxiliary electrode to each SiC MOSFET chip, and simultaneously utilize the body diode voltage drop of the SiC MOSFET as calibration, thereby avoiding the test drift problem caused by the degradation of the grid electrode of the SiC MOSFET chip and improving the test accuracy.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A method of evaluating power cycling capability of a semiconductor module, comprising:
arranging a drain electrode auxiliary electrode and a source electrode auxiliary electrode on the semiconductor module to be tested;
carrying out power cycle test on the semiconductor module;
obtaining test data through the drain electrode auxiliary electrode and the source electrode auxiliary electrode, and determining the resistance of a source electrode bonding wire and the resistance of a welding layer;
and (4) counting the resistance of each part to obtain the change relation between the resistance of the source bonding wire and the resistance of the welding layer along with the power cycle period.
2. The method of claim 1, wherein the power cycling the semiconductor module comprises:
and applying a reference power supply on the source electrode main electrode, and grounding the drain electrode main electrode to enable current to sequentially pass through the source electrode main electrode, the copper layer, the source bonding wire, the semiconductor chip, the semiconductor welding layer, the copper layer, the drain bonding wire and the drain electrode main electrode.
3. The method of claim 2, wherein the semiconductor module is subjected to a power cycle test comprising:
carrying out power cycle test on the semiconductor module, carrying out resistance test on each part after testing for a plurality of periods, and recording the obtained resistance value;
and repeating the power cycle test and the resistance test until the service life of the semiconductor module is failed.
4. The method of claim 3, wherein the semiconductor module fails when the saturation pressure drop of the semiconductor module increases by 5%.
5. The method of claim 3, wherein the number of periods is a predetermined fixed test period.
6. The method of any one of claims 1-5, wherein said obtaining test data via a drain auxiliary electrode and a source auxiliary electrode comprises:
measuring a first voltage, a second voltage and a third voltage respectively;
wherein the first voltage is a voltage between the drain auxiliary electrode and the drain main electrode, the second voltage is a voltage between the source auxiliary electrode and the drain main electrode, and the third voltage is a voltage between the source main electrode and the drain main electrode.
7. The method of claim 6, wherein said determining a source bond wire resistance and a layer resistance comprises:
and determining the resistance of the source bonding wire and the resistance of the welding layer according to the voltage division relation among the first voltage, the second voltage and the third voltage.
8. A semiconductor module applying the method according to any one of claims 1 to 7, comprising: the semiconductor chip is connected to the first copper layer through the chip welding layer; characterized in that the semiconductor module further comprises: a source main electrode, a drain main electrode, a source auxiliary electrode, a drain auxiliary electrode disposed on the first copper layer;
the source main electrode and the source auxiliary electrode are respectively connected with the semiconductor chip through bonding wires, and the drain main electrode and the drain auxiliary electrode are respectively connected with the semiconductor chip through bonding wires; the source auxiliary electrode and the drain auxiliary electrode are each connected to the outside through a bonding wire.
9. The semiconductor module of claim 8, wherein the bond point to the drain auxiliary electrode is located close to the semiconductor chip, and the bond point to the source main electrode and the drain main electrode is located far from the semiconductor chip.
10. The semiconductor module according to claim 8, wherein the semiconductor chip is a SiC MOSFET chip.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117195665A (en) * | 2023-11-07 | 2023-12-08 | 湖南大学 | Method for constructing life prediction model of bonding wire of power semiconductor device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB493916A (en) * | 1936-04-16 | 1938-10-17 | British Thomson Houston Co Ltd | Improvements in and relating to electric oscillatory power supply circuits |
| US20100224880A1 (en) * | 2009-03-05 | 2010-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN108802590A (en) * | 2018-06-22 | 2018-11-13 | 华北电力大学 | A kind of the power circulation test method and test system of semiconductor devices |
| CN110161398A (en) * | 2018-09-04 | 2019-08-23 | 河北工业大学 | A method of IGBT power module ageing state is assessed using shell temperature |
| CN111239576A (en) * | 2018-11-29 | 2020-06-05 | 株洲中车时代电气股份有限公司 | Constant power cycle test circuit and method based on power loss linear control |
| CN112098789A (en) * | 2020-08-04 | 2020-12-18 | 株洲中车时代半导体有限公司 | Statistical method and device for service life of IGBT module, electronic equipment and storage medium |
| US20200400738A1 (en) * | 2019-06-18 | 2020-12-24 | Board Of Regents, The University Of Texas System | Methods of monitoring conditions associated with aging of silicon carbide power mosfet devices in-situ, related circuits and computer program products |
| CN113491059A (en) * | 2019-03-01 | 2021-10-08 | 三菱电机株式会社 | Semiconductor device and method for diagnosing semiconductor device |
| CN114019335A (en) * | 2020-07-17 | 2022-02-08 | 中车永济电机有限公司 | Power device detection device and method |
-
2022
- 2022-01-06 CN CN202210011740.XA patent/CN114325288A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB493916A (en) * | 1936-04-16 | 1938-10-17 | British Thomson Houston Co Ltd | Improvements in and relating to electric oscillatory power supply circuits |
| US20100224880A1 (en) * | 2009-03-05 | 2010-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN108802590A (en) * | 2018-06-22 | 2018-11-13 | 华北电力大学 | A kind of the power circulation test method and test system of semiconductor devices |
| CN110161398A (en) * | 2018-09-04 | 2019-08-23 | 河北工业大学 | A method of IGBT power module ageing state is assessed using shell temperature |
| CN111239576A (en) * | 2018-11-29 | 2020-06-05 | 株洲中车时代电气股份有限公司 | Constant power cycle test circuit and method based on power loss linear control |
| CN113491059A (en) * | 2019-03-01 | 2021-10-08 | 三菱电机株式会社 | Semiconductor device and method for diagnosing semiconductor device |
| US20200400738A1 (en) * | 2019-06-18 | 2020-12-24 | Board Of Regents, The University Of Texas System | Methods of monitoring conditions associated with aging of silicon carbide power mosfet devices in-situ, related circuits and computer program products |
| CN114019335A (en) * | 2020-07-17 | 2022-02-08 | 中车永济电机有限公司 | Power device detection device and method |
| CN112098789A (en) * | 2020-08-04 | 2020-12-18 | 株洲中车时代半导体有限公司 | Statistical method and device for service life of IGBT module, electronic equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 李世平: "IGBT 模块功率循环能力与可靠性试验", 《机车电传动》, pages 1 - 4 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117195665A (en) * | 2023-11-07 | 2023-12-08 | 湖南大学 | Method for constructing life prediction model of bonding wire of power semiconductor device |
| CN117195665B (en) * | 2023-11-07 | 2024-01-26 | 湖南大学 | Method for constructing life prediction model of bonding wire of power semiconductor device |
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