JP7119521B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a silicon carbide (SiC) semiconductor device and its manufacturing method.

Commercially available SiC single crystal substrates are mainly manufactured by a sublimation method. Sublimation substrates contain a large number of dislocations including basal plane dislocations (BPDs). Such dislocations are taken over by an epitaxial substrate obtained by epitaxially growing a SiC single crystal on the substrate. Therefore, it is known that the characteristics of the semiconductor device formed on the epitaxial substrate are adversely affected.

In particular, basal plane dislocations cause deterioration of characteristics, particularly forward characteristics, of SiC semiconductor devices such as bipolar devices or MOS field effect transistors (FETs) in which bipolar operation is included at turn-off due to built-in diodes. In a SiC semiconductor device such as a MOS field effect transistor (FET) as well, it causes deterioration of the forward characteristics of the built-in diode that performs bipolar operation when turned off. For example, minority carriers (holes in n-type semiconductors, electrons in p-type semiconductors) generated by forward conduction during bipolar operation diffuse in the epitaxial substrate. When the minority carriers recombine around the basal plane dislocation and give recombination energy above a certain level to the basal plane dislocation, stacking faults extend in the epitaxial substrate starting from the basal plane dislocation. When the stacking fault expands, the on-voltage rises and the forward resistance increases when a forward current is applied. A method for sorting and inspecting defective products with deteriorated device characteristics is required.

In Patent Document 1, the temperature of the bipolar element is set to 150° C. or higher and 230° C. or lower, and the current density is 120 A/cm ² or higher and 400 A/cm ² or lower. A method has been proposed to check the However, even if the screening and inspection conditions are harsher than the actual usage conditions, new element characteristic deterioration may occur during actual usage, leading to a decrease in the reliability of the semiconductor device.

Japanese Patent No. 6104363

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a SiC semiconductor device and a method of manufacturing the same that can prevent deterioration in reliability of the semiconductor device due to degradation of forward characteristics.

In order to achieve the above object, according to one aspect of the present invention, there are provided the following steps: (a) fabricating a semiconductor device including a bipolar element using a silicon carbide epitaxial substrate as a base; A first test temperature of 175°C or less is applied, and a forward current is passed through the bipolar element at a first current density of 20 A/cm2 or more and 400 A/cm2 or less, and defective products whose forward characteristics have increased above the reference value are removed. (c) the remaining non-defective bipolar devices from which defective products have been removed are subjected to a second inspection temperature of 50° C. or more and 175° C. or less, and a second inspection temperature of 65 A/cm or more and 110 A/cm or less; A second screening inspection for removing new defective products whose forward characteristic value has increased above the reference value by applying a forward current at a current density, the product of the first inspection temperature and the first current density The gist of the present invention is a method for manufacturing a SiC semiconductor device, wherein a defined first stress intensity is greater than a second stress intensity defined by a product of a second inspection temperature and a second current density .

According to another aspect of the present invention, (a) a bipolar element is included, and the value of the forward characteristic at a first stress intensity defined by the product of a first current density of a forward current flowing through the bipolar element and a first surface temperature is A first sorting inspection for removing defective products that have increased beyond the reference value, a second stress strength defined by the product of the second current density of the forward current flowing through the bipolar element and the second surface temperature, and the value of the forward characteristic A semiconductor device based on a silicon carbide epitaxial substrate selected by a second screening inspection for removing defective products having increased to a reference value or more, wherein (b) the first stress intensity is higher than the second stress intensity. The main gist of the invention is a silicon carbide semiconductor device in which a ratio of a projected area of a stacking fault generated in an epitaxial layer of an epitaxial substrate onto the upper surface of the epitaxial layer to the area of the upper surface is 3.4% or less.

ADVANTAGE OF THE INVENTION According to this invention, the SiC semiconductor device which can prevent the deterioration of the reliability of a semiconductor device by deterioration of a forward characteristic, and its manufacturing method can be provided.

1 is a schematic cross-sectional view showing an example of a semiconductor device used for describing an embodiment of the present invention; FIG. FIG. 2 is a schematic cross-sectional view showing an example of basal plane dislocations distributed near the interface between the substrate and the epitaxial layer; FIG. 4 is a schematic cross-sectional view showing a basal plane dislocation in which expansion of stacking faults has been detected by a normal sorting inspection; FIG. 4 is a diagram showing the result of an electrical test performed after the sorting inspection shown in FIG. 3; It is a figure which shows the relationship between the current density and stacking-fault occurrence rate in an electricity test. 4 is a PL image showing extended stacking faults in an epitaxial substrate. FIG. 4 is a diagram showing the relationship between the projected area ratio of stacking faults projected onto the epitaxial substrate surface and the forward voltage change rate; 4 is a flow chart showing an example of a method for manufacturing a semiconductor device according to an embodiment of the invention; It is process sectional drawing for demonstrating an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. FIG. 10 is a process cross-sectional view subsequent to FIG. 9 for explaining the example of the method of manufacturing the semiconductor device according to the embodiment of the present invention; FIG. 11 is a cross-sectional view of the process subsequent to FIG. 10 for explaining the example of the method of manufacturing the semiconductor device according to the embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and overlapping descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may differ from the actual ones. In addition, portions having different dimensional relationships and ratios may also be included between drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not specified below.

Further, the definitions of directions such as up and down in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. For example, if an object is observed after being rotated by 90°, it will be read with its top and bottom converted to left and right, and if it is observed after being rotated by 180°, it will of course be read with its top and bottom reversed. Further, in the following description, a case where the first conductivity type is the n-type and the second conductivity type is the p-type will be exemplified. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Moreover, + and - attached to n and p mean semiconductor regions having relatively high or low impurity densities, respectively, compared to semiconductor regions not marked with + and -. However, even if the semiconductor regions are given the same n and n, it does not mean that the impurity density of each semiconductor region is exactly the same. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

In the following description, a MOS transistor having a trench gate structure having a parasitic body diode is used as a representative example of a semiconductor device, but the semiconductor device of the present invention is not limited to a trench gate structure MOS transistor. For example, a MOS transistor with a planar gate structure, a MISFET, a static induction transistor (SIT), or the like may be used. Alternatively, a pin diode or the like having a pn junction may be used. Furthermore, a bipolar device such as an insulated gate bipolar transistor (IGBT), a static induction thyristor (SI thyristor), or a gate turn-off thyristor (GTO), in which a forward current is passed through a pn junction, may be used.

(Structure of main part of semiconductor device)
A ^{semiconductor} device according to an embodiment of the present invention, as shown in FIG. It is called a base. The substrate includes three SiC epitaxial layers (2, 3, 4) of an n ⁺ -type buffer layer 2, an n- -type drift region 3 and a second conductivity type (p-type) base region 4. . Three epitaxial layers (2, 3, 4) are sequentially grown on the SiC substrate forming the n ⁺ -type drain region 1 to form a base. A p ⁺ -type base contact region 5 and an n ⁺ -type source region 6 are selectively provided above the base region 4 forming the upper portion of the substrate. Source region 6 has a higher impurity density than drift layer 3 , and base contact region 5 has a higher impurity density than base region 4 . Drift region 3 has a lower impurity density than drain region 1 .

SiC crystals have crystal polymorphism, the main ones being cubic 3C and hexagonal 4H and 6H. The forbidden band width at room temperature is reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. The embodiments of the present invention will be described using 4H—SiC.

A gate trench 7 is provided from the upper surface of the source region 6 to reach the drift region 3 through the source region 6 and the base region 4 . A gate insulating film 8 is provided on the bottom and side surfaces of the gate trench 7 . A gate electrode 9 is embedded in the gate trench 7 via a gate insulating film 8 to form an insulated gate type electrode structure (8, 9). Although FIG. 1 illustrates the case where the gate electrode 9 is embedded only in the gate trench 7, the gate electrode 9 may extend to the upper surface of the source region 6 via the gate insulating film 8. .

As a material of the gate electrode 9, for example, a polysilicon layer (doped polysilicon layer) doped with an impurity such as phosphorus (P) at a high concentration can be used. Source electrodes (surface electrodes) (11, 12, 13) are provided on the gate electrode 9 with an interlayer insulating film 10 interposed therebetween. Source electrodes ( 11 , 12 , 13 ) are electrically connected to source region 6 and base contact region 5 .

The source electrodes (11, 12, 13) comprise a source contact layer 11, a lower barrier metal layer 12, and an upper barrier metal layer 13, which serve as underlying metals. The source contact layer 11 is arranged as an ohmic electrode so as to metallurgically contact the source region 6 and the base contact region 5 . Lower barrier metal layer 12 is metallurgically in contact with source region 6 and is arranged to cover interlayer insulating film 10 . Upper barrier metal layer 13 is arranged to cover source contact layer 11 and lower barrier metal layer 12 . For example, a nickel (Ni) film as the source contact layer 11, a titanium nitride (TiN) film as the lower barrier metal layer 12, and a titanium (Ti)/TiN/Ti laminated structure as the upper barrier metal layer 13 can be used.

A drain electrode (back surface electrode) 14 is arranged on the lower surface side of the drain region 1 so as to be in contact with the drain region 1 . As the drain electrode 14, for example, a single layer film made of gold (Au) or a metal film in which Al, nickel (Ni), and Au are laminated in this order can be used. A metal plate such as tungsten (W) may be laminated.

In the structure shown in FIG. 1, the p-type base region 4 is formed above the n-type drift region 3 to form a pn junction built-in diode that constitutes a potential barrier for controlling carrier injection. That is, the base contact region 5, the base region 4, the drift region 3, the buffer layer 2 and the drain region 1 form built-in diodes (body diodes) (5, 4, 3, 2, 1). From the semiconductor substrate, the drain region 1 functions as a "cathode region" of the body diode, and the drift region 3 on the buffer layer 2 functions as a "running region" in which carriers drift. The base contact region 5 and the base region 4 also function as the "anode region" of the body diode. Therefore, the drain electrode 14 provided on the lower surface of the drain region 1 functions as a "cathode electrode" and supplies carriers supplied to the drain region 1 to an external circuit via the drain electrode 14 . The source electrodes (11, 12, 13) provided on the upper surface of the base contact region 5 function as the "anode electrode" of the body diode, and an external circuit is connected to the base contact region 5 via the source electrodes (11, 12, 13). and supply carriers to the base region 4 . Carriers (electrons) supplied from the drain region 1 travel in the drift region 3 in a drift electric field. Carriers (holes) are injected into the drift region 3 from the base contact region through the base region 4 .

The drain region 1, the drift region 3 epitaxially grown on the drain region 1, and the base region 4 and the base contact region 5 formed on the drift region 3 are made of SiC crystal. The surface of the drain region 1 is a (0001) Si plane and has an off angle of about 0° to 8° in the <11-20> direction with respect to the <0001> (c-axis) direction. The drift region 3 , base region 4 and base contact region 5 epitaxially grown on the drain region 1 also have the same off-angle as the drain region 1 . The n-type impurity of the drift region 3 is nitrogen (N), for example, and the impurity density is in the range of about 1×10 ¹⁵ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ . The thickness of the drift region 3 ranges from about 1 μm to several hundred μm, and the optimum thickness and impurity density are selected according to the breakdown voltage specifications of the body diodes (5, 4, 3, 2, 1).

A normal SiC substrate has basal plane dislocations on the order of 1000/cm ² . As shown in FIG. 2, when the epitaxial layer 3a is epitaxially grown on the substrate 1a, most of the basal plane dislocations 20 are converted into threading dislocations parallel to the c-axis of the SiC crystal within the epitaxial layer 3a. On the other hand, some of the basal plane dislocations 20 propagate from the substrate 1a to the epitaxial layer 3a. When a pn diode is formed using such epitaxial substrates (1a, 3a), basal plane dislocations 20 in the vicinity of the interface between the substrate 1a and the epitaxial layer 3a can become starting points for expansion of stacking faults due to current application. That is, holes are injected into the epitaxial layer 3a from the p-type anode region formed in the upper portion of the epitaxial layer 3a, so that the basal plane dislocations 20 become starting points for expanding stacking faults. Threading dislocations converted from the basal plane dislocations 20 do not extend to stacking faults.

Holes are injected from the anode region of the body diode as "minority carriers" into n-type epitaxial layer 3a. It is known that the electronic level of this stacking fault is 0.2 eV to 0.3 eV lower than the bottom of the conduction band of the 4H—SiC crystal. An electron in the conduction band generated by forward conduction or photoexcitation recombines with a hole at the electronic level of the stacking fault, resulting in expansion of the stacking fault. Since this recombination energy is small, expansion of the stacking fault does not occur unless the density of holes reaching the stacking fault exceeds the threshold value. The threshold hole density is said to be about 1×10 ¹⁵ cm ⁻³ . Epitaxial layer 3a has a low impurity density, and the diffusion depth of holes injected into epitaxial layer 3a is about 10 μm. Therefore, when the epitaxial layer 3a having a thickness of about 10 μm is used as the running region of the body diode, holes injected from the anode region can reach the substrate 1a at a density equal to or higher than the threshold. Starting from basal plane dislocations 20 localized in the vicinity of the interface between epitaxial layer 3a and substrate 1a, stacking faults extend along the basal plane within epitaxial layer 3a. The basal plane is the (0001) Si plane, and the conducting direction of the body diode is almost perpendicular to the basal plane. Since the stacking fault becomes a high-resistance region, the current flows through the region without the stacking fault. As a result, deterioration of forward characteristics such as an increase in ON voltage (forward voltage) and an increase in ON resistance is caused.

Using the epitaxial substrates (1a, 3a) shown in FIG. 2, a pn junction forming a body diode was fabricated, and sorting inspection was performed by forward conduction. A normal sorting inspection is carried out under sorting conditions in which the forward current density and the surface temperature are set higher than the actual usage conditions of the body diode. For example, the screening test was performed under screening conditions that are more than twice the actual usage conditions, a forward current density of 370 A/cm ² , and a body diode surface temperature of 150°C. As shown in FIG. 3, stacking faults occur starting from basal plane dislocations 21 existing within a diffusion depth Dth at which the hole density is equal to or greater than the threshold value under the sorting conditions. The diffusion depth Dth is deeper than the diffusion depth Dp at which the hole density is equal to or greater than the threshold under actual use conditions. Therefore, if the sorting inspection is performed under these sorting conditions and defective products are removed, it is assumed that defects due to deterioration of forward characteristics will not occur during actual use.

Actually, however, there is a possibility that stacking faults that are generated with delay or stacking faults that are in the process of expansion remain in the vicinity of the interface between the epitaxial layer 3a and the substrate 1a. FIG. 4 shows the result of conducting a current test after the sorting inspection under conditions close to actual usage conditions, a forward current density of 160 A/cm ² , and a surface temperature of the pn junction diode serving as the body diode of 150°C. As shown in FIG. 4, most diodes have a voltage change rate (forward voltage change rate) of ON voltage within about 1%. However, in some diodes, the forward voltage change rate increases to 2-5%. As described above, in the one-step sorting inspection that is usually performed, it is not possible to sufficiently sort out non-defective products, and there is a possibility that defects will occur during actual use.

As described above, generation of stacking faults due to forward conduction in the pn junction diodes fabricated by forming the p-type anode regions on the epitaxial substrates (1a, 3a) was evaluated. FIG. 5 shows the number of occurrences of stacking faults expanded at each current density while increasing the current density of the forward current flowing through the diode. When the temperature of the diode is 50° C., stacking faults extending from the epitaxial layer 3a occur at current densities ranging from 20 A/cm ² to 75 A/cm ² . In the current density range of 110 A/cm ² to 400 A/cm ² , stacking faults extending from the substrate 1a occur. When the temperature of the diode is 175° C., stacking faults extending from within the epitaxial layer 3a occur at current densities ranging from 10 A/cm ² to 50 A/cm ² . When the current density is in the range of 75 A/cm ² to 400 A/cm ² , stacking faults extending from the substrate 1a are generated. Thus, the generation of stacking faults is affected not only by the forward current but also by the surface temperature.

FIG. 6 shows a photoluminescence (PL) image observed from the surface side of the epitaxial layer 3a with expanded stacking faults. PL is composed of both fluorescence and phosphorescence processes and originates from absorption-emission processes between different electronic energy levels in the material. The PL measurement is performed by irradiating ultraviolet (UV) light from the surface of the epitaxial layer 3a. The PL images 22a and 22b are projected images of extended stacking faults on the surface of the epitaxial layer 3a. Stacking faults have right triangle and band shapes corresponding to their modes of expansion. The PL image 22a is a projection image of stacking faults of a right-angled triangle, and has a short side width L of about 143 μm and a long side width W of about 248 μm forming a right angle. The PL image 22b is a projection image of a strip-shaped stacking fault, and has a width L of about 143 μm and a longitudinal length of about 2.5 mm. The substrate 1a has an off-angle of 4° and the thickness of the epitaxial layer 3a is about 10 µm. A stacking fault extends from a basal plane dislocation near the interface between the substrate 1a and the epitaxial layer 3a to the surface along the basal plane. One of the acute angles of the PL images 22a and 22b is approximately 30° and the other is approximately 60°.

FIG. 7 shows the relationship between the rate of change in the forward voltage of a pn junction diode measured with expanded stacking faults and the ratio of the projected area of the stacking faults to the surface area of the pn junction diode (stacking fault projected area ratio). As shown in FIG. 7, the coefficient of determination of the regression line showing the relationship between the stacking fault projected area ratio and the forward voltage change ratio is about 0.97, indicating a strong correlation. For example, if the forward voltage change is about 3% or less, the stacking fault projected area ratio is about 3.4% or less.

As described above, normal one-step sorting inspection may expand the stacking faults during actual use, degrading the forward characteristics of the bipolar device structure. In the embodiment, multiple stages of sorting inspection are performed to suppress expansion of stacking faults and prevent deterioration of forward characteristics even during actual use. The stress intensity is defined as the product of the inspection temperature and the forward current density in the sorting inspection, and the stress intensity for each sorting inspection is set appropriately. For example, in the two-stage sorting inspection, the residual stacking fault is expanded by weakening the stress intensity in the second sorting inspection with respect to the stress intensity applied to the bipolar element structure in the first sorting inspection. Therefore, application of excessive stress can be avoided, and a decrease in the yield of non-defective products can be prevented. The forward characteristics depend on the projected area ratio of the generated stacking faults to the surface of the epitaxial layer. Therefore, in the embodiment, semiconductor devices having a forward voltage change rate of 3% or less are selected as non-defective products in the sorting inspection. The sorted semiconductor device has a stacking fault projected area ratio of about 3.4% or less.

(Method for manufacturing semiconductor device)
The method for manufacturing the semiconductor device according to the embodiment will be described below with reference to the flow chart of FIG. 8 and the process cross-sectional views of FIGS. 9 to 11 show only the n-type semiconductor region consisting of the drain region 1, the buffer layer 2, and the drift region 3 for convenience of explanation. It should be noted that the method of manufacturing a semiconductor device described below is merely an example, and that various other manufacturing methods, including this modified example, can be implemented within the scope of the scope of the claims. Of course.

At step S50 of the flow chart shown in FIG. 8, the trench gate type MOS transistor shown in FIG. 1 is manufactured by a conventional method. As shown in FIG. 9, an n ⁺ type buffer layer 2, an n type epitaxial layer that will be the drift region 3, and a base region 4 are formed on an n ⁺ type substrate of SiC crystal that will be the drain region 1 by an epitaxial growth technique or the like. A p-type epitaxial layer is continuously epitaxially grown. The substrate is a (0001) Si plane with the main plane turned 4° off in the <11-20> direction. The buffer layer 2 is doped with an n-type impurity such as nitrogen (N) at an impurity density of about 1×10 ¹⁸ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ . The epitaxial layer that forms the drift region 3 is doped with n-type impurities at a lower impurity density than the buffer layer 2 . The thicknesses of the buffer layer 2 and the epitaxial layer are, for example, about 1 μm and about 10 μm, respectively. The thickness of the base region 4 at this stage is, for example, about 0.3 to 1 μm.

Further, a p-type ion implantation mask having windows selectively opened in the region of the p ⁺ -type base contact region 5 is formed by photolithography, and p-type impurity ions are implanted into the upper portion of the base region 4 in multiple steps. do. After removing the p-type ion implantation mask, similarly, an n-type ion implantation mask having a window selectively opened in the region of the n ⁺ -type source region 6 is formed by photolithography, and an n-type impurity is removed. Ions are implanted in multiple stages above the base region 4 . After removing the n-type ion implantation mask, a heat treatment is performed to selectively form a base contact region 5 and a source region 6 above the base region 4 as shown in FIG. After that, an etching mask having windows selectively opened at trench positions is formed by photolithography, and reactive ion etching (RIE) or the like is performed to penetrate the source region 6 and the base region 4 to form an upper portion of the drift region 3 . Gate trenches 7 with reaching vertical sidewalls are formed. Then, a gate insulating film 8 is formed on the bottom and side surfaces of the gate trench 7 by a technique such as thermal oxidation.

Further, a gate electrode 9 is buried in the gate trench 7 through the gate insulating film 8 by a method such as chemical vapor deposition (CVD), thereby forming an insulating gate type electrode structure (8, 9) as shown in FIG. to form Furthermore, if this predetermined film formation process is performed, a trench type MOS transistor structure is formed on the upper part of the structure of the substrate based on the epitaxial layers (2, 3, 4). The drain region 1 contains many crystal defects such as basal plane dislocations 20 . In the buffer layer 2 grown on the drain region 1, most of the basal plane dislocations 20 propagating from the drain region 1 are converted into threading dislocations. Threading dislocations converted from basal plane dislocations do not extend into stacking faults.

First, the initial values of the forward characteristics of body diodes (5, 4, 3, 2, 1) built in a plurality of MOS transistors are measured. A forward voltage change is used as the forward characteristic. For example, the initial value of the forward voltage is measured at a normal temperature of 50° C. or less and a forward current density of 10 A/cm ² or less. On-resistance or the like may be used as the forward characteristic.

In step S51, body diodes (5, 4, 3, 2, 1) built in a plurality of MOS transistors are energized in the forward direction under the first selection condition. The energization is carried out by heating the MOS transistor with a hot plate or the like in the atmosphere. The first selection condition is that the surface temperature (inspection temperature) of the MOS transistor is 50° C. or more and 175° C. or less, the forward current density of the body diode (5, 4, 3, 2, 1) is 20 A/cm ² or more, It is 400 A/cm ² or less, and the energization time is about 10 minutes. As shown in FIG. 9, the forward energization supplies holes to the basal plane dislocations 20 existing within the diffusion depth Dth at which the hole density is equal to or greater than the threshold value under the first selection condition, and the stacking faults 22c, 22d, . 22e and 22f are generated. Since the time until the stacking faults 22c, 22d, 22e, and 22f start to expand varies, the extent of expansion varies. Stacking faults 22 c and 22 d greatly extend into drift region 3 or buffer layer 2 . Therefore, there is a high possibility that the forward voltage change rate of the body diodes (5, 4, 3, 2, 1) including the stacking faults 22c, 22d exceeds the reference value and becomes defective. On the other hand, the stacking faults 22e and 22f are in the process of expanding and do not significantly affect the forward characteristics. There are also basal plane dislocations 20 that convert to threading dislocations or the like in the substrate and do not extend to stacking faults. The MOS transistor may be heated in an inert gas such as nitrogen (N ₂ ) gas in a constant temperature bath or the like.

In step S52, the forward characteristics of the body diodes (5, 4, 3, 2, 1) are measured to perform the first sorting inspection. A forward voltage change is used as the forward characteristic. For example, the test value of the forward voltage is measured at a normal temperature of 50° C. or less and a forward current density of 10 A/cm ² or less. If the forward voltage change rate obtained from the forward voltage inspection value and the initial value exceeds a reference value, for example, 3%, the product is rejected as a defective product.

In step S53, the body diodes (5, 4, 3, 2, 1) are energized in the forward direction under the second selection condition. The energization is carried out by heating the MOS transistor with a hot plate or the like in the atmosphere. The second selection condition is that the inspection temperature is 50° C. or more and 175° C. or less, the forward current density of the body diode (5, 4, 3, 2, 1) is 65 A/cm ² or more and 110 A/cm ² or less, The energization time is about 10 minutes. As shown in FIG. 10, the forward energization supplies holes to the stacking faults 22e expanded within the diffusion depth De at which the hole density is equal to or greater than the threshold value under the second selection condition. The stacking fault 22 e re-expands to the drift region 3 . As a result, there is a high possibility that the forward voltage change rate of the body diode (5, 4, 3, 2, 1) including the stacking fault 22e exceeds the reference value and becomes defective. On the other hand, the stacking fault 22f is insufficiently supplied with holes and remains in the middle of expansion, which does not significantly affect the forward characteristics. Body diodes (5, 4, 3, 2, 1) containing basal plane dislocations 21 already extended to stacking faults under the first screening condition are removed if the forward voltage change rate exceeds the reference value, If it is within the standard value, it can be considered as a non-defective product.

In step S54, the forward characteristics of the body diodes (5, 4, 3, 2, 1) are measured to perform a second screening test. A forward voltage change is used as the forward characteristic. For example, the test value of the forward voltage is measured at a normal temperature of 50° C. or less and a forward current density of 10 A/cm ² or less. If the forward voltage change rate obtained from the forward voltage inspection value and the initial value exceeds a reference value, for example, 3%, the product is rejected as a defective product.

In step S55, non-defective products whose forward voltage change rates of the body diodes (5, 4, 3, 2, 1) are equal to or less than a reference value are sorted out. As shown in FIG. 11, the stacking fault 22f in the middle of expansion may remain in the body diode (5, 4, 3, 2, 1). Since the stacking fault 22f is located deeper than the diffusion depth Dp at which the hole density is equal to or greater than the threshold value under actual use conditions, it does not expand again during actual use. Although the diffusion depth Dp is positioned at the interface between the drain region 1 and the buffer layer 2 under the actual usage conditions, the diffusion depth Dp may be located within the buffer layer 2 . Body diodes (5, 4, 3, 2, 1) including basal plane dislocations 21 already extended to stacking faults under the first and second screening conditions are removed if the forward voltage change rate exceeds the reference value. However, if it is within the standard value, it is a non-defective product.

As described above, in the embodiment, the two-step sorting inspection can be performed to suppress the deterioration of the forward characteristics during actual use due to variations in stacking fault expansion. The diffusion depth Dp under the second selection condition in the latter stage is shallower than the diffusion depth Dth of holes under the first selection condition in the former stage. Therefore, the stress applied to the body diodes (5, 4, 3, 2, 1) by the sorting inspection is weaker under the second sorting condition than under the first sorting condition. If the stress is made stronger under the second sorting condition than under the first sorting condition, it will extend to unnecessary stacking faults from the viewpoint of actual use. As a result, an excessive number of defective products are selected, resulting in a decrease in yield. In addition, in the embodiment, a two-step sorting inspection is performed, but a plurality of three or more steps of sorting inspection may be performed. In this case, it is desirable to gradually weaken the stress toward the later stages.

As the first selection conditions, the test temperature is 50° C. or higher and 175° C. or lower, and the forward current density of the body diode (5, 4, 3, 2, 1) is 20 A/cm ² or higher and 400 A/cm ² or lower. there is When the inspection temperature is less than 50° C. and the current density is less than 20 A/cm ² , diffusion of holes into the drain region 1 is insufficient and stacking faults cannot be extended. If the current density exceeds 400 A/cm ² , stacking faults extend from an excessively deep position in the drain region 1, reducing the yield. In the case of a package made of the same material as a silicon semiconductor element, if the inspection temperature exceeds 175° C., the package of the semiconductor element may be damaged. However, in the case of a high-temperature package dedicated to SiC semiconductor elements, the rated temperature may be 200° C., the inspection temperature may be 200° C., and the forward current density may be 90 A/cm ² or more and 400 A/cm ² or less. Moreover, the forward current density of the first selection condition is preferably 110 A/cm ² or more. By increasing the diffusion depth Dth to the inside of the drain region 1, the stacking fault can be expanded sufficiently.

As shown in FIG. 5, the expansion of stacking faults depends not only on the forward current density but also on the inspection temperature. In the embodiment, the stress intensity in sorting inspection is defined by the product of inspection temperature and current density. Moreover, it is desirable to use the rating of the semiconductor device, which is the maximum use condition, as the actual use condition. For example, the MOS transistor shown in FIG. 5 has a rated current density of 75 A/cm ² and a rated temperature of 175°C. Since the stacking fault expansion phenomenon depends on the carrier density generated when the body diode is operating (it depends on both temperature and current), the product of the rated current density and the rated temperature is defined as the rated stress strength.

It is desirable that the stress intensity of the first sorting condition is higher than the stress intensity of the second sorting condition, and that the stress intensity of the second sorting condition is higher than the rated stress intensity. Moreover, it is desirable that the stress intensity of the first sorting condition is 1.2 times or more the rated stress intensity, and that 0.9 times the stress intensity of the first sorting condition is the stress intensity of the second sorting condition or more. In this case, new expansion of stacking faults can be prevented under actual use conditions within the rating.

It is desirable that the stress intensity of the first sorting condition is higher than the rated stress intensity and that the rated stress intensity is higher than the stress intensity of the second sorting condition. Further, the stress intensity of the first sorting condition is 1.2 times or more the rated stress intensity, and 0.93 times the rated stress intensity is set to be 0.93 times or more of the stress intensity of the second sorting condition, and the stress of the second sorting condition It is desirable to set the strength to 100° C.A/cm ² or more. In this case, the stress intensity under the second selection condition is set to be weaker than the rated stress intensity. It is possible to re-expand with the second selection condition.

(Other embodiments)
While embodiments of the present invention have been described above, the discussion and drawings forming part of this disclosure should not be construed as limiting the invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

As described above, 4H-SiC crystals are used in the embodiments, but crystal polymorphs such as cubic 3C-SiC and hexagonal 6H-SiC may also be used.

In the above, the MOS transistor was exemplified as the main device including the bipolar element. However, the semiconductor device as the main device including the bipolar element is not limited to the MOSFET, and may be a static induction transistor (SIT). Furthermore, a semiconductor device in which the main device is a bipolar element itself, such as a bipolar transistor (BJT) or an insulated gate bipolar transistor (IGBT), may be used. A static induction thyristor (SI thyristor), a gate turn-off (GTO) thyristor, etc. also operate in a bipolar manner, and therefore correspond to the "semiconductor device including a bipolar element" of the present invention. Of course, various other composite devices can also correspond to the "semiconductor device including a bipolar element" of the present invention.

As described above, the present invention naturally includes various embodiments and the like not described here, such as configurations in which the configurations described in the above embodiments and modifications are arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the valid scope of claims based on the above description.

DESCRIPTION OF SYMBOLS 1... Drain region 1a... Substrate (1a, 3a)... Epitaxial substrate 2... Buffer layer 3... Drift region 3a... Epitaxial layer 4... Base region 5... Base contact region (5, 4, 3, 2, 1)... Body diode 6 Source region 7 Gate trench 8 Gate insulating film 9 Gate electrode 10 Interlayer insulating film 11 Source contact layer 12 Lower barrier metal layer 13 Upper barrier metal layer 14 Drain electrode (back electrode)
20, 21... Basal plane dislocations 22a, 22b... PL images 22c, 22d, 22e, 22f... Stacking faults

Claims (8)

fabricating a semiconductor device including a bipolar element using a silicon carbide epitaxial substrate as a base;
The surface temperature of the semiconductor device is set to a first test temperature of 50° C. or higher and 175° C. or lower, a forward current is passed through the bipolar element at a first current density of 20 A/cm ² or higher and 400 A/cm ² or lower, and the forward characteristics are measured. A first sorting inspection that removes defective products whose value has increased to a reference value or more;
The remaining non-defective bipolar devices from which the defective devices have been removed are subjected to forward current at a second inspection temperature of 50° C. or higher and 175° C. or lower at a second current density of 65 A/cm ² or higher and 110 A/cm ² or lower. a second sorting inspection to remove new defective products whose forward characteristic value has increased above the reference value ;
A first stress intensity defined by the product of the first inspection temperature and the first current density is greater than a second stress intensity defined by the product of the second inspection temperature and the second current density. A method for manufacturing a silicon carbide semiconductor device. 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein said second stress intensity is higher than a rated stress intensity defined as a product of a rated operating temperature and a rated current density of said semiconductor device. 3. The method according to claim 2, wherein the first stress intensity is 1.2 times or more the rated stress intensity, and 0.9 times the first stress intensity is the second stress intensity or more. A method for manufacturing the silicon carbide semiconductor device described above. A first stress intensity defined by the product of the first test temperature and the first current density is greater than a rated stress intensity defined by the product of a rated operating temperature and a rated current density of the semiconductor device, and the rated stress 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the intensity is greater than a second stress intensity defined by a product of said second inspection temperature and said second current density. The first stress intensity is 1.2 times or more the rated stress intensity, and 0.93 times the rated stress intensity is the second stress intensity or more, and the second stress intensity is 100 ℃ A /cm ² or more, the method for manufacturing a silicon carbide semiconductor device according to claim 4. The carbonization according to any one of claims 1 to 5, wherein the forward characteristic is the forward voltage of the bipolar element, and the reference value is defined by voltage change of the forward voltage. A method for manufacturing a silicon semiconductor device. 7. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein said voltage change is defined by a projected area obtained by projecting stacking faults generated in an epitaxial layer of said epitaxial substrate onto an upper surface of said epitaxial layer. Eliminate defective products that include a bipolar element and have a forward characteristic value increased to a reference value or more at a first stress intensity defined by the product of a first current density of a forward current flowing through the bipolar element and a first surface temperature. a first sorting inspection, a defect in which the value of the forward characteristic increased to the reference value or more at a second stress intensity defined by the product of the second current density of the forward current flowing through the bipolar element and the second surface temperature; A semiconductor device based on a silicon carbide epitaxial substrate selected by a second screening inspection that removes non-defective products,
The first stress intensity is greater than the second stress intensity,
A silicon carbide semiconductor device, wherein a ratio of a projected area obtained by projecting stacking faults generated in an epitaxial layer of the epitaxial layer onto an upper surface of the epitaxial layer to an area of the upper surface is 3.4% or less.

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