JP2018101650A - Method for inspecting semiconductor device, and semiconductor base body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a method for inspecting a semiconductor device, by which a power-on test can be performed without applying an overload beyond a product design specification range; and a semiconductor base body.SOLUTION: A silicon carbide base body 12 has a laminate structure of a silicon carbide epitaxial growth layer 11, in which an element structure 10a making a diode structure of an element for inspection is formed. A method for inspecting a semiconductor device comprises the steps of: scratching the surface of a silicon carbide epitaxial growth layer 11 when screening silicon carbide base bodies 12; subsequently, passing a forward current through an element for inspection to cause the element for inspection to emit light, and observing a lamination defect extending from the place where the surface is scratched so as to calculate a speed of the extension of the lamination defect; then, calculating a hole density at an epi/substrate interface 8 when the forward current is running through the element for inspection, based on the extension speed of the lamination defect; and determining that the silicon carbide substrate 12 is a conforming product if the hole density is under a lower limit of a defect extension threshold hole density of the epi/substrate interface 8.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device inspection method and a semiconductor substrate.

  Includes bipolar operations such as pin (p-intrinsic-n) diodes made using silicon carbide (SiC) and parasitic diodes (body diodes) of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) It is known that bipolar degradation occurs in the element. Bipolar degradation is a phenomenon in which a stacking fault expands in a silicon carbide substrate when a device including a bipolar operation is energized in a forward direction, and a forward voltage drop increases.

  In order to prevent this bipolar degradation phenomenon from occurring in the product market, screening tests (energization tests) are performed under conditions of high current and high temperature on semiconductor chips and semiconductor wafers on which elements including bipolar operation are formed before shipment or during production. ) Is common. It has been empirically found that the bipolar deterioration phenomenon is likely to occur during operation under conditions of high current and high temperature. For this reason, the screening test is performed under conditions that are stricter than the actual use environment of the element based on the empirical rules of the workers.

It has been disclosed that the stacking fault expansion phenomenon that causes the bipolar deterioration phenomenon is caused when the hole (hole) density at the interface between the silicon carbide epitaxial layer and the silicon carbide substrate exceeds a predetermined value ( For example, see Patent Document 1 and Non-Patent Document 1 below.) FIG. 10 is an explanatory view schematically showing an expansion phenomenon of stacking faults in a conventional semiconductor device. In the conventional semiconductor device shown in FIG. 10, a silicon carbide substrate 112 formed by laminating a silicon carbide epitaxial growth layer 111 with few crystal defects on an n ⁺ type silicon carbide substrate 101 is used.

Here, a diode 110 is shown as an example of an element including a bipolar operation. N ⁺ type silicon carbide substrate 101 is an n ⁺ type cathode layer. On the front surface of n ⁺ -type silicon carbide substrate 101, n-type buffer layer 102, n ⁻ -type drift layer 103 and p-type anode layer 104 are sequentially laminated as silicon carbide epitaxial growth layer 111. Inside the p-type anode layer 104, a p ⁺ -type anode contact region 105 is formed by ion implantation. Reference numerals 106 and 107 denote an anode electrode and a cathode electrode.

When the diode 110 is energized in the forward direction, a hole 121 moves from the anode electrode 106 to the cathode electrode 107 through each layer of the silicon carbide substrate 112. At this time, if the hole density of interface (hereinafter referred to as epi / substrate interface) 108 between silicon carbide epitaxial growth layer 111 and n ⁺ -type silicon carbide substrate 101 exceeds a predetermined value, the basal plane existing at epi / substrate interface 108 From the dislocation 122, it is suggested that the stacking fault 123 expands in the silicon carbide epitaxial growth layer 111.

  As a method for detecting a stacking fault in a silicon carbide substrate, a method for detecting a stacking fault by a PL (Photoluminescence) method has been proposed (for example, see Patent Document 2 below).

Japanese Patent Laid-Open No. 2006-082197 JP, 2014-022503, A

K. Maeda, 3 others, Separation of the Driving Force and Radiation-Enhanced Dislocation Glide in 4H-SiC Forum (Materials Science Forum), (Switzerland), Trans Tech Publications Inc., July 2012, Vol. 725, pp. 35-40

As described above, the generation mechanism of the expansion phenomenon of the stacking fault 123 in the silicon carbide substrate 112 is disclosed. However, it is difficult to actually measure the hole density of the epi / substrate interface 108 and the hole density of the n ⁻ type drift layer 103 during forward energization of the device including the bipolar operation. For this reason, at present, it is in a situation where it is necessary to rely on a screening test method based on an empirical rule of the worker. In this case, in order to confirm that the stacking fault 123 does not occur in the silicon carbide epitaxial growth layer 111, a screening test is performed under severe conditions due to overload. As a result, there is a problem that the product life is shortened due to deterioration of the wiring or the like, or defective products are generated more than necessary, resulting in a decrease in yield.

  An object of the present invention is to provide an inspection method for a semiconductor device and a semiconductor substrate capable of conducting an energization test without applying an overload exceeding the design specification range of the product in order to eliminate the above-described problems caused by the prior art. And

  In order to solve the above-described problems and achieve the object of the present invention, a method for inspecting a semiconductor device according to the present invention includes applying a voltage to an electrode provided on a main surface of a semiconductor substrate made of silicon carbide, A method for inspecting a semiconductor device for inspecting the quality of the semiconductor device has the following characteristics. First, the semiconductor substrate in which an epitaxial growth layer made of silicon carbide is stacked on a semiconductor substrate made of silicon carbide is used as the anode electrode, and the electrode disposed on the first main surface of the semiconductor substrate on the epitaxial growth layer side is used as the semiconductor substrate. A first step of forming a diode using the electrode disposed on the second main surface on the substrate side as a cathode electrode is performed. Next, a second step of scratching the first main surface of the semiconductor substrate is performed. Next, a third step of calculating the expansion rate of the stacking fault by observing the stacking fault expanded when the diode is forward-turned from the damaged portion by causing the diode to emit light in the forward direction. I do. Next, based on the calculation result of the third step, a fourth step of calculating the hole density at the interface between the epitaxial growth layer and the semiconductor substrate is performed. Next, based on the calculation result of the fourth step, a fifth step of determining whether or not the semiconductor substrate is a non-defective product is performed.

  In the method for inspecting a semiconductor device according to the present invention, in the above-described invention, in the first step, the anode electrode is selectively removed to form a window opening portion exposing a part of the epitaxial growth layer. In the second step, the scratch is made on a portion of the epitaxial growth layer exposed at the window opening. In the third step, an extension phenomenon of the stacking fault is observed from a portion of the epitaxial growth layer exposed to the window opening portion.

  In the method for inspecting a semiconductor device according to the present invention, in the above-described invention, in the second step, the epitaxial growth layer is scratched through the anode electrode. In the third step, the stacking fault is expanded from the scratched portion by energizing the diode in the forward direction, and then the anode electrode is removed, the diode is caused to emit light, and the stacking fault is observed. It is characterized by that.

  The semiconductor device inspection method according to the present invention is characterized in that, in the above-described invention, in the second step, the scratch is made by denting the epitaxial growth layer.

  The semiconductor device inspection method according to the present invention is characterized in that, in the above-described invention, in the second step, the scratch is made by scratching the epitaxial growth layer.

  The semiconductor device inspection method according to the present invention is characterized in that, in the above-described invention, in the second step, the scratch is made by locally implanting an inert element into the epitaxial growth layer.

In the semiconductor device inspection method according to the present invention, in the above-described invention, the ion implantation of the inert element is performed at an impurity concentration of 1 × 10 ¹⁴ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. The thickness is 0.5 μm.

  In the method for inspecting a semiconductor device according to the present invention, in the above-described invention, in the fourth step, first, a characteristic formula indicating the relationship between the expansion rate of the stacking fault and the hole density of the epitaxial growth layer is acquired in advance. . The hole density at the interface between the epitaxially grown layer of the diode and the semiconductor substrate is obtained based on the calculation result of the third step and the characteristic formula.

  In the method for inspecting a semiconductor device according to the present invention, in the above-described invention, in the fifth step, first, a lower limit value of a hole density range of the epitaxial growth layer in which the stacking fault occurs is acquired in advance as a threshold value. And when the calculation result of the said 4th process is less than the said threshold value, the said semiconductor substrate is determined to be non-defective.

In the semiconductor device inspection method according to the present invention, the threshold value is 1.0 × 10 ¹⁵ / cm ³ in the above-described invention.

  The semiconductor device inspection method according to the present invention is characterized in that, in the above-described invention, the semiconductor device further includes a step of forming a semiconductor element as a product including a semiconductor region having the same conditions as the diode on the semiconductor substrate. To do.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor substrate according to the present invention is used for manufacturing a semiconductor element as a product, and a quality inspection is performed before the product is shipped. A semiconductor substrate made of silicon carbide having the following characteristics. The semiconductor substrate has a laminated structure in which an epitaxial growth layer made of silicon carbide is laminated on a semiconductor substrate made of silicon carbide. A diode is constituted by a part of the semiconductor substrate and the epitaxial growth layer. The diode includes an anode electrode provided on a first main surface on the epitaxial growth layer side and a cathode electrode provided on a second main surface on the semiconductor substrate side. A scratch is formed on the first main surface of the semiconductor substrate.

  In the semiconductor substrate according to the present invention, in the above-described invention, the anode electrode is provided with a window opening portion for exposing a part of the epitaxial growth layer. The scratch is formed in a portion of the epitaxial growth layer exposed at the window opening.

  According to the above-described invention, by observing the stacking fault that expands during the forward energization of the inspection element from the scratch on the semiconductor substrate, and calculating the expansion rate of the stacking fault, the forward energization of the inspection element The hole density of the epitaxially grown layer can be easily calculated. As a result, the hole density at the interface between the epitaxial growth layer and the semiconductor substrate (epi / substrate interface) can be calculated. Based on the hole density at the epi / substrate interface, It can be determined whether or not a stacking fault occurs.

  According to the semiconductor device inspection method and the semiconductor substrate according to the present invention, it is possible to perform an energization test without applying an overload under the maximum conditions in the product design specification range.

It is sectional drawing which shows an example of the cross-sectional structure of the test object in the inspection method of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the cross-sectional structure of the test object in the inspection method of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the cross-sectional structure of the test object in the inspection method of the semiconductor device concerning embodiment. 3 is a flowchart showing an outline of a semiconductor device inspection method according to an embodiment; It is a top view which shows the state which observed the silicon carbide base | substrate from the window opening part of the element for a test | inspection. FIG. 6 is a characteristic diagram showing the relationship between the hole density of the n ⁻ type drift layer and the expansion rate of stacking faults when the reference pin diode is energized in the forward direction. It is a characteristic view showing the relationship between the p-type impurity concentration of the p-type layer of the reference pin diode and the defect expansion threshold hole density of the stacking fault from the epi / substrate interface during forward energization. It is a top view which shows the state of the stacking fault after completion | finish of the voltage application to the element for a test | inspection. It is a characteristic view which shows the relationship between the forward current of a general diode, and energization time. It is explanatory drawing which shows typically the expansion phenomenon of the stacking fault in the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device inspection method and a semiconductor substrate according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Also, in this specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment)
First, the structure of an inspection element used in the semiconductor device inspection method according to the embodiment will be described. 1 to 3 are cross-sectional views illustrating an example of a cross-sectional structure of an inspection element used in the semiconductor device inspection method according to the embodiment. An inspection element (hereinafter referred to as an inspection element) used in the semiconductor device inspection method according to the embodiment is formed on the same silicon carbide (SiC) substrate 12 as a semiconductor element (not shown) as a product. As shown in FIGS. 1 to 3, first to third element structures 10 a to 10 c including a bipolar operation can be assumed as inspection elements.

Silicon carbide substrate 12 is a semiconductor wafer obtained by epitaxially growing a silicon carbide layer (hereinafter referred to as a silicon carbide epitaxial growth layer) 11 on a semiconductor substrate (hereinafter referred to as an n ⁺ -type silicon carbide substrate) 1 made of silicon carbide, or This is a semiconductor chip obtained by dividing the semiconductor wafer. Specifically, the silicon carbide substrate 12 is formed on the front surface of the n ⁺ -type silicon carbide substrate 1 as the silicon carbide epitaxial growth layer 11 as an n-type buffer layer 2, an n ⁻ -type drift layer 3 and a p-type base layer. 4 are laminated in order.

Inside the p-type base layer 4, p ⁺ -type contact regions 5 are provided in a pattern corresponding to the first to third element structures 10a to 10c, for example, by ion implantation. A diode is constituted by a pn junction formed by the laminated structure of the silicon carbide substrate 12. Anode electrode 6 is provided on the front surface (surface on the p-type base layer 4 side) of silicon carbide substrate 12 and is in contact with p ⁺ -type contact region 5. Cathode electrode 7 is provided on the back surface of silicon carbide substrate 12 (the back surface of n ⁺ -type silicon carbide substrate 1).

  The anode electrode 6 and the cathode electrode 7 are electrode pads for inspection described later. The anode electrode 6 is provided with openings (hereinafter referred to as window opening portions) 21 having a predetermined pattern. The window opening portion 21 of the anode electrode 6 is a window for observing the expansion rate of stacking faults in the silicon carbide substrate 12 during inspection described later. The window opening portion 21 of the anode electrode 6 may have a configuration in which, for example, linear slits parallel to the <11-20> direction are arranged in a striped planar layout.

The first element structure 10a shown in FIG. 1 is a structure simulating a planar gate structure. In the first element structure 10a, a p ⁺ -type contact region 5 is selectively provided in the surface region of the p-type base layer 4 (portion on the substrate front surface side). In addition, for example, the p-type base layer 4 is partially inverted to n-type by ion implantation, and an n-type region 8a that penetrates the p-type base layer 4 in the depth direction and reaches the n ⁻ -type drift layer 3 is provided. N type region 8 a is arranged apart from p ⁺ type contact region 5. The p-type base layer 4 is divided into a plurality of parts by the n-type region 8a.

The second element structure 10b shown in FIG. 2 is a structure simulating a trench gate structure. In the second element structure 10 b, a p ⁺ type contact region 5 is selectively provided in the surface region of the p type base layer 4. In addition, a trench 8 b that penetrates the p-type base layer 4 in the depth direction and reaches the n ⁻ -type drift layer 3 is provided. Trench 8b is arranged apart from p ⁺ -type contact region 5. The p-type base layer 4 is divided into a plurality of parts by the trench 8b. Inside the trench 8b, only the insulating film 8c or a conductive film is buried via the insulating film 8c.

In the first and second element structures 10 a and 10 b, a diode is formed at a pn junction between the p-type base layer 4 and the n ⁻ -type drift layer 3. N ⁺ type source regions may not be provided in both the first and second element structures 10a and 10b. In the window opening portion 21 of the anode electrode 6 of the first element structure 10a, the portion of the p-type base layer 4 sandwiched between the n-type region 8a and the p ⁺ -type contact region 5 and the n-type region 8a are exposed. . In the window opening portion 21 of the anode electrode 6 of the second element structure 10b, the portion of the p-type base layer 4 sandwiched between the insulating film 8c and the p ⁺ -type contact region 5 and the insulating film 8c are exposed.

The third element structure 10c shown in FIG. 3 is a structure simulating a pin diode. In the third element structure 10 c, the p ⁺ type contact region 5 is uniformly provided in the surface region of the p type base layer 4. The p ⁺ -type contact region 5 is exposed at the window opening portion 21 of the anode electrode 6. Such an inspection element having any one of the first to third element structures 10a to 10c, the anode electrode 6 and the cathode electrode 7 is provided on the same silicon carbide substrate 12 as a semiconductor element to be a product. Although it is desirable that the semiconductor device is disposed apart from the semiconductor device, it may be manufactured separately using a substrate having the same quality as that of the product.

Next, a semiconductor device inspection method according to the embodiment will be described with reference to FIGS. FIG. 4 is a flowchart illustrating an outline of the semiconductor device inspection method according to the embodiment. FIG. 5 is a plan view showing a state in which the silicon carbide substrate is observed from the window opening portion of the inspection element. First, a silicon carbide substrate 12 (semiconductor wafer) is prepared in which each layer to be a silicon carbide epitaxial growth layer 11 is laminated in a predetermined laminated structure on the n ⁺ type silicon carbide substrate 1 described above to form a pn junction (FIGS. 1 to 1). 3).

  Next, inspection elements are formed at a plurality of locations in the silicon carbide substrate 12 by a general method (step S1). The inspection element includes any one of the first to third element structures 10 a to 10 c described above, the anode electrode 6, the window opening portion 21, and the cathode electrode 7. The element structure of the inspection element is an element structure corresponding to the element structure of a semiconductor element formed on the same silicon carbide substrate 12 and serving as a product. In addition, the inspection element may be formed in the same chip size as that of the semiconductor element to be a product, for example.

  Next, a portion of the silicon carbide substrate 12 exposed to the window opening portion 21 of the anode electrode 6 is scratched (step S2). Scratches are a concave portion generated by being pushed into the surface of the silicon carbide substrate 12, a chip generated by scratching, or the like. The conductivity type of the portion 31 (see FIG. 5) that damages the silicon carbide substrate 12 may be either n-type or p-type, but a p-type region capable of generating a strip-like stacking fault at a low current. It is preferable to scratch the surface. The equipment 22 (see FIGS. 1 to 3) used for scratching the surface of the silicon carbide substrate 12 can be variously changed. For example, the surface of the silicon carbide substrate 12 may be indented with an ultra-micro hardness measuring machine (Nano Indenter), or the surface of the silicon carbide substrate 12 may be scratched with a diamond pen. May be attached. As yet another method, the surface of the silicon carbide substrate 12 may be damaged by irradiating a laser.

Next, a positive voltage is applied to the anode electrode 6 of the testing element and a negative voltage is applied to the cathode electrode 7 under the conditions of the maximum current and the maximum temperature of the design specifications of the semiconductor element to be the product, and the p-type base layer The pn junction between 4 and the n ⁻ -type drift layer 3 is forward-biased. As a result, as shown in FIG. 5, a stacking fault 32 is generated starting from the portion 31 damaged in step S2, and the direction 33 is parallel to the front surface of the substrate and perpendicular to the <11-20> direction. Extend to The expansion phenomenon of the stacking fault 32 is observed from the window opening portion 21 of the anode electrode 6 (step S3).

  In step S3, for example, the detection element is caused to emit light by an electroluminescence (EL) method or the like, and the stacking fault 32 is observed by a camera or the like, for example. At this time, the length L of the expanded portion of the stacking fault 32 in the direction 33 perpendicular to the <11-20> direction and the time required for the stacking fault 32 to extend by the length L (hereinafter, energization time) Measure t. Reference numerals 34 and 35 are a start point and an end point of the expanded portion of the stacking fault 32, respectively.

  Next, the expansion speed v of the stacking fault 32 is calculated (step S4). The expansion speed v of the stacking fault 32 is expressed by the following equation (1). When a high stress is applied to the silicon carbide substrate 12, the stacking fault 32 moves under the influence of the stress, so that the expansion speed v of the stacking fault 32 is increased. For this reason, by detecting the stacking fault 32 in real time in step S3 or calculating the expansion speed v of the stacking fault 32 in step S4, it is detected that a high stress is accidentally applied to the silicon carbide substrate 12. can do.

  v = L / t (1)

Next, based on the calculation result of step S4, the hole density of the n ⁻ -type drift layer 3 when the test element is forwardly energized is calculated (step S5). A method for calculating the hole density of the n ⁻ -type drift layer 3 in step S5 will be described later. Next, based on the calculation result of step S5, the hole density of the interface (epi / substrate interface) 8 between the silicon carbide epitaxial growth layer 11 and the n ⁺ type silicon carbide substrate 1 at the time of forward energization of the inspection element is calculated. (Step S6). Specifically, the hole density at the epi / substrate interface 8 is a hole density within a range of 0.2 μm or less from the epi / substrate interface 8 in the n-type buffer layer 2.

  In addition, the lower limit value of the range of variation in hole density (hereinafter referred to as defect expansion threshold hole density) when a stacking fault 32 starts to occur from the epi / substrate interface 8 during forward energization of an inspection element that is not scratched. Is acquired in advance. Then, the quality of silicon carbide substrate 12 is inspected based on the lower limit value of the defect expansion threshold hole density at epi / substrate interface 8 and the calculation result in step S6 (step S7). Specifically, in step S7, the silicon carbide substrate 12 in which the calculation result in step S6 is less than the lower limit value of the defect expansion threshold hole density at the epi / substrate interface 8 is determined as a non-defective product. Thereby, the inspection of the semiconductor device according to the embodiment is completed.

Next, a method for calculating the hole density of the n ⁻ type drift layer 3 in step S5 described above will be described. FIG. 6 is a characteristic diagram showing the relationship between the hole density of the n ⁻ -type drift layer and the expansion rate of stacking faults when the reference pin diode is forwardly energized. First, a characteristic value based on the dependency between the hole density of the n ⁻ type drift layer and the expansion rate of stacking faults in the forward direction of a general pin diode (hereinafter referred to as a “reference pin diode”) as a reference in advance. get. The reference pin diode has a structure in which a p-type layer, an n ⁻ -type drift layer, and an n ⁺ -type layer are arranged in this order from the anode side to the cathode side.

Specifically, the forward current of the reference pin diode, expansion rate of the stacking faults, n ^- depends strongly on the hole density of the type drift layer, n ^- to increase with increasing hole density type drift layer Has been confirmed by the present inventors. For this reason, by using the inspection method of the semiconductor device according to the above-described embodiment, the hole density of the n ⁻ -type drift layer is changed variously, and the stacking fault expansion speed when the reference pin diode is forward-directed is measured. . The result is shown in FIG. Then, an approximate line 41 indicating the relationship between the hole density of the n ⁻ -type drift layer and the expansion rate of the stacking fault is obtained from the plurality of measurement points.

The hole density of the n ⁻ type drift layer of the reference pin diode is calculated by a general method from the operating temperature of the reference pin diode, the p type impurity concentration of the p type layer, the minority carrier lifetime of the n ⁻ type drift layer, and the like. do it. In FIG. 6, the operating temperature of the reference pin diode was variously changed in the range of 20 ° C. or higher and 150 ° C. or lower. In the p-type layer of the reference pin diode, the dopant was aluminum (Al), and the impurity concentration was variously changed within the range of 1.8 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁹ / cm ³ .

The p-type impurity concentration of the p-type layer of the reference pin diode can be obtained by general elemental analysis or the like. The lifetime of minority carriers in the n ⁻ -type drift layer can be measured by a general carrier lifetime measuring apparatus. From the results shown in FIG. 6, it can be seen that the stacking fault expansion rate depends on the approximate line 41 approximated by a quadratic function with respect to the hole density of the n ⁻ -type drift layer when the reference pin diode is forward energized. . The characteristics of the reference pin diode shown in FIG. 6 are also applied to the inspection element including the first to third element structures 10a to 10c. The reason is as follows.

The inventor has confirmed that the expansion rate of stacking faults does not depend on the impurity concentration of the p-type layer but strongly depends on the hole density of the n ⁻ -type drift layer. This is because the approximate line 41 in FIG. 6 does not depend on the arrangement of the p-type region formed inside the p-type layer or the impurity concentration, and can therefore be applied to an inspection element having the same diode structure as the reference pin diode. . The p-type base layer 4, the n ⁻ type drift layer 3 and the n ⁺ type silicon carbide substrate 1 of the testing element correspond to the p type layer, the n ⁻ type drift layer and the n ⁺ type layer of the reference pin diode, respectively.

That is, the hole density of the n ⁻ -type drift layer 3 when the inspection element is forwardly energized corresponds to the n ⁻ -type drift layer corresponding to the stacking fault extension speed v calculated in step S4 in the approximate line 41 of FIG. The hole density. Therefore, when the expansion speed v of the stacking fault 32 calculated in step S4 is the predetermined speed v1, the hole density p1 of the n ⁻ type drift layer corresponding to the predetermined speed v1 is acquired from the approximate line 41 of FIG. 6 prepared in advance. . The hole density p1 of the n ⁻ -type drift layer is the hole density of the n ⁻ -type drift layer 3 when the test element is energized in the forward direction.

Next, a method of calculating the lower limit value of the defect expansion threshold hole density at the epi / substrate interface 8 when the inspection element is forward-energized will be described. FIG. 7 is a characteristic diagram showing the relationship between the p-type impurity concentration of the p-type layer of the reference pin diode and the defect expansion threshold hole density of stacking faults from the epi / substrate interface during forward energization. First, using the semiconductor device inspection method according to the above-described embodiment, when a stacking fault occurs during forward energization of the reference pin diode (that is, after the stacking fault occurs, the stacking fault starts to expand). The hole density of the n ⁻ -type drift layer is calculated.

Since the reference pin diode does not include an n-type buffer layer, the hole density of the n ⁻ -type drift layer calculated here is the defect expansion threshold hole density at the epi / substrate interface when the reference pin diode is forwardly energized. The hole density of the n ⁻ -type drift layer may be calculated in the same manner as the characteristic diagram of FIG. FIG. 7 shows the result of calculating the defect expansion threshold hole density at the epi / substrate interface when the reference pin diode is forwardly energized while variously changing the impurity concentration conditions of the p-type layer. The configuration of the reference pin diode is the same as that of the reference pin diode used in the characteristic diagram of FIG.

As shown in FIG. 7, the defect expansion threshold hole density at the epi / substrate interface at the time of forward energization of the reference pin diode varies with a plurality of stacking faults generated in the same silicon carbide substrate 51 (range indicated by vertical lines). However, the lower limit value of the range of the variation 51 (hereinafter simply referred to as the lower limit value) is a substantially constant range (the range of the rectangular frame in FIG. 7) regardless of the temperature and the impurity concentration condition of the p-type layer. Inner) It was confirmed to be within 52. Specifically, the lower limit value of the defect expansion threshold hole density at the epi / substrate interface during forward energization of the reference pin diode is about 1.0 × 10 ¹⁵ / cm ³ . In FIG. 7, the operating temperature of the reference pin diode and the impurity concentration range of the p-type layer are the same as those in the characteristic diagram of FIG.

As described above, the lower limit value of the defect expansion threshold hole density at the epi / substrate interface during forward energization of the reference pin diode is constant regardless of the impurity concentration condition of the p-type layer. The present invention can also be applied to an inspection element having a structure. Further, the inspection element including the n-type buffer layer 2 can be assumed to have a structure in which the n-type impurity concentration of the n ⁻ -type drift layer is increased in the reference pin diode. Therefore, in step S7, the hole density of the n-type buffer layer 2 calculated in step S6 may be compared with the lower limit value of the defect expansion threshold hole density at the epi / substrate interface in FIG.

Specifically, from the results shown in FIG. 7, the lower limit value of the defect expansion threshold hole density at the epi / substrate interface 8 during forward energization of the inspection element is about 1.0 × 10 ¹⁵ / cm ³ . For this reason, if the hole density of the n-type buffer layer 2 calculated in step S6 is less than about 1.0 × 10 ¹⁵ / cm ³ , the silicon carbide substrate 12 is formed within the range of the design specifications of the semiconductor element to be the product. Stacking defects do not occur. For this reason, silicon carbide substrate 12 is determined to be a non-defective product in step S7. The hole density of the n-type buffer layer 2 is determined by a general method from the hole density of the n ⁻ -type drift layer 3, the n-type impurity concentration of the n-type buffer layer 2, the minority carrier lifetime of the n-type buffer layer 2, and the like. What is necessary is just to calculate.

When the inspection element does not include the n-type buffer layer 2 (not shown), the hole density of the epi / substrate interface 8 when the inspection element is forward-energized is the hole density of the n ⁻ type drift layer 3. is there. For this reason, the step S6 is omitted, and in step S7, the hole density of the n ⁻ -type drift layer 3 calculated in step S5 and the lower limit value of the defect expansion threshold hole density at the epi / substrate interface in FIG. Should be compared. That is, when the inspection element does not include the n-type buffer layer 2, if the hole density of the n ⁻ -type drift layer 3 calculated in step S5 is less than about 1.0 × 10 ¹⁵ / cm ³ , the silicon carbide substrate 12 is determined to be a non-defective product.

  When the inspection element is provided on the same silicon carbide substrate 12 as the product, the timing for performing the inspection method of the semiconductor device according to the above-described embodiment is after the semiconductor element to be the product is formed on the silicon carbide substrate 12. Is desirable. There are two reasons for this. The first is that the lifetime of silicon carbide epitaxial growth layer 11 varies due to heat treatment and ion implantation in the process of forming a semiconductor element as a product, and the amount of hole injection into silicon carbide epitaxial growth layer 11 may change from the initial value. It is. In order to correctly estimate the hole injection amount of a product, it is necessary to inspect after the formation of a semiconductor element as a product. The second reason is to estimate the influence of the stress applied to the silicon carbide substrate 12 in the process of forming a semiconductor element to be a product. It is known that an excessive stress is applied to the silicon carbide substrate 12 to change the extension rate of stacking faults. By utilizing this change in the extension rate, stacking faults are formed after the formation of a semiconductor element as a product. By examining the expansion speed, it is possible to detect whether or not a different stress is applied to a semiconductor element as a product.

In step S2, an inert element such as neon (Ne), argon (Ar), or krypton (Kr) is locally ion-implanted instead of scratching the silicon carbide substrate 12 with a nanoindenter or diamond pen. Thus, the surface of the silicon carbide substrate 12 may be damaged. In this case, an inert element may be locally ion-implanted before the anode electrode 6 is formed. In the ion implantation of the inert element, for example, the impurity concentration may be about 1 × 10 ¹⁴ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, and the implantation depth may be about 0.5 μm.

  Next, another example of the method for calculating the expansion speed of the stacking fault 32 in step S4 described above will be described. FIG. 8 is a plan view showing a state of stacking faults after the voltage application to the inspection element is completed. FIG. 9 is a characteristic diagram showing the relationship between the forward current of a general diode and the energization time. When it is difficult to form the window opening 21 in the anode electrode 6, in step S2, a scratch having a depth reaching the silicon carbide substrate 12 through the anode electrode 6 of the inspection element is made, for example, with a probe or the like. It suffices to energize the inspection element.

  Even when the surface of the silicon carbide substrate 12 is scratched through the anode electrode 6 in this way, the portion 36 damaged in step S2 is parallel to the front surface of the substrate and in the <11-20> direction. The strip-shaped stacking fault 37 can be expanded in the vertical direction 33. In this case, since the stacking fault 37 is covered with the anode electrode 6, it cannot be observed by light emission by electroluminescence. For this reason, after removing the anode electrode 6 of the inspection element, the stacking fault 37 is caused to emit light and observed by a PL imaging apparatus or the like.

  Then, as in step S3, the length L in the direction 33 perpendicular to the <11-20> direction of the expanded portion of the stacking fault 37 is obtained. The time (energization time) t required for the stacking fault 37 to extend by the length L is calculated based on the forward characteristics of the diode, and the change start of the forward voltage Vf to the inspection element (= energization time 0 s). ) Until the forward voltage Vf of the testing element reaches a substantially constant value Vf1 (see FIG. 9). Thereafter, the expansion speed of the stacking fault 37 is calculated based on the above equation (1).

As described above, the present inventor has found that the stacking fault extending from the scratch on the surface of the silicon carbide substrate strongly depends on the hole density of the n ⁻ type drift layer. For this reason, according to the embodiment, by observing the stacking fault that expands during the forward energization of the inspection element from the scratches on the surface of the silicon carbide substrate, and calculating the extension speed of the stacking fault, It is possible to easily calculate the hole density of the n ⁻ -type drift layer when the element is forwardly energized.

In the prior art, n ^- when calculating the hole density of the type drift layer, it must be calculated in consideration of the recombination of the impact of any activation rate and defects p base layer, n ^- hole density type drift layer It was difficult to get accurate values. On the other hand, according to the embodiment, as described above, the hole density of the n ⁻ type drift layer at the time of forward energization of the inspection element can be calculated easily and accurately, and the calculated n ⁻ type The hole density at the epi / substrate interface can be easily calculated using the hole density of the drift layer.

  During this screening test, a voltage based on the maximum current and maximum temperature conditions in the product design specification range is applied to the test element, and the product design specification range is based on the calculated hole density at the epi / substrate interface. A silicon carbide substrate in which no stacking fault occurs can be obtained. For this reason, an overload exceeding the design specification range is not applied during the screening test. Therefore, it is possible to prevent the yield from being lowered more than necessary. Moreover, since a stacking fault does not occur in the silicon carbide substrate during actual use of the product, the product life can be extended.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Further, the present invention is similarly established even when the conductivity type is reversed.

  As described above, the semiconductor device inspection method and the semiconductor substrate according to the present invention are useful for power conversion devices such as inverters, power supply devices such as various industrial machines, and power semiconductor devices used for automobile igniters. is there.

1 n ⁺ type silicon carbide substrate 2 n type buffer layer 3 n ⁻ type drift layer 4 p type base layer 5 p ⁺ type contact region 6 anode electrode 7 cathode electrode 8 epi / substrate interface 8a n type region 8b trench 8c insulating film 10a -10c Device structure 11 Silicon carbide epitaxial growth layer 12 Silicon carbide substrate 21 Opening portion of anode electrode 22 Equipment for scratching the surface of silicon carbide substrate 31, 36 Scratched portion of silicon carbide substrate 32, 37 Stacking fault 33 Carbonization Direction parallel to the front surface of the silicon substrate and perpendicular to the <11-20> direction 41 Approximate line Vf, Vf1 Forward voltage p1 Hole density v, v1 Stacking defect diffusion rate

Claims (13)

A method for inspecting a semiconductor device for inspecting the quality of a semiconductor substrate by applying a voltage to an electrode provided on a main surface of a semiconductor substrate made of silicon carbide,
The semiconductor substrate in which an epitaxial growth layer made of silicon carbide is laminated on a semiconductor substrate made of silicon carbide, the electrode disposed on the first main surface of the semiconductor substrate on the epitaxial growth layer side is an anode electrode, and the semiconductor substrate side A first step of forming a diode using the electrode disposed on the second main surface of the cathode as a cathode electrode;
A second step of scratching the first main surface of the semiconductor substrate;
A third step of causing the diode to flow in the forward direction to emit light, observing a stacking fault expanded from the scratched portion when the diode is energized in the forward direction, and calculating an extension rate of the stacking fault;
A fourth step of calculating a hole density at the interface between the epitaxial growth layer and the semiconductor substrate based on the calculation result of the third step;
A fifth step of determining whether or not the semiconductor substrate is a non-defective product based on the calculation result of the fourth step;
A method for inspecting a semiconductor device, comprising: In the first step, a window opening portion is formed by selectively removing the anode electrode to expose a part of the epitaxial growth layer;
In the second step, the scratch is made on a portion of the epitaxial growth layer exposed at the window opening,
2. The method for inspecting a semiconductor device according to claim 1, wherein, in the third step, an extension phenomenon of the stacking fault is observed from a portion of the epitaxial growth layer exposed at the window opening portion. In the second step, the scratch is made on the epitaxial growth layer through the anode electrode,
In the third step, the stacking fault is expanded from the scratched portion by energizing the diode in the forward direction, and then the anode electrode is removed, the diode is caused to emit light, and the stacking fault is observed. The method for inspecting a semiconductor device according to claim 1.   The semiconductor device inspection method according to claim 1, wherein, in the second step, the scratch is made by denting the epitaxial growth layer.   3. The semiconductor device inspection method according to claim 1, wherein, in the second step, the scratch is made by scratching the epitaxial growth layer.   3. The method for inspecting a semiconductor device according to claim 1, wherein, in the second step, the scratch is made by locally implanting an inert element into the epitaxial growth layer. 7. The ion implantation of the inert element is performed by setting an impurity concentration to 1 × 10 ¹⁴ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less and an implantation depth to 0.5 μm. Inspection method of semiconductor device. In the fourth step,
Obtaining in advance a characteristic equation indicating the relationship between the expansion rate of the stacking fault and the hole density of the epitaxial growth layer,
The hole density at the interface between the epitaxially grown layer of the diode and the semiconductor substrate is obtained based on the calculation result of the third step and the characteristic formula. The inspection method of the semiconductor device as described. In the fifth step,
Acquire in advance as a threshold the lower limit value of the hole density range of the epitaxial growth layer where the stacking fault occurs,
9. The method for inspecting a semiconductor device according to claim 1, wherein when the calculation result of the fourth step is less than the threshold value, the semiconductor substrate is determined to be a non-defective product. The semiconductor device inspection method according to claim 9, wherein the threshold value is 1.0 × 10 ¹⁵ / cm ³ .   The semiconductor device inspection according to claim 1, further comprising a step of forming a semiconductor element that is a product including a semiconductor region having the same conditions as the diode on the semiconductor substrate. Method. A semiconductor substrate made of silicon carbide, which is used for manufacturing a semiconductor element to be a product and subjected to a quality inspection before the product is shipped,
A laminated structure in which an epitaxial growth layer made of silicon carbide is laminated on a semiconductor substrate made of silicon carbide;
A diode comprising a part of the semiconductor substrate and the epitaxial growth layer and having an anode electrode provided on the first main surface on the epitaxial growth layer side and a cathode electrode provided on the second main surface on the semiconductor substrate side When,
Scratches formed on the first main surface;
A semiconductor substrate comprising: The anode electrode is provided with a window opening portion for exposing a part of the epitaxial growth layer,
The semiconductor substrate according to claim 12, wherein the scratch is formed in a portion of the epitaxial growth layer exposed at the window opening.

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