CN106847911B - 一种宽禁带iii-v cmos应变场效应晶体管 - Google Patents
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Abstract
本发明涉及半导体器件制造技术领域，具体涉及一种基于硅衬底的、结合了n沟道晶体管和p沟道晶体管的宽禁带III‑V CMOS应变场效应晶体管，采用MOCVD或MBE设备外延生长，由在硅衬底上依次外延生长的第一多层晶格应变缓冲层、GaSb沟道层、AlGaSb势垒层、GaSb帽层、第二多层晶格应变缓冲层、In0.53Ga0.47As沟道层、In0.52Al0.48As势垒层及In0.53Ga0.47As帽层构成。本发明可有效地提升p沟道晶体管迁移率，以改进III‑V中n沟道晶体管和p沟道晶体管迁移率巨大差别的问题，并提供高载流子速度与高驱动电流的宽禁带III‑V族晶体管通道，有效的改善晶体管等比例缩小过程中带来短沟道效应，降低功耗，克服摩尔定律，打破极限，维持半导体产业等比例缩小进程。
Description
技术领域
本发明属于半导体器件制造技术领域，具体涉及一种宽禁带III-V CMOS应变场效应晶体管。
背景技术
根据摩尔定律，“集成电路上可容纳的元器件的数目，约每隔18-24个月便会增加一倍，性能也将提升一倍”。大抵而言，若在相同面积的晶圆下生产同样规格的IC，随着制程技术的进步，每隔一年半，IC产出量就可增加一倍，换算为成本，即每隔一年半成本可降低五成，平均每年成本可降低三成多。就摩尔定律延伸，IC技术每隔一年半推进一个世代。国际上半导体厂商基本都遵循着该项定律。
但是，国际上最大的芯片制造厂商英特尔日前宣布将推迟旗下基于10纳米制造技术的Cannonlake芯片的发布时间，推迟至2017年下半年，而Cannonlake芯片原定的发布日期是2016年。英特尔公司首席执行官Brian Krzanich在电话会议上表示，“由于要用各类相关技术，而每一种技术都有其自身一系列的复杂性和难度，从14纳米到10纳米和从22纳米到14纳米不是一回事。如果想大规模生产，光刻技术会更加困难，而且，完成多样式步骤的数目会不断增加”。英特尔一直以来遵循每两年缩小晶体管体积的时间表，也就是俗称的“摩尔定律”，上述消息令时间表出现裂痕，究其原因是构造芯片变得越来越复杂，功耗越来越难以降低，而且各种短沟道效应难以克服。
因此，半导体技术虽然日益进步，但受制于物理定律，最小尺寸不可能过小，为延续半导体摩尔定律的有效性，采用新的物料来制作处理器晶体管已经刻不容缓。目前已经已有不少研究机构，透过为硅材料整合更高性能的材料，例如采用化合物半导体材料如InGaAs/InP(如砷化铟镓与磷化铟)等，形成所谓的宽禁带III-V沟道的晶体管，可增进p-type迁移率和提供高载流子速度与高驱动电流，这种新的化合物半导体可望超越硅材料本身性能，维持摩尔定律，实现持续等比例缩小。
但该项方案目前也遇到了不少问题，主要存在两方面的挑战，一方面，硅基材料和化合物半导体材料如GaAs/InP等之间存在大的晶格常数差，一直无法克服材料之间原子晶格难以匹配的难题；另一方面，通常Si基晶体管由P沟道晶体管和n沟道晶体管结合构成CMOS结构运用于大规模数字领域，而通常III-V如GaAs器件方面n沟道器件容易实现，而p沟道器件受限于掺杂工程和外延制程，同时p沟道的迁移率远低于n沟道，目前结合n-沟道和p-沟道的GaAs/InP晶体管由于两者迁移率相差太大，无法实现CMOS同样电路结构，极大的阻碍了GaAs/InP器件在数字电路领域的应用。
发明内容
本发明的目的在于提供一种宽禁带III-V CMOS应变场效应晶体管，该场效应晶体管可以很好地解决现有晶体管在等比例缩小过程中功耗难以降低、短沟道效应难以克服的问题。
为达到上述要求，本发明采取的技术方案是：提供一种宽禁带III-V CMOS应变场效应晶体管，一种宽禁带III-V CMOS应变场效应晶体管，包括P沟道晶体管和n沟道晶体管，P沟道晶体管为AlGaSb/GaSb HFET(异质结场效应晶体管)，n沟道晶体管为GaAs mHEMT(应变高电子迁移率晶体管)。P沟道晶体管在硅衬底上依次外延生长第一多层晶格应变缓冲层、GaSb沟道层及AlGaSb势垒层，AlGaSb势垒层上方生长第一GaSb帽层和第二GaSb帽层，所述GaSb沟道层与AlGaSb势垒层形成二维空穴气；所述第一GaSb帽层上形成有第一漏极，且AlGaSb势垒层上形成有第一栅极，第二GaSb帽层上形成有第一源极；n沟道晶体管在所述第二GaSb帽层上依次外延生长第二多层晶格应变缓冲层、In0.53Ga0.47As沟道层及In0.52Al0.48As势垒层，In0.52Al0.48As势垒层上方生长第一In0.53Ga0.47As帽层和第二In0.53Ga0.47As帽层，所述In0.53Ga0.47As沟道层与In0.52Al0.48As势垒层形成二维空穴气，且第一In0.53Ga0.47As帽层上形成有第二源极，In0.52Al0.48As势垒层上形成有第二栅极，第二In0.53Ga0.47As帽层上形成有第二漏极。其中n沟道晶体管的外延异质结由InAlAs/InGaAs构成，p沟道晶体管的外延异质结由AlGaSb/GaSb构成。
与现有技术相比，本发明具有以下优点：
(1)基于硅衬底、集成了n沟道晶体管和p沟道晶体管的宽禁带III-V CMOS应变场效应晶体管可有效改善晶体管等比例缩小过程中带来的短沟道效应，并能够降低功耗，实现半导体器件尺寸的持续等比例缩小；
(2)本发明中III-V CMOS晶体管采用了GaAs mHEMT作为n型器件，与常规采用GaAsHEMT作为n型器件的III-V COMS晶体管相比迁移率会更高，器件高频性能更加出色。
(3)AlGaSb势垒层采用p型掺杂形成，与GaSb沟道层之间形成二维空穴气，可有效提升P沟道晶体管的迁移率，以改进III-V中n沟道晶体管和p沟道晶体管迁移率差别巨大的问题；
(4)第一多层晶格应变缓冲层可用于吸收硅基衬底与后续外延层之间因为晶格失配产生的应力，过滤掉衬底产生的散射中心，避免产生晶格驰豫，有效克服了后续外延层与硅基衬底之间原子晶格难以匹配的问题；
(5)第二多层晶格应变缓冲层可用于吸收P沟道晶体管与后续n沟道晶体管外延层之间因为晶格失配产生的应力，避免产生晶格驰豫；
(6)第一多层晶格应变缓冲层和第二多层晶格应变缓冲层为多种材料构成的复合缓冲层结构，由于不同材料之间的能带差，形成多个量子阱结构，可有效地阻隔断硅衬底的缺陷向GaSb沟道层扩散，以及阻隔断第二In0.53Ga0.47As帽层的缺陷向In0.53Ga0.47As沟道层扩散。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，在这些附图中使用相同的参考标号来表示相同或相似的部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本发明的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，以下结合附图及具体实施例，对本申请作进一步地详细说明。为简单起见，以下描述中省略了本领域技术人员公知的某些技术特征。
如图1所示，本实施例提供一种宽禁带III-V CMOS应变场效应晶体管，采用MOCVD或MBE设备外延生长，包括P沟道晶体管和n沟道晶体管；P沟道晶体管在硅衬底上依次外延生长第一多层晶格应变缓冲层、GaSb沟道层及AlGaSb势垒层，AlGaSb势垒层上方生长第一GaSb帽层和第二GaSb帽层，所述GaSb沟道层与AlGaSb势垒层接触处大概5nm区域形成二维空穴气，如图1中下面一条虚线所示；所述第一GaSb帽层上形成有第一漏极，且AlGaSb势垒层上形成有第一栅极，第二GaSb帽层上形成有第一源极；n沟道晶体管在所述第二GaSb帽层上依次外延生长第二多层晶格应变缓冲层、In0.53Ga0.47As沟道层1及In0.52Al0.48As势垒层2，In0.52Al0.48As势垒层2上方生长第一In0.53Ga0.47As帽层3和第二In0.53Ga0.47As帽层4，所述In0.53Ga0.47As沟道层1与In0.52Al0.48As势垒层2接触处大概5nm区域形成二维空穴气，如图1中上面一条虚线所示；且第一In0.53Ga0.47As帽层3上形成有第二源极，In0.52Al0.48As势垒层2上形成有第二栅极，第二In0.53Ga0.47As帽层4上形成有第二漏极。
硅衬底为p型Si衬底，其材料为Si、SiC、GaN、蓝宝石或金刚石，主要作为支撑材料。
第一多层晶格应变缓冲层，可用于吸收硅衬底与后续外延层之间因为晶格失配产生的应力，不掺杂，厚度为800～1800nm，从下至上先低温生长GaAs缓冲层，再高温生长GaAs/AlGaAs超晶格缓冲层，再采用梯度结构生长GaAsySb1-y缓冲层，再生长GaSb/AlGaSb超晶格缓冲层；y的值从1逐步降为0；GaSb/AlGaSb超晶格缓冲层中Al含量小于30％。
GaSb沟道层不掺杂，厚度为50～100nm。
AlGaSb势垒层，用于和栅金属形成肖特基接触和提供GaSb沟道层的自由空穴；厚度为15～40nm，Al含量小于30％，采用p型掺杂，体掺杂材料为Be、C或Mg，掺杂剂量为1×1018cm-3～3×1018cm-3。
第一GaSb帽层和第二GaSb帽层，用以保护势垒层不被氧化，同时用以降低欧姆接触电阻率；厚度为15～40nm，采用p型掺杂，体掺杂材料为Be、C或Mg，掺杂剂量为5×1018cm-3～2×1019cm-3。
第二多层晶格应变缓冲层，用于吸收P型沟道结构与后续n型沟道结构外延层之间因为晶格失配产生的应力，避免产生晶格驰豫；不掺杂，厚度600～1500nm，从下至上先采用梯度结构生长GaAsySb1-y缓冲层，再生长In0.53Ga0.47As/InP超晶格缓冲层；y的值从0逐步升为0.42。
In0.53Ga0.47As沟道层不掺杂1，厚度为50～100nm。
In0.52Al0.48As势垒层2，用于和栅金属形成肖特基接触和提供In0.53Ga0.47As沟道层的自由空穴；厚度为15～40nm，采用n型掺杂，体掺杂Si的剂量为2×1018cm-3～6×1018cm-3。
第一In0.53Ga0.47As帽层3和第二In0.53Ga0.47As帽层4，用于为器件制备提供良好的欧姆接触；厚度为15～40nm，采用n型掺杂，体掺杂Si的剂量为5×1018cm-3～2×1019cm-3。
以上实施例仅表示本发明的几种实施方式，其描述较为具体和详细，但并不能理解为对本发明范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明保护范围。因此本发明的保护范围应该以权利要求为准。
Claims (9)
1.一种宽禁带III-V CMOS应变场效应晶体管，其特征在于，包括P沟道晶体管和n沟道晶体管；P沟道晶体管在硅衬底上依次外延生长第一多层晶格应变缓冲层、GaSb沟道层及AlGaSb势垒层，AlGaSb势垒层上方生长第一GaSb帽层和第二GaSb帽层，所述GaSb沟道层与AlGaSb势垒层形成二维空穴气；所述第一GaSb帽层上形成有第一漏极，且AlGaSb势垒层上形成有第一栅极，第二GaSb帽层上形成有第一源极；n沟道晶体管在所述第二GaSb帽层上依次外延生长第二多层晶格应变缓冲层、In0.53Ga0.47As沟道层及In0.52Al0.48As势垒层，In0.52Al0.48As势垒层上方生长第一In0.53Ga0.47As帽层和第二In0.53Ga0.47As帽层，所述In0.53Ga0.47As沟道层与In0.52Al0.48As势垒层形成二维空穴气，且第一In0.53Ga0.47As帽层上形成有第二源极，In0.52Al0.48As势垒层上形成有第二栅极，第二In0.53Ga0.47As帽层上形成有第二漏极；
所述第一多层晶格应变缓冲层不掺杂，厚度为800～1800nm，从下至上先低温生长GaAs缓冲层，再高温生长GaAs/AlGaAs超晶格缓冲层，再采用梯度结构生长GaAsySb1-y缓冲层，再生长GaSb/AlGaSb超晶格缓冲层；y的值从1逐步降为0；GaSb/AlGaSb超晶格缓冲层中Al含量小于30％。
2.根据权利要求1所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述硅衬底为p型Si衬底。
3.根据权利要求1所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述GaSb沟道层不掺杂，厚度为50～100nm。
4.根据权利要求1所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述AlGaSb势垒层厚度为15～40nm，Al含量小于30％，采用p型掺杂，体掺杂材料为Be、C或Mg，掺杂剂量为1×1018cm-3～3×1018cm-3。
5.根据权利要求1所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述第一GaSb帽层和第二GaSb帽层的厚度为15～40nm，采用p型掺杂，体掺杂材料为Be、C或Mg，掺杂剂量为5×1018cm-3～2×1019cm-3。
6.根据权利要求1所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述第二多层晶格应变缓冲层不掺杂，厚度600～1500nm，从下至上先采用梯度结构生长GaAsySb1-y缓冲层，再生长In0.53Ga0.47As/InP超晶格缓冲层；y的值从0逐步升为0.42。
7.根据权利要求3-6任一权项所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述In0.53Ga0.47As沟道层不掺杂，厚度为50～100nm。
8.根据权利要求3-6任一权项所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述In0.52Al0.48As势垒层的厚度为15～40nm，采用n型掺杂，体掺杂Si的剂量为2×1018cm-3～6×1018cm-3。
9.根据权利要求3-6任一权项所述的宽禁带III-V CMOS应变场效应晶体管，其特征在于，所述第一In0.53Ga0.47As帽层和第二In0.53Ga0.47As帽层的厚度为15～40nm，采用n型掺杂，体掺杂Si的剂量为5×1018cm-3～2×1019cm-3。
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