WO2021258765A1 - 一种半导体器件、制造方法及电子设备 - Google Patents

一种半导体器件、制造方法及电子设备 Download PDF

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WO2021258765A1
WO2021258765A1 PCT/CN2021/078575 CN2021078575W WO2021258765A1 WO 2021258765 A1 WO2021258765 A1 WO 2021258765A1 CN 2021078575 W CN2021078575 W CN 2021078575W WO 2021258765 A1 WO2021258765 A1 WO 2021258765A1
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semiconductor layer
type
region
electrode
layer
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PCT/CN2021/078575
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English (en)
French (fr)
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黎子兰
张树昕
陈卫宾
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广东致能科技有限公司
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Priority claimed from CN202011527315.3A external-priority patent/CN113838935A/zh
Application filed by 广东致能科技有限公司 filed Critical 广东致能科技有限公司
Priority to US17/436,009 priority Critical patent/US12100759B2/en
Priority to EP21761955.0A priority patent/EP3958295A4/en
Publication of WO2021258765A1 publication Critical patent/WO2021258765A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device, a manufacturing method, and an electronic device.
  • Group III nitride semiconductor is an important new semiconductor material, which mainly includes AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Utilizing the advantages of the III-nitride semiconductors with direct band gap, wide band gap, high breakdown electric field strength, etc., through optimized design of device structure and process, III-nitride semiconductors have great prospects in the field of power semiconductors.
  • the present disclosure aims to provide a semiconductor device, a manufacturing method, and an electronic device, which can, for example, avoid damage to the crystal structure, and can be easily achieved in the process, and can maintain good
  • the transport properties of the two-dimensional charge carrier gas are conducive to the improvement of device performance.
  • a semiconductor device which includes: a substrate; an interface for generating a two-dimensional charge carrier gas; a first electrode and a second electrode; and a first type of dopant atoms formed on the substrate.
  • the first semiconductor layer in the first semiconductor layer, a first region where dopant atoms of the first type are not electrically active and a second region where dopant atoms of the first type are electrically active are formed; the second The area includes a part coplanar with the first area.
  • the first region is a region co-doped with doping atoms of the first type and a doping atom of the second type
  • the second region is a region doped with doping atoms of the first type
  • the first area does not deplete the two-dimensional charge carrier gas at its corresponding interface
  • a sub-area in the second area substantially depletes the two-dimensional charge carrier gas at its corresponding interface.
  • the first region is N-type, weak P-type, high-resistance type, or insulating type as a whole; when the semiconductor device is HHMT, the first region The whole area is P-type, weak N-type, high-resistance type or insulation type.
  • the thickness of the first region is less than or equal to the thickness of the second region.
  • the first area at least corresponds to the area between the first electrode and the second electrode.
  • the projection range of a sub-region in the second region relative to the substrate is less than or equal to the projection range of the second electrode relative to the substrate; when the In the case of semiconductor device diodes, the projection range of a sub-region in the second region relative to the substrate is larger than the projection range of the second electrode relative to the substrate.
  • the second type dopant atoms are N-type or atoms capable of producing a deep energy level effect
  • the first type dopant atoms are P-type atoms
  • the second type dopant atoms are P-type or atoms capable of producing a deep energy level effect, and the first type dopant atoms are N-type.
  • the doping concentration of the second type doping atoms is greater than 10% of the doping concentration of the first type doping atoms.
  • the doping concentration of the second type of doping atoms is uniformly distributed or gradually decreased along the direction of the first electrode perpendicular to the substrate.
  • the N-type doping atom is silicon or germanium
  • the P-type doping atom is magnesium
  • the atom capable of producing a deep level effect is nitrogen, carbon, iron or argon
  • the P-type dopant atom is magnesium
  • the first area is continuous or discrete; or the shape of each section of the first area is regular or irregular.
  • the thickness of the first area is equal or unequal.
  • it further includes a second semiconductor layer formed on the first semiconductor layer, and the two-dimensional charge carrier gas is formed at the interface between the first semiconductor layer and the second semiconductor layer.
  • it further includes a third semiconductor layer formed on the first semiconductor layer, and the two-dimensional charge carrier gas is formed at the interface between the third semiconductor layer and the second semiconductor layer.
  • the doping concentration of the first type dopant atoms in the first semiconductor layer is set to be uniformly distributed, gradually increasing from the direction of the electrode perpendicular to the substrate, or from the direction of the electrode perpendicular to the substrate
  • the top is set in a way that the two ends are high and the middle is low.
  • a passivation layer is further provided on the second semiconductor layer.
  • the substrate further has a nucleation layer, a buffer layer or an insertion layer.
  • the first electrode is a cathode and the second electrode is an anode.
  • the first electrode is a source electrode or a drain electrode
  • the second electrode is a gate electrode
  • an integrated electrode is further included, and the body electrode is electrically connected or disconnected from the first electrode.
  • an integral electrode is further included, wherein the body electrode forms an ohmic contact with the first semiconductor layer.
  • a method for manufacturing a semiconductor device which includes: providing a substrate; forming an interface for generating a two-dimensional charge carrier gas; forming at least a first electrode and a second electrode; on the substrate A first semiconductor layer doped with doping atoms of the first type is formed, and a first region in the first semiconductor layer is doped with doping atoms of a second type so that the first region is doped with the first type
  • the atoms do not have electrical activity, and the first type dopant atoms in the second region where the second type dopant atoms are not doped in the first semiconductor layer have electrical activity.
  • the second type dopant atoms are N-type or atoms capable of producing a deep energy level effect
  • the first type dopant atoms are P-type atoms
  • the second type dopant atoms are P-type or atoms capable of producing a deep level effect
  • the first type dopant atoms are N-type.
  • the doping concentration of the second type doping atoms is greater than 10% of the doping concentration of the first type doping atoms.
  • the doping concentration of the second type of doping atoms is uniformly distributed or gradually decreased along the direction of the first electrode perpendicular to the substrate.
  • the N-type doping atom is silicon or germanium
  • the P-type doping atom is magnesium
  • the atom capable of producing a deep energy level is carbon, argon, iron, and nitrogen.
  • the first region does not deplete the two-dimensional charge carrier gas at its corresponding interface
  • a sub-region in the second region substantially depletes the two-dimensional charge carrier gas at its corresponding interface
  • the first region is formed at least in the first semiconductor layer corresponding to the region between the first electrode and the second electrode.
  • the method for forming the first region is to form a mask layer on the first semiconductor layer, lithographically etch the mask layer to form a pattern with openings, and then ion implant the second semiconductor layer.
  • Two types of doping atoms Two types of doping atoms.
  • the opening is selected from:
  • the first region is formed in a manner selected from:
  • Method 1 A second-type doped atom material layer is formed on the first semiconductor layer, and the material layer is lithographically etched to form a pattern with openings, and then the second-type dopant atoms are removed from the material by heat treatment. The layer diffuses into the first semiconductor layer.
  • Method 2 forming a mask layer with openings on the first semiconductor layer, and then forming a second-type doped atomic material layer on the mask layer, by peeling off the mask layer, leaving only the mask The second type dopant atom material layer at the opening, and then the second type dopant atom diffuses from the material layer into the first semiconductor layer through heat treatment.
  • the opening in mode one is selected from:
  • the opening in the second mode and the opening in the first mode are complementary patterns.
  • the openings are provided so that the first area is formed to include continuous or discrete, regular or irregular sub-areas, or a combination of the foregoing.
  • the depth of ion implantation or ion diffusion in each sub-region is less than or equal to the thickness of the first semiconductor layer, the implant dose between each sub-region, or the diffusion time is the same or different, or The above combination method.
  • the method further includes optionally forming a third semiconductor layer on the first semiconductor layer.
  • it further includes forming a second semiconductor layer on the first semiconductor layer or the third semiconductor layer so as to be at the interface between the first/second semiconductor layer or at the third/second semiconductor layer.
  • the two-dimensional charge carrier gas is formed at the interface between the semiconducting layers.
  • it further includes forming a first electrode, a second electrode and a third electrode; wherein the first electrode and the third electrode are in ohmic contact with the two-dimensional charge carrier, and the second electrode is in contact with the The second semiconductor layer or the first semiconductor layer forms a Schottky contact.
  • it further includes forming an insulating layer between the second electrode and the second semiconductor layer.
  • it further includes forming a passivation layer on the second semiconductor layer;
  • a nucleation layer, an insertion layer and/or a buffer layer are formed on the substrate.
  • it further includes forming a fourth electrode, and the fourth electrode is in ohmic contact with the first semiconductor layer.
  • the fourth electrode is electrically connected or not connected to the first electrode.
  • an electronic device including any of the above-mentioned semiconductor devices.
  • the solution of the present disclosure can at least help to achieve one of the following effects: avoiding damage to the crystal structure, and easy to achieve in the process, can also maintain better two-dimensional charge carrier gas transport properties, and achieve better thresholds
  • the stability of the voltage contributes to the electric field distribution of the device and achieves higher withstand voltage capability.
  • Figures 1-2 show schematic cross-sectional views according to embodiments of the present disclosure
  • FIGS 3-11 show schematic cross-sectional views according to embodiments of the present disclosure
  • Figures 12-15 show schematic cross-sectional views according to an embodiment of the present disclosure
  • Figures 16-17 show schematic cross-sectional views according to embodiments of the present disclosure
  • Figures 18-24 show schematic cross-sectional views according to an embodiment of the present disclosure
  • Figures 25-28 show schematic cross-sectional views according to an embodiment of the present disclosure.
  • the semiconductor device of the present disclosure may be a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device may be a group III nitride semiconductor device.
  • the III-nitride semiconductor device may include a transistor using Wurtzite III-nitride semiconductor material and a GaN diode including a GaN semiconductor material.
  • the transistor may be a GaN transistor containing a GaN semiconductor material.
  • the GaN transistor may be a normally-off transistor GaN-HEMT and/or GaN-HHMT.
  • the process of fabricating a III-nitride semiconductor normally closed device is generally achieved by fabricating a P-type nitride semiconductor gate electrode on the barrier layer. Due to the poor insulation performance of the barrier layer, it is easy to cause the appearance of a large gate current. At the same time, the distance between the gate electrode and the channel due to the barrier layer is relatively long, which is not conducive to obtaining a higher threshold voltage.
  • the present disclosure provides a III-nitride semiconductor normally closed device.
  • the existing defects are overcome and the beneficial technical effects as described above are achieved.
  • FIGS. 1-2 A semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 1-2, in which FIG. 1 shows the structure of the HEMT, and FIG. 2 shows the structure of the diode.
  • the semiconductor device may include a substrate 100, and the material of the substrate 100 may be selected according to actual needs.
  • the specific form of the substrate 100 is not limited in this embodiment.
  • the substrate 100 may be ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single crystal silicon, etc.; preferably, the substrate 100 may be Al2O3 of (0001) plane; more preferably The substrate 100 may be a (111)-plane silicon substrate 100.
  • a first semiconductor layer 201 formed on a first surface 1001 of a substrate 100 the first semiconductor layer 201 may have a first surface A and a second surface B, and the first semiconductor layer 201 may be P-GaN, for example,
  • the concentration of P-doping in the first semiconductor layer 201 may be uniform; or the concentration of doping in the first semiconductor layer 201 along the first surface A to the second surface B may be variable. . For example, it may be gradually increasing from the first surface A to the second surface B, or set in such a way that the doping concentration of the first surface A and the second surface B is higher and the intermediate concentration is lower.
  • the doping concentration of the P-type impurity may be set in the range of 1E+17/cm3-1E+20/cm3.
  • the second semiconductor layer 202 is formed on the first semiconductor layer 201.
  • the first semiconductor layer 201 may have a smaller band gap than the second semiconductor layer 202, and a two-dimensional charge carrier gas, such as 2DEG, is formed between the first semiconductor layer 201 and the second semiconductor layer 202.
  • the second semiconductor layer 202 may be an AlN, AlGaN, InAlGaN, InAlN layer, or the like.
  • a third semiconductor layer 203 can also be formed on the first semiconductor layer 201.
  • the third semiconductor layer 203 can be used as a channel layer to reduce the scattering effect caused by P-GaN or impurities. Improve the electron mobility of the channel.
  • a two-dimensional charge carrier gas, such as 2DEG, may be formed between the third semiconductor layer 203 and the second semiconductor layer 202, and the third semiconductor layer 203 may be an intrinsic or unintentionally doped GaN layer.
  • a source 301, a gate 302, and a drain 303 can be formed on the second semiconductor layer 202, and the drain, the source and the two-dimensional charge carrier gas can be formed Ohmic contact, the gate and the second semiconductor layer may form a Schottky contact, or the gate may form a MIS gate with the second insulating layer and the second semiconductor layer; or as shown in FIG.
  • a cathode 304 and an anode 305 are formed on the second semiconductor layer 202, the cathode may form an ohmic contact with the two-dimensional charge carrier gas, and the anode may form an ohmic contact with the first semiconductor layer or the second semiconductor layer. Tekey contact.
  • a nucleation layer 204 and or a buffer layer 205 can also be formed between the substrate 100 and the first semiconductor layer 201, wherein when there are both the nucleation layer and the buffer layer, the buffer layer It may be formed on the nucleation layer.
  • the buffer layer can slow down the strain of the first or third semiconductor layer subsequently formed above the buffer layer to prevent the formation of defects in the upper first or third semiconductor layer, and reduce the difference in lattice constant and thermal expansion coefficient, and reduce the anode Leakage current between the substrate and the substrate.
  • the material of the buffer layer may be one or more of semi-insulating GaN, AlN, AlGaN, InGaN, AlInN, and AlGaInN.
  • a first insulating layer 400 can also be formed on the second semiconductor layer 202.
  • the insulating layer 400 can be a passivation layer, which can make the device more stable.
  • the optional passivation layer material is SiO2, SiN, Al2O3, and the like.
  • a second insulating layer 401 can be formed between the gate electrode and the second semiconductor layer, and the material is SiO2, SiN, Al2O3, etc., to reduce gate leakage current.
  • the sub-region 2012' in the first semiconductor layer 201 can enable the interface formed by the second semiconductor layer and the first or third semiconductor layer to be due to the effect of the first semiconductor layer when no bias is applied. Depletion makes 2DEG not present at the interface, but 2DEG is present at the interface in the case of the positive bias.
  • the doping concentration of the P-type impurity may be 1E+17/cm3-1E+20/cm3, and the impurity may be magnesium atoms.
  • the upper and lower surfaces of the sub-region 2012' and the upper and lower surfaces of the sub-region 2011/2013 in the first semiconductor layer 201 may be coplanar or not.
  • the thickness of the sub-region 2012' may be 10 to 100 nm , Which can better improve the performance parameters of the device.
  • the first semiconductor layer 201 corresponding to the sub-region 2011 between the source and the gate, and in the first semiconductor layer 201 corresponding to the drain and The sub-region 2013 between the gates or as shown in FIG. 2 may also have doping and P in the first semiconductor layer 201 corresponding to the sub-region 2011 between the cathode and the anode.
  • -Different types of impurity atoms may be N-type atoms such as silicon or germanium, and the doping concentration of the N-type atoms such as silicon or germanium is such that the first semiconductor layer 201 has the N-doped atoms and all the N-type atoms.
  • the region 2011/2013 where the P-type atoms coexist has an N-type or weak P-type morphology as a whole.
  • the doping concentration of the N-type atoms such as silicon or germanium can be made to be substantially equal to the total doping concentration.
  • the P-type atom doping concentration is 10%.
  • the doping depth may be between 1 nanometer and 50 nanometers.
  • the doped impurities may be carbon, nitrogen, iron or argon atoms, and the doping concentration may be selected such that the first semiconductor layer 201 has a region 2011/where the dopant atoms and the P-type atoms coexist.
  • the overall impedance of 2013 is only ten times higher than the impedance of the first semiconductor layer 201 in the region 2012 where two different atoms do not coexist.
  • the doping concentration may be between 1 nanometer and 50 nanometers.
  • the area 2011 in the first semiconductor layer 201 in FIG. 1 that corresponds to the source electrode and the gate electrode may include an edge E1 corresponding to the gate electrode 302 that is close to the source electrode 301 to the corresponding The area from the source to the edge F1 of the gate, or the area 2011 in the first semiconductor layer 201 in FIG.
  • the region 2013 in the first semiconductor layer 201 that corresponds to the drain and the gate may start from the edge E2 that corresponds to the gate 302 close to the drain 303 to correspond to the drain
  • the range of the region far away from the edge F2 of the gate when the device is a HEMT, the length of the sub-region 2012' of the first semiconductor layer may be less than or equal to the size of the gate, preferably, the length may be 1/5 to 1/4 of the length between the first electrode and the third electrode.
  • the length of the sub-region 2012' of the first semiconductor layer may be greater than the size of the anode, preferably, The length can be 1 to 10 microns.
  • the width of the first semiconductor layer 201 having the coexistence region 2011/2013 of different doping atoms is adjustable.
  • the doping concentration of N-type atoms such as silicon or germanium may be uniformly distributed or uneven. For example, it gradually decreases along the direction in which the first electrode is perpendicular to the substrate, that is, the direction perpendicular to the second surface 2012 from the first surface 2011.
  • the doping depth of the N-type atoms such as silicon or germanium may be less than or equal to the thickness of the first semiconductor layer.
  • the regions 2011 and 2013 in FIG. 1 may be discrete or continuous, and the region 2011 in FIG. 2 may Is continuous.
  • the doping depth of impurity atoms in the region 2011 may be smaller than the doping depth of the impurity atoms in the region 2013, so as to further meet the requirements for a more uniform electric field distribution between the gate and drain, and the region 2011/2013 may be
  • the regular regions may also be irregular regions each, or any combination of the above, and the setting of the regions is also used to adapt to the uniform electric field requirements.
  • the P-type nitride layer will not deplete the two-dimensional charge carrier gas in the region 2011/2013, thereby maintaining better transport properties.
  • the sub-region 2012' in the first semiconductor layer 201 corresponds to the area of the gate or the anode, and the size of the sub-region 2012' can also be precisely controlled to achieve the previously described length dimension.
  • the existence of the region 2012' can make the interface formed by the first or third semiconductor layer and the second semiconductor layer can be at the interface due to the depletion of the first semiconductor layer when no bias is applied.
  • the semiconductor device is a HEMT/HHMT
  • the length of the region can be 2 to 4 microns; when the semiconductor device is a diode, the region can be 6 to 8 microns.
  • the above device structure can also grow an intrinsically or unintentionally doped GaN layer at the position of the first semiconductor layer, and the first semiconductor layer (P-GaN) layer is arranged on the second semiconductor layer , And the corresponding processing as described above is performed on the first semiconductor layer (P-GaN) layer.
  • the structure in which the first semiconductor layer (P-GaN) is placed under the second semiconductor layer and then the corresponding region is doped is compared to the structure where the first semiconductor (P-GaN) layer is placed Above the second semiconductor layer, as far as the structure of the corresponding area doping treatment is concerned, since the distance between the gate electrode and the first/third semiconductor layer is relatively short, the performance test shows that this setting method has more excellent performance. Performance, for example, is more conducive to obtaining a higher threshold voltage, and better process control, avoiding damage, etc. Therefore, in this embodiment, it is preferable to arrange the first semiconductor layer (P-GaN) under the second semiconductor layer and then perform the corresponding region doping treatment.
  • the first semiconductor layer is described as an example of P-GaN in the above device, those skilled in the art know that when the device is an HHMT, the first semiconductor layer can be Set to N-GaN, and make corresponding adaptive changes to the co-doping type existing in the sub-region 2011 and the sub-region 2013, so that the region 2011/2013 in the first semiconductor layer 201 where the doping atoms coexist appears as a whole If the form of P-type, weak N-type, high-resistance state or insulation state, other parts can be set according to the aforementioned HEMT method.
  • FIGS. 3-11 A manufacturing method for manufacturing a semiconductor device of an embodiment of the present disclosure will now be exemplarily described with reference to FIGS. 3-11. It should be understood that although the semiconductor device in this embodiment takes the HEMT and the diode as an example, it is only an exemplary description and is not a limitation on the type of the semiconductor device.
  • step 100 a substrate 100 is provided, and the selection of the material of the substrate 100 can refer to the relevant description in the embodiments of the present disclosure, which will not be repeated here.
  • the first semiconductor layer 201 may include a P-type nitride semiconductor, such as P-GaN.
  • the first semiconductor layer 201 is preferably formed by a material growth method.
  • the first semiconductor layer 201 can be formed by epitaxial growth, so that damage to the crystal structure caused by ion implantation can be avoided.
  • the doping mode of the first semiconductor layer can be as described in the embodiments of the present disclosure, and will not be repeated here.
  • Step 300 A mask layer 206 is formed on the first semiconductor layer 201, and then only the mask corresponding to the position of the subsequent gate region or anode region can be retained, and N-type impurities such as Si, Ge, or ion implantation can be performed. N, Ar, C, Fe and other atoms. As a result, the regions 2011/2013 in the first semiconductor layer that are not protected by the mask form an overall N-type, weak P-type morphology, or a shape that is higher than that of the first semiconductor layer protected by the mask. High resistance state or insulation state.
  • the corresponding mask, injection dose, time and other parameters can also be designed according to specific requirements, so that the region 2011 as a whole presents an N-type, a weak P-type, a high resistance or an insulating state.
  • the size, shape, depth, doping concentration, etc. of the region are all adjustable and controllable.
  • the mask can be removed, and the crystal lattice can be repaired by heat treatment to reduce the damage caused by ion implantation.
  • the region 2011/2013 that is not protected by the mask in the first semiconductor layer 201 exhibits an N-type, weak P-type morphology, or a more masked area 2011/2013 through ion implantation.
  • the region 2012 of the first semiconductor layer protected by the film is in a high resistance state or an insulated state.
  • the manufacturing method has simple process manufacturing and control, and prevents the P-GaN from being very close to the drain electrode, thereby causing the breakdown voltage of the device to drop sharply.
  • Step 400 forming the second semiconductor 202 on the processed first semiconductor layer 201, thereby forming a two-dimensional charge carrier gas at the interface between the second semiconductor layer and the first semiconductor layer.
  • a third semiconductor layer 203 may be epitaxially grown on the processed first semiconductor layer 201, and then the second semiconductor layer 202 may be formed.
  • Step 500 forming a passivation layer 400 on the second semiconductor layer 202.
  • Step 600 forming openings at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to form the source electrode 301 and the drain electrode 303 respectively, and forming openings at the corresponding positions of the passivation layer 400 to form openings in the corresponding positions of the passivation layer 400 and the second semiconductor layer 202
  • a gate 302 is formed on the second semiconductor layer 202, or openings are formed at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to form a cathode 304 and an anode 305, respectively.
  • a second insulating layer 401 is formed between the second semiconductor layer 202 and the gate 402.
  • a nucleation layer, a buffer layer, etc. may be formed on the substrate 100 first.
  • FIGS. 12-15 Another manufacturing method for manufacturing the semiconductor device of the embodiment of the present disclosure will now be exemplarily described with reference to FIGS. 12-15.
  • Step 300 deposit a material layer 207 containing N-type impurities to be diffused in the first semiconductor layer 201, for example, a silicon-containing material layer or a germanium-containing material layer, or an amorphous carbon or iron-containing material layer Material layer, etc. Then, the material layer 207 is lithographically etched to remove the material layer corresponding to the position where the gate region or the anode region is subsequently formed, and then heated so that the impurity material diffuses into the first semiconductor layer 201, and then the material layer is removed. Material layer 207.
  • a material layer 207 containing N-type impurities to be diffused in the first semiconductor layer 201 for example, a silicon-containing material layer or a germanium-containing material layer, or an amorphous carbon or iron-containing material layer Material layer, etc.
  • step 300 can also use a lift-off process: a mask layer with openings is formed on the first semiconductor layer 201, and a material layer of N-type impurities to be diffused is formed on the mask layer. 207, for example, a material layer containing silicon or a material layer containing germanium, or a material layer containing amorphous carbon or iron elements.
  • a mask layer with openings is formed on the first semiconductor layer 201, and a material layer of N-type impurities to be diffused is formed on the mask layer.
  • 207 for example, a material layer containing silicon or a material layer containing germanium, or a material layer containing amorphous carbon or iron elements.
  • the corresponding mask, dopant dose, time and other parameters can also be designed according to specific requirements, so that the whole area presents an N-type, a weak P-type, a high resistance or an insulating state.
  • the size, shape, depth, doping concentration, etc. are all adjustable and controllable.
  • the above-mentioned method of introducing impurities by diffusion method does not use ion implantation, its process realization and control are very simple, and compared with ion implantation, its production cost is lower, and there is no ion implantation. Damage is more conducive to the improvement of device performance.
  • FIGS. 16-17 A semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 16-17.
  • the difference between the embodiments of the present disclosure and the foregoing embodiments is that there is no region in the first semiconductor layer 201 where two different atoms coexist, that is, the region 2012 that retains the electrical activity of the P-type impurity, not only contains the region corresponding to the gate
  • the region of the pole or the anode also includes a subregion 2012" corresponding to the edge of the source electrode F1, or the edge of the cathode F1, which is far from the gate or the anode.
  • a body electrode 306 in ohmic contact with the first semiconductor layer is formed on the sub-region 2012". It should be noted that although the body electrode 306 is located on the sub-region 2012" in this embodiment, the The body electrode may also be located at other positions as long as it forms an ohmic contact with the first semiconductor layer.
  • the body electrode 306 may be physically connected to the source electrode, electrically connected, or not electrically connected to the source electrode.
  • a manufacturing method for manufacturing a semiconductor device of an embodiment of the present disclosure will now be exemplarily described with reference to FIGS. 18-24.
  • step 300 and step 600 The difference between the manufacturing method and the manufacturing method in the foregoing embodiment lies in step 300 and step 600, and the remaining steps are the same as the manufacturing method in the foregoing embodiment:
  • a material layer 207 containing impurities to be diffused may be deposited in the first semiconductor layer 201, for example, a silicon-containing material layer, a germanium-containing material layer, a carbon-containing material layer or an iron-containing material layer, etc. Then, the material layer 207 can be lithographically etched to remove the material layer corresponding to the position of the subsequent formation of the gate region or the anode region, and remove the position corresponding to the subsequent source or the cathode away from the gate or The material layer at the anode, that is, the material layer in the sub-region 2012" and the sub-region 2012' is removed, and then heated to diffuse the impurity material into the first semiconductor layer 201, and then the material layer is removed. Material layer 207.
  • step 300 can also use the similar steps of the stripping process described in the previous embodiment, by setting the mask opening, depositing the material layer 207; by stripping the mask layer, removing the area 2012" and the area 2012' The material layer, and then the second type dopant atoms diffuse from the material layer to the sub-region 2011/2013 in the first semiconductor layer through heat treatment.
  • the corresponding mask, dopant dose, time and other parameters can also be designed according to specific requirements, so that the whole area presents an N-type, a weak P-type, a high resistance or an insulating state.
  • the size, shape, depth, number, doping concentration, etc. are also adjustable and controllable.
  • openings may be formed in the corresponding positions of the passivation layer 400 and the second semiconductor layer 202, and then the source electrode 301, the drain electrode 303, and the body electrode 306 are formed respectively, and in the passivation layer 400
  • An opening is formed at the corresponding position of the second semiconductor layer, and then a gate 302 is formed on the second semiconductor layer, or an opening is formed at the corresponding position of the passivation layer 400 and the second semiconductor layer 202, thereby forming a cathode 304 and an anode 305, respectively. ⁇ 306 ⁇ And the body electrode 306.
  • FIGS. 25-28 A method of manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 25-28.
  • step 300 The difference between the embodiment of the present disclosure and the foregoing embodiment is step 300:
  • Step 300 A mask layer may be formed on the first semiconductor layer 201, and then the mask layer corresponding to the position of the gate region or the anode region to be formed later, and the position corresponding to the source electrode or the cathode electrode may be retained.
  • the mask layer 206 far away from the gate or the anode, that is, the region 2012" and the region 2012' are covered by the mask layer, ion implantation of N-type impurities such as Si, Ge, or ion implantation of N, Atoms such as Ar, C, Fe, etc., so that the first semiconductor layer that is not protected by the mask exhibits an N-type, weak P-type form as a whole, or exhibits a higher morphology than the first semiconductor layer protected by the mask.
  • a state in which the resistance of the layer is high or an insulating state.
  • the corresponding mask, injection dose, time and other parameters can also be designed according to specific needs, so that the overall size of the area showing N-type, weak P-type, high resistance or insulation state , Shape, depth, doping concentration, etc. are all adjustable and controllable.
  • the embodiments of the present disclosure also provide an electronic device, which may be a voltage stabilizer, a rectifier, an inverter, a charger, and so on.
  • the electronic device includes any one of the semiconductor devices in the foregoing embodiments, and the semiconductor device constitutes a basic constituent unit in the electronic device.
  • the embodiments of the present disclosure provide semiconductor devices, manufacturing methods, and electronic equipment. Because the semiconductor devices of the embodiments of the present disclosure do not require ion implantation, they can avoid damage to the crystal structure and can be easily achieved in process.
  • the device structure of the semiconductor device has better two-dimensional charge carrier gas transport properties, which is conducive to the improvement of device performance.

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Abstract

本公开内容提供一种半导体器件、制造方法及电子设备。所述半导体器件包括：基底；生成二维电荷载流子气的一界面；第一电极和第二电极；所述基底上形成的第一类型掺杂的第一半导体层，在所述第一半导体层中形成所述第一类型掺杂原子不具备电活性的第一区域和所述第一类型掺杂原子具备电活性的第二区域；所述第二区域中包含与所述第一区域共面的部分。所述半导体器件既能避免晶体结构的损伤，又能在工艺上容易实现，且能保持较好的二维电荷载流子气的输送性质，有利于器件性能的提升。

Description

一种半导体器件、制造方法及电子设备
相关申请的交叉引用
本公开要求于2020年06月24日提交中国专利局的申请号为202010590696.3、名称为“一种常关型器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
本公开要求于2020年12月22日提交中国专利局的申请号为202011527315.3、名称为“一种半导体器件、制造方法及其应用”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开内容涉及半导体技术领域，具体而言，涉及一种半导体器件、制造方法及电子设备。
背景技术
III族氮化物半导体是一种重要的新型半导体材料，主要包括AlN、GaN、InN及这些材料的化合物如AlGaN、InGaN、AlInGaN等。利用所述III族氮化物半导体具有直接带隙、宽禁带、高击穿电场强度等优点，通过器件结构与工艺的优化设计，III族氮化物半导体在功率半导体领域拥有巨大前景。
利用所述III族氮化物半导体的上述优点，通过器件结构与工艺的优化设计，来开发具有高功率、低导通电阻等高性能的半导体器件是期望的。
在现有的III族氮化物半导体器件中，大多是通过选区生长的方式来处理栅极或阳极附近的半导体层，进而实现期望的器件，然而上述工艺方法涉及到选区生长所产生的较大形貌，所以工艺的控制上也相对复杂。
发明内容
为了解决本领域已知存在的技术问题，本公开旨在提供一种半导体器件、制造方法及电子设备，例如能够实现避免晶体结构的损伤，又能在工艺上容易实现，且能保持较好的二维电荷载流子气的输送性质，有利于器件性能的提升。
在下文中将给出关于本公开内容的简要概述，以便提供关于本公开内容某些方面的基 本理解。应当理解，此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分，也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
根据本公开内容，提供了一种半导体器件，其包括：基底；生成二维电荷载流子气的一界面；第一电极和第二电极；所述基底上形成的包含第一类型掺杂原子的第一半导体层，在所述第一半导体层中形成第一类型掺杂原子不具备电活性的第一区域和所述第一类型掺杂原子具备电活性的第二区域；所述第二区域中包含与所述第一区域共面的部分。
可选地，其中所述第一区域为所述第一类型掺杂原子和第二类型掺杂原子共掺杂区域，所述第二区域为所述第一类型掺杂原子掺杂区域，且所述第一区域不耗尽其对应的界面处的二维电荷载流子气，所述第二区域中的一子区域基本耗尽其对应的界面处的二维电荷载流子气。
可选地，当所述半导体器件为HEMT或二极管时，所述第一区域整体为N-型、弱P-型、高阻型或绝缘型；当所述半导体器件为HHMT时，所述第一区域整体为P-型、弱N-型、高阻型或绝缘型。
可选地，其中所述第一区域的厚度小于或等于所述第二区域的厚度。
可选地，其中所述第一区域至少对应于所述第一电极和所述第二电极之间的区域。
可选地，其中当所述半导体器件为HEMT/HHMT时所述第二区域中一子区域相对所述基底的投影范围小于或等于所述第二电极相对所述基底的投影范围；当所述半导体器件二极管时，所述第二区域中一子区域相对基底的投影范围大于所述第二电极相对所述基底的投影范围。
可选地，其中所述第二类型掺杂原子为N-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为P-型原子；或者，
所述第二类型掺杂原子为P-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为N-型。
可选地，其中所述第二类型掺杂原子的掺杂浓度大于所述第一类型掺杂原子的掺杂浓度的10％。
可选地，其中所述的第二类型掺杂原子的掺杂浓度沿着第一电极垂直基底的方向均匀分布或逐渐递减。
可选地，其中所述N-型掺杂原子为硅或锗，其中所述P-型掺杂原子为镁。
可选地，其中所述能产生深能级效果的原子为氮、碳、铁或氩，所述P-型掺杂原子为镁。
可选地，其中所述第一区域是连续或分立；或者所述第一区域各剖面的形状规则或不 规则。
可选地，其中当所述第一区域为分立时，所述第一区域的厚度相等或不等。
可选地，其中还包括在所述第一半导体层上形成的第二半导体层，所述第一半导体层和所述第二半导体层之间的界面处形成所述二维电荷载流子气。
可选地，其中还包括在所述第一半导体层上形成的第三半导体层，所述第三半导体层和所述第二半导体层之间的界面处形成所述二维电荷载流子气。
可选地，其中所述第一半导体层中所述第一类型掺杂原子的掺杂浓度设置为：均匀分布、从所述电极垂直基底的方向逐渐递增、或者从所述电极垂直基底的方向上以两头高中间低的方式设置。
可选地，其中所述第二半导体层上还进一步具有一钝化层。
可选地，其中基底上还进一步具有成核层、缓冲层或插入层。
可选地，其中所述第一电极是阴极，所述第二电极是阳极。
可选地，其中所述第一电极是源极或漏极，所述第二电极是栅极。
可选地，其中还包括一体电极，所述体电极与所述第一电极电性连接或者无连接。
可选地，其中还包括一体电极，其中所述体电极与所述第一半导体层形成欧姆接触。
根据本公开内容，提供了一种半导体器件的制造方法，其包括：提供一基底；形成一产生二维电荷载流子气的界面；至少形成第一电极和第二电极；在所述基底上形成含有第一类型掺杂原子掺杂的第一半导体层，在所述第一半导体层中的第一区域掺杂第二类型掺杂原子使得所述第一区域中所述第一类型掺杂原子不具备电活性，所述第一半导体层中未进行所述第二类型掺杂原子掺杂的第二区域中的所述第一类型掺杂原子具备电活性。
可选地，其中所述第二类型掺杂原子为N-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为P-型原子；
或者，所述第二类型掺杂原子为P-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为N-型。
可选地，其中所述第二类型掺杂原子的掺杂浓度大于所述第一类型掺杂原子的掺杂浓度的10％。
可选地，其中所述的第二类型掺杂原子的掺杂浓度沿着第一电极垂直基底的方向均匀分布或逐渐递减。
可选地，其中所述N-型掺杂原子为硅或锗，所述P-型掺杂原子为镁，所述能产生深能级效果的原子为碳、氩、铁、氮。
可选地，其中所述第一区域不耗尽其对应的界面处的二维电荷载流子气，所述第二区域中的一子区域基本耗尽其对应的界面处的二维电荷载流子气。
可选地，其中至少在对应于第一电极到第二电极区域间的所述第一半导体层中形成所述第一区域。
可选地，其中所述第一区域的形成方式为在所述第一半导体层上形成一掩膜层，所述掩膜层上光刻刻蚀形成具有开口的图案，然后离子注入所述第二类型掺杂原子。
可选地，其中在所述开口选自：
遮挡对应于第二电极和远离第二电极方向的所述第一电极的附近的所述第一半导体层的上表面；
遮挡对应于第二电极的所述第一半导体层的上表面。
可选地，其中所述第一区域的形成方式选自：
方式一：在所述第一半导体层上形成一第二类型掺杂原子材料层，所述材料层上光刻刻蚀形成具有开口的图案，然后第二类型掺杂原子通过热处理从所述材料层中扩散到所述第一半导体层中。
方式二：在所述第一半导体层上形成一具有开口的掩膜层，然后在所述掩膜层上形成一第二类型掺杂原子材料层，通过剥离掩膜层，仅留下掩膜开口处的所述第二类型掺杂原子材料层，然后第二类型掺杂原子通过热处理从所述材料层中扩散到所述第一半导体层中。
可选地，其中方式一中所述开口选自：
露出对应于第二电极和远离第二电极方向的第一电极附近的所述第一半导体层的上表面；
露出对应于第二电极的所述第一半导体层的上表面；
其中所述方式二中的开口与所述方式一中的开口为互补图案的方式。
可选地，其中通过开口设置使得所述第一区域内形成为包括连续或分立、规则或不规则的子区域，或为上述组合方式。
可选地，所述各子区域中离子注入的深度或离子扩散的深度小于或等于所述第一半导体层的厚度、各子区域之间的注入剂量、或扩散的时间相同或不同，或者为上述组合方式。
可选地，还包括在所述第一半导体层上可选择地形成第三半导体层。
可选地，还包括在所述第一半导体层或第三半导体层上形成第二半导体层，从而在所述第一/第二半导体层之间的界面处或在所述第三/第二半导层之间的界面处形成所述二维电荷载流子气。
可选地，其中还包括形成第一电极、第二电极和第三电极；其中所述第一电极和第三电极与所述二维电荷载流子气欧姆接触，所述第二电极与所述第二半导体层或所述第一半导体层形成肖特基接触。
可选地，其中还包括在第二电极和所述第二半导体层之间形成一绝缘层。
可选地，其中还进一步包括在第二半导体层上形成一钝化层；或者
在所述基底上形成成核层、插入层和/或缓冲层。
可选地，其中还包括形成第四电极，所述第四电极与所述第一半导体层欧姆接触。
可选地，其中所述第四电极与所述第一电极电性连接或不连接。根据本公开内容，提供了一种电子设备，其包括上述任一项的半导体器件。
本公开内容的方案至少能有助于实现如下效果之一：避免晶体结构的损伤，且工艺上容易实现，还能保持较好的二维电荷载流子气的输送性质，实现更好的阈值电压的稳定性，有助于器件的电场分布，实现更高的耐压能力等。
附图说明
参照附图下面说明本公开内容的具体内容，这将有助于更加容易地理解本公开内容的以上和其他目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1-2示出了根据本公开实施方式的示意性剖视图；
图3-11示出了根据本公开实施方式的示意性剖视图；
图12-15示出了根据本公开实施方式的示意性剖视图；
图16-17示出了根据本公开实施方式的示意性剖视图；
图18-24示出了根据本公开实施方式的示意性剖视图；
图25-28示出了根据本公开实施方式的示意性剖视图。
具体实施方式
在下文中将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见，在说明书中并未描述实现本公开内容的所有特征。然而，应该了解，在开发任何实现本公开内容的过程中可以做出很多特定于本公开内容的决定，以便实现开发人员的具体目标，并且这些决定可能会随着本公开内容的不同而有所改变。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本公开内容，在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构，而省略了与本公开内容关系不大的其他细节。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本公开内容中，在可行的情况下，不同实施方案之间的特征可替换或借用、以及在一个实施方案中可省略一个或多个特征。
在以下具体实施方案中可参照附图，附图形成了本公开内容的一部分并例示了示例性 实施方案。此外，应理解的是，在不脱离所请求保护的主题的范围的情况下，可以利用其它实施方案并可以做出结构和/或逻辑改变。还应当指出，方向和参照(例如，上、下、顶部、底部、等等)仅用于帮助对附图中的特征的描述，并非在限制性意义上仅采用以下具体实施方案。
如在本公开内容的说明书和所附权利要求书中所使用的，除非上下文另外明确指示，单数形式“一”、“一个”和“所述”也包括复数形式。还将理解的是，如本文中所使用的术语“和/或”指代并包括相关联的列出的项中的一个或多个的任何和所有可能的组合。
具体地，本公开内容的半导体器件可以为包含氮化物半导体材料的化合物半导体器件，也称为氮化物半导体器件,其中所述氮化物半导体器件可以是III族氮化物半导体器件。可选地，所述III族氮化物半导体器件可以包括使用纤锌矿(Wurtzite)III族氮化物半导体材料的晶体管和包含GaN半导体材料的GaN二极管。可选地，所述晶体管可以是包含GaN半导体材料的GaN晶体管。特别的，所述GaN晶体管可以是常闭的晶体管GaN-HEMT和/或GaN-HHMT。
目前，制作III族氮化物半导体常闭型器件的工艺一般都是通过在势垒层上制作P-型氮化物半导体栅电极实现的。由于势垒层的绝缘性能较差，容易导致较大栅电流的出现。同时，栅电极由于势垒层的间隔与沟道的距离也相对较远，不利于获得较高的阈值电压。
有鉴于此，本公开提供了一种III族氮化物半导体常闭型器件，通过设计新的工艺流程方法，从而克服现有的缺陷，达到如前所述的有益的技术效果。
参照图1-2来描述根据本公开实施方式的半导体器件，其中图1中示出的是HEMT的结构，图2示出的是二极管的结构。
如图1-2所示，在本公开实施方式中，所述半导体器件，可以包括基底100，所述基底100的材质可以根据实际需要选取，本实施方案中并不限制基底100的具体形式。可选的，所述基底100可以是ZnO、SiC、AlN、GaAs、LiAlO、GaAlLiO、GaN、Al2O3或单晶硅等；优选的，所述基底100可以是(0001)面的Al2O3；更优选的，所述基底100可以是(111)面的硅基底100。
在基底100第一表面1001上形成的第一半导体层201，所述第一半导体层201可以具有第一表面A和第二表面B，所述第一半导体层201示例性可为P-GaN，可选地，所述第一半导体层201中P-掺杂的浓度可以为均匀的；或者所述第一半导体层201中沿着第一表面A至第二表面B方向的掺杂浓度可变。例如，可以是从第一表面A至第二表面B逐渐递增的，或者以第一表面A和第二表面B掺杂浓度较高并且中间浓度较低的方式设置。所述P-型杂质的掺杂浓度可设置在1E+17/cm3-1E+20/cm3的范围内。
在所述第一半导体层201上形成的第二半导体层202。第一半导体层201可以具有比第二半导体层202更小的禁带宽度，在第一半导体层201和第二半导体层202之间形成二维电荷载流子气，例如2DEG。可选的，所述第二半导体层202可以为AlN、AlGaN、InAlGaN、InAlN层等。
可以理解的是，还可以在所述第一半导体层201上形成第三半导体层203，所述第三半导体层203可以用作沟道层，可以减少P-GaN或杂质导致的散射效应，以提高沟道的电子迁移率。第三半导体层203和第二半导体层202之间可以形成二维电荷载流子气，例如2DEG，第三半导体层203可为本征或非故意掺杂的GaN层。
接着，如图1中所述可以在所述第二半导体层202上形成源极301、栅极302和漏极303,所述漏极、源极与所述二维电荷载流子气可以形成欧姆接触，所述栅极与所述第二半导体层可以形成肖特基接触，或栅极与第二绝缘层、第二半导体层形成MIS栅；或者如图2中所示可以在所述第二半导体层202上形成阴极304和阳极305，所述阴极与所述二维电荷载流子气可以形成欧姆接触，所述阳极与所述第一半导体层或所述第二半导体层可以形成肖特基接触。
可以理解的是，也可以在所述基底100和所述第一半导体层201之间形成一成核层204和或缓冲层205，其中当同时具有成核层和缓冲层时，所述缓冲层可以形成在所述成核层上。缓冲层可减缓后续形成于缓冲层上方的第一或第三半导体层的应变，以防止缺陷形成于上方的第一或第三半导体层中，以及减少晶格常数和热膨胀系数等差异，降低阳极与基底之间的漏电流。缓冲层的材料示例性的可为半绝缘GaN、AlN、AlGaN、InGaN、AlInN和AlGaInN中的一种或多种。
可以理解的是，还可以在所述第二半导体层202上形成一第一绝缘层400。所述绝缘层400可为钝化层，其可以使得器件更加稳定，可选的所述钝化层材料为SiO2、SiN、Al2O3等。如图1所示，还可以在位于栅电极与所述第二半导体层之间形成第二绝缘层401，其材料为SiO2、SiN、Al2O3等，以降低栅漏电流。
所述第一半导体层201中的子区域2012’可以使得所述第二半导体层与所述第一或第三半导体层构成的界面可以在不加偏压的时候由于所述第一半导体层的耗尽使得所述界面处不存在2DEG，但在所述正偏压的情况下所述界面处存在2DEG。示例性的，P-型杂质的掺杂浓度可以为1E+17/cm3-1E+20/cm3，所述杂质可为镁原子。其中所述子区域2012’的上下表面与第一半导体层201中的子区域2011/2013的上下表面可以共面或不共面，优选的，所述子区域2012’的厚度可以为10至100nm，其能更好提高器件的性能参数。
如图1中所示在所述第一半导体层201中对应于所述源极和所述栅极之间的子区域2011处、在所述第一半导体层201中对应于所述漏极和所述栅极之间的子区域2013处或 者如图2中所示在所述第一半导体层201中对应于所述阴极和所述阳极之间的子区域2011还可以存在有掺杂与P-型不同类型的杂质原子。所述掺杂的杂质原子可以为硅或锗等N-型原子，其中所述硅或锗等N-型原子的掺杂浓度使得第一半导体层201中具有所述N-掺杂原子和所述P-型原子共存的区域2011/2013整体呈现出N-型或弱P-型的形态即可，示例性的，可以使得所述硅或锗等N-型原子的掺杂浓度大等于所述P-型原子掺杂浓度的10％。示例性的，所述掺杂深度可以在1纳米至50纳米之间。
或者所述掺杂的杂质可以为碳、氮、铁或氩原子，其掺杂浓度可选择为使得第一半导体层201中具有所述掺杂原子和所述P-型原子共存的区域2011/2013整体呈现出阻抗比起第一半导体层201中没有两种不同原子共存区域2012的阻抗高十倍以上的形态即可。示例性的，所述掺杂浓度可以在1纳米至50纳米之间。
图1中所述第一半导体层201中对应于所述源极和所述栅极之间的区域2011处可以包括从对应于栅极302的靠近所述源极301的边缘E1起始到对应于所述源极远离栅极的边缘F1为止的区域范围，或者图2中所述第一半导体层201中对应于所述阴极和所述阳极之间的区域2011处可以包括对应于阴极靠近所述阳极的边缘E1’起始、到对应于所述阴极远离阳极的边缘F1’为止的、所述第一半导体层201中的区域范围。对应的，其中所述第一半导体层201中对应于所述漏极和栅极之间的区域2013可以从对应于栅极302靠近漏极303的边缘E2起始、到对应于所述漏极远离栅极的边缘F2为止的区域范围，当所述器件为HEMT时，其中所述第一半导体层的子区域2012’的长度可小于或等于所述栅极大小，优选地，该长度可以为第一电极和第三电极之间长度的1/5至1/4，当所述器件为二极管时，所述第一半导体层的子区域2012’的长度可大于所述阳极大小，优选的，该长度可以为1至10微米。
不难理解，所述第一半导体层201中具有所述不同掺杂原子共存区域2011/2013的宽度可调所述硅或锗等N-型原子的掺杂浓度可以是均匀分布的或者不均匀的，例如沿着所述第一电极垂直基底的方向，也即从所述第一表面2011垂直指向所述第二表面2012的方向逐渐递减的。所述硅或锗等N-型原子的掺杂深度可以小于或等于所述第一半导体层的厚度，图1中的区域2011和2013可以是分立的或连续的，图2中的区域2011可以是连续的。优选的，在区域2011中杂质原子的掺杂深度可以小于在区域2013的杂质原子的掺杂深度，以进一步满足栅漏之间的更均匀化的电场分布需求，所述区域2011/2013可以是规则的区域，也可以各自是不规则的区域，或者上述任意的组合形式，所述区域的设置同样用于适配均匀化的电场需求。
应当指出的是，所述区域2011/2013不会出现P型氮化物层对二维电荷载流子气的耗尽，从而保持了较好的输送性质。
第一半导体层201中的所述子区域2012’对应于所述栅极或所述阳极的区域，该子区 域2012’的尺寸也可以精确控制，进而实现先前所述的长度尺寸。该区域2012’的存在可以使得所述第一或第三半导体层与所述第二半导体层构成的界面可以在不加偏压的时候由于所述第一半导体层的耗尽使得所述界面处不存在2DEG，也就是说在该区域2012’，还保留了P-GaN的电活性。由于减少所述部分2012’的长度可以有效降低器件的导通电阻，也有利于缩小器件的尺寸、提高晶圆的面积利用率，但是也需指出太短的长度可能导致器件反偏时出现较大的漏电流。示例性的，当半导体器件为HEMT/HHMT时该区域的长度可以为2至4微米；当半导体器件为二极管时该区域可以为6至8微米。
上述器件结构也可以在所述第一半导体层的位置处生长本征或非故意掺杂的GaN层，而将所述第一半导体层(P-GaN)层设置在所述第二半导体层上，以及对所述第一半导体层(P-GaN)层进行如前所述的相应处理。
但应当指出，将所述第一半导体层(P-GaN)设置在所述第二半导体层下方再进行相应区域掺杂处理的结构，相对于将所述第一半导体(P-GaN)层设置在第二半导体层上方，在进行相应区域掺杂处理的结构而言，由于栅电极与所述第一/第三半导体层的距离相对较近，性能测试中表明此种设置方式有着更加优异的性能，例如更能有利于获得较高的阈值电压，以及工艺上更好控制，避免损伤等。因此本实施方式中优选将所述第一半导体层(P-GaN)设置在所述第二半导体层下方再进行相应区域掺杂处理的结构。
可以理解的是，上述器件中虽然对第一半导体层的设置是以P-GaN为例进行的说明，但本领域技术人员悉知，当所述器件为HHMT时，所述第一半导体层可设置为N-GaN，及对所述子区域2011和子区域2013存在的共掺杂类型进行对应的适应性更改，使得第一半导体层201中具有所述掺杂原子共存的区域2011/2013整体呈现出P-型、弱N-型的形态、高阻态或绝缘态，其它部分对照前述HEMT的方式对应设置即可。
现将参照图3-11来示例性描述用于制造本公开实施方式的半导体器件的制造方法。应理解，本实施方案中的半导体器件虽然以HEMT和二极管为例，但其仅为示例性说明，并不是对所述半导体器件类型的限制。
步骤100、提供一基底100，基底100材料的选取可以参见本公开实施方式中的相关描述，在此不再赘述。
步骤200、在基底100的第一表面上形成所述第一半导体层201，所述第一半导体层201可以包含P-型氮化物半导体，例如P-GaN。这里，优选以材料生长方法来形成第一半导体层201，例如可以采用外延生长的方式来形成所述第一半导体层201，如此可以避免离子注入方式导致的晶体结构的损伤。其中所述第一半导体层的掺杂模式可如本公开实施方式中的描述，在此不再赘述。
步骤300：在所述第一半导体层201上形成掩膜层206，然后可以仅保留对应于后续栅区域或者阳极区域位置处的掩膜，离子注入N-型杂质如Si、Ge，或者离子注入N、Ar、C、Fe等原子。从而使得未被掩膜保护的所述第一半导体层中的区域2011/2013形成整体呈现出N-型、弱P-型的形态或者呈现出比被掩膜保护的所述第一半导体层的阻值高的状态或绝缘态。
可以理解的是，还可以根据具体的需求进行设计相应的掩膜、注射剂量、时间等参数，使得所述区域2011整体呈现出N-型、弱P-型、阻值高或者绝缘状态。所述区域的大小、形状、深度、掺杂浓度等都可调可控。
然后可以去除掩膜，再通过热处理修复晶格，以降低离子注入带来的损伤。
在本实施方式中，通过离子注入的方法实现所述第一半导体层201中未被掩膜保护的区域2011/2013整体呈现出N-型、弱P-型的形态，或者呈现出比被掩膜保护的所述第一半导体层的区域2012阻值高的状态或绝缘态。本制造方法工艺制造、控制简单，避免了P-GaN非常靠近漏电极，从而导致器件的耐击穿电压急剧降低。
步骤400、在处理后的所述第一半导体层201上形成所述第二半导体202，从而在所述第二半导体层和所述第一半导体层的界面处形成二维电荷载流子气。应当理解的是，也可以在处理后的所述第一半导体层201上先外延生长一层第三半导体层203，再进而形成所述第二半导体层202。
步骤500、在所述第二半导体层202上形成一钝化层400。
步骤600、在所述钝化层400和所述第二半导体层202的相应位置形成开口进而分别形成所述源极301和漏极303和在所述钝化层400的相应位置形成开口进而在所述第二半导体层202上形成栅极302，或者在所述钝化层400和所述第二半导体层202的相应位置形成开口进而分别形成阴极304和阳极305。
步骤700、可选的，在所述第二半导体层202和栅极402之间形成第二绝缘层401。
可以理解的，在步骤200之前，可以先在基底100上先形成成核层、缓冲层等。
现将参照图12-15来示例性描述用于制造本公开实施方式的半导体器件的另一制造方法。
所述制造方法与前述制造方法的区别仅在于：
步骤300、在所述第一半导体层201中沉积含待扩散的N-型杂质的材料层207，例如，含硅的材料层或含锗的材料层，或者含非晶碳或含铁元素的材料层等。然后在所述材料层207上光刻刻蚀，去除对应于后续形成栅区域或者阳极区域位置的材料层，然后加热使得 所述杂质材料扩散到所述第一半导体层201内，然后去除所述材料层207。
可以理解的是，步骤300也可以采用剥离工艺：在所述第一半导体层201上形成一具有开口的掩膜层，然而在所述掩膜层上形成待扩散的N-型杂质的材料层207，例如，含硅的材料层或含锗的材料层，或者含非晶碳或含铁元素的材料层等。通过剥离掩膜层，仅留下掩膜开口处的所述第二类型掺杂原子材料层，然后第二类型掺杂原子通过热处理从所述材料层中扩散到所述第一半导体层中。
可以理解的是，还可以根据具体的需求进行设计相应的掩膜、掺杂剂量、时间等参数，使得所述整体呈现出N-型、弱P-型、阻值高或者绝缘状态的区域的大小、形状、深度、掺杂浓度等都可调可控。
可以理解的是，上述通过扩散方式引入杂质的方式，由于没有采用离子注入方式，其工艺的实现及控制都非常简单，且相比离子注入方式，其生产成本更低，且没有离子注入造成的损伤，更有利于器件性能的提升。
参照图16-17来描述根据本公开实施方式的半导体器件。
本公开实施方式与前述实施方式的区别在于，第一半导体层201中的没有两种不同原子共存的区域，也即保留了P型杂质电活性的区域2012，不仅仅包含了对应于所述栅极或所述阳极的区域，还包含了对应于所述源极的边缘处F1起、或所述阴极的边缘处F1起、远离所述栅极或所述阳极处的子区域2012”。
然后在所述子区域2012”上形成与所述第一半导体层欧姆接触的体电极306。应当指出的是，虽然本实施方式中所述体电极306位于所述子区域2012”上，但所述体电极也可以位于其它位置，只要其与所述第一半导体层形成欧姆接触即可。
所述体电极306可以与所述源电极物理连接、电性连接，或者与所述源电极不进行电性连接。
现将参照图18-24来示例性描述用于制造本公开实施方式的半导体器件的制造方法。
所述制造方法与前述实施方式中的制造方法的区别在于步骤300和步骤600，其余的步骤处理与前述实施方式中的制造方法相同：
步骤300、可以在所述第一半导体层201中沉积含待扩散杂质的材料层207，例如，含硅的材料层、含锗的材料层、含碳的材料层或含铁的材料层等。然后可以在所述材料层207上光刻刻蚀，去除对应于后续形成栅极区域或者阳极区域位置的材料层，以及去除对应于后续所述源极或所述阴极处远离所述栅极或所述阳极处的材料层，也就是使得子区域2012”和子区域2012’的所述材料层被去除，然后再加热使得所述杂质材料扩散到所述第一半导体 层201内，接着去除所述材料层207。
可以理解的是，步骤300也可以采用前述实施方式中所述的剥离工艺的类似的步骤，通过设置掩膜开口，沉积材料层207；通过剥离掩膜层，去除区域2012”和区域2012’的材料层，然后第二类型掺杂原子通过热处理、从所述材料层中扩散到所述第一半导体层中的子区域2011/2013。
可以理解的是，还可以根据具体的需求进行设计相应的掩膜、掺杂剂量、时间等参数，使得所述整体呈现出N-型、弱P-型、阻值高或者绝缘状态的区域的大小、形状、深度、数目、掺杂浓度等同样都可调可控。
步骤600、可以在所述钝化层400和所述第二半导体层202的相应位置形成开口，进而分别形成所述源极301、漏极303和体电极306，以及在所述钝化层400的相应位置形成开口，进而在所述第二半导体层上形成栅极302，或者在所述钝化层400和所述第二半导体层202的相应位置形成开口，进而分别形成阴极304、阳极305和体电极306。
参照图25-28来描述根据本公开实施方式的半导体器件的制造方法。
本公开实施方式与所述前述实施方式的区别在于步骤300:
步骤300：可以在所述第一半导体层201上形成掩膜层，然后保留对应于后续形成栅极区域或者阳极区域位置的掩膜层，以及保留对应于后续所述源极或所述阴极处远离所述栅极或所述阳极处的掩膜层206，也就是使得区域2012”和区域2012’被所述掩膜层覆盖，离子注入N-型杂质如Si、Ge，或者离子注入N、Ar、C、Fe等原子。从而使得未被掩膜保护的所述第一半导体层中整体呈现出N-型、弱P-型的形态或者呈现出比被掩膜保护的所述第一半导体层的阻值高的状态或绝缘态。
可以理解的是，还可以根据具体的需求进行设计相应的掩膜、注射剂量、时间等参数，使得所述整体呈现出N-型、弱P-型、阻值高或者绝缘状态的区域的大小、形状、深度、掺杂浓度等都可调可控。
本公开实施方式还提供一种电子设备，所述电子设备可以是稳压器、整流器、逆变器、充电器等等。所述电子设备包括上述实施方案中的任一种半导体器件，所述半导体器件构成了所述电子设备中的基本构成单元。
以上结合具体的实施方案对本公开内容进行了描述，但本领域技术人员应该清楚，这些描述都是示例性的，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据 本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。
工业实用性
本公开实施方式提供了半导体器件、制造方法及电子设备，由于本公开实施方式的半导体器件不需要离子注入因而能够实现避免晶体结构的损伤，又能在工艺上容易实现，并且本公开实施方式的半导体器件的器件结构具有较好的二维电荷载流子气的输送性质，这有利于器件性能的提升。

Claims (20)

  1. 一种半导体器件，包括：
    基底；
    生成二维电荷载流子气的一界面；
    第一电极和第二电极；
    所述基底上形成的包含第一类型掺杂原子的第一半导体层，在所述第一半导体层中形成所述第一类型掺杂原子不具备电活性的第一区域和所述第一类型掺杂原子具备电活性的第二区域；
    所述第二区域中包含与所述第一区域共面的部分。
  2. 根据权利要求1所述的半导体器件，其中所述第一区域为所述第一类型掺杂原子和第二类型掺杂原子共掺杂区域，所述第二区域为所述第一类型掺杂原子掺杂区域，且所述第一区域不耗尽其对应的界面处的二维电荷载流子气，所述第二区域中的一子区域基本耗尽其对应的界面处的二维电荷载流子气。
  3. 根据权利要求1或2所述的半导体器件，当所述半导体器件为HEMT或二极管时，所述第一区域整体为N-型、弱P-型、高阻型或绝缘型；当所述半导体器件为HHMT时，所述第一区域整体为P-型、弱N-型、高阻型或绝缘型。
  4. 根据权利要求1至3中任一项所述的半导体器件，其中当所述半导体器件为HEMT/HHMT时所述第二区域中一子区域相对所述基底的投影范围小于或等于所述第二电极相对所述基底的投影范围；当所述半导体器件二极管时，所述第二区域中一子区域相对基底的投影范围大于所述第二电极相对所述基底的投影范围。
  5. 根据权利要求2至4中任一项所述的半导体器件，其中所述第二类型掺杂原子为N-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为P-型原子；
    或者，所述第二类型掺杂原子为P-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为N-型。
  6. 根据权利要求1至5中任一项所述的半导体器件，其中还包括在所述第一半导体层上形成的第二半导体层，所述第一半导体层和所述第二半导体层之间的界面处形成所述二维电荷载流子气。
  7. 根据权利要求6所述的半导体器件，其中还包括在所述第一半导体层上形成的第三半导体层，所述第三半导体层和所述第二半导体层之间的界面处形成所述二维电荷载流子气。
  8. 根据权利要求1至7中任一项所述的半导体器件，其中还包括一体电极，所述 体电极与所述第一电极电性连接或者无连接。
  9. 根据权利要求1至8中任一项所述的半导体器件，其中还包括一体电极，其中所述体电极与所述第一半导体层形成欧姆接触。
  10. 根据权利要求1至9中任一项所述的半导体器件，其中当所述第一区域为分立时，所述第一区域的厚度相等或不等。
  11. 一种半导体器件的制造方法，其包括：
    提供一基底；
    形成一产生二维电荷载流子气的界面；
    至少形成第一电极和第二电极；
    在所述基底上形成含有第一类型掺杂原子掺杂的第一半导体层，在所述第一半导体层中的第一区域掺杂第二类型掺杂原子使得所述第一区域中所述第一类型掺杂原子不具备电活性，所述第一半导体层中未进行所述第二类型掺杂原子掺杂的第二区域中的所述第一类型掺杂原子具备电活性。
  12. 根据权利要求11所述的制造方法，其中所述第二类型掺杂原子为N-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为P-型原子；
    或者，所述第二类型掺杂原子为P-型或能产生深能级效果的原子，并且所述第一类型掺杂原子为N-型。
  13. 根据权利要求11或12所述的制造方法，还包括在所述第一半导体层上形成第三半导体层。
  14. 根据权利要求13所述的制造方法，还包括在所述第一半导体层或所述第三半导体层上形成第二半导体层，从而在所述第一半导体层与所述第二半导体层之间的界面处或在所述第三半导体层与所述第二半导体层之间的界面处形成所述二维电荷载流子气。
  15. 根据权利要求14所述的制造方法，其中还包括形成第三电极；所述第一电极和所述第三电极与所述二维电荷载流子气欧姆接触，所述第二电极与所述第二半导体层或所述第一半导体层形成肖特基接触。
  16. 根据权利要求14或15所述的制造方法，其中还包括在所述第二电极和所述第二半导体层之间形成一绝缘层。
  17. 根据权利要求14至16中任一项所述的制造方法，其中还包括在所述第二半导体层上形成一钝化层；
    或者，在所述基底上形成成核层、缓冲层和/或插入层。
  18. 根据权利要求11至17中任一项所述的制造方法，其中还包括形成第四电极，所述第四电极与所述第一半导体层欧姆接触。
  19. 根据权利要求18所述的制造方法，其中所述第四电极与所述第一电极电性连接或不连接。
  20. 一种电子设备，其包括权利要求1-19中任一项所述的半导体器件。
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