CN110224032B - 具有结型栅AlGaN/GaN异质结的横向晶体管及其制作方法 - Google Patents

具有结型栅AlGaN/GaN异质结的横向晶体管及其制作方法 Download PDF

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CN110224032B
CN110224032B CN201910440263.7A CN201910440263A CN110224032B CN 110224032 B CN110224032 B CN 110224032B CN 201910440263 A CN201910440263 A CN 201910440263A CN 110224032 B CN110224032 B CN 110224032B
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段宝兴
王彦东
孙李诚
杨银堂
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Abstract

本发明提出了一种具有结型栅AlGaN/GaN异质结的横向晶体管及其制作方法。该横向晶体管中,外延层对应于栅极下方的区域通过离子注入形成P型区;靠近漏极一侧的外延层表面还通过异质外延形成AlGaN层与漏极相接,形成AlGaN/GaN异质结;栅极为结型栅,源极和漏极为欧姆接触。AlGaN/GaN异质结通过自发极化和压电极化效应在异质结界面处形成高密度二维电子气,从而使具有结型栅和AlGaN/GaN异质结的横向晶体管具有很低的导通电阻。氮化镓外延层与衬底之间的异质结优化了晶体管的纵向电场分布,提高了器件的击穿电压;同时,采用结型栅可以获得增强型器件。

Description

具有结型栅AlGaN/GaN异质结的横向晶体管及其制作方法
技术领域
本发明涉及功率半导体器件领域,具体涉及一种结型栅横向晶体管。
背景技术
宽禁带半导体材料本身具有的优越性质,电子漂移饱和速度高、介电常数小、导电性能好的特点,在功率器件领域应用中潜在的巨大前景。由于氮化物材料没有天然的衬底,需要依靠材料生长的方式实现单晶材料,在GaN材料的生长过程中,由于无法避免的N空位、Si杂质和O杂质的存在,即使不对GaN材料掺杂,GaN材料的n型掺杂浓度也会高度1016/cm-3,这个现象对GaN基材料电子器件的性能产生了严重影响。
JFET是电压控制的单极型器件,它具有开关速度快、输入阻抗高、高温特性好、制备工艺成熟等优点,已成为近年来发展很快的功率器件之一,并有广泛的应用。
目前,在结型栅横向晶体管中,随着漂移区的长度增加,导通电阻大幅增加,且电流密度仍然较小。
发明内容
本发明提出了一种具有结型栅AlGaN/GaN异质结的横向晶体管,突破了横向器件中随着漂移区长度增加导通电阻大幅增加的问题。
本发明的技术方案如下:
该具有结型栅AlGaN/GaN异质结的横向晶体管,包括:
半导体材料的衬底;
位于衬底上表面的GaN材料的外延层;
位于外延层表面的源极、漏极和栅极;
其中,所述外延层对应于栅极下方的区域通过离子注入形成P型区;靠近漏极一侧的外延层表面还通过异质外延形成AlGaN层与漏极相接,形成
AlGaN/GaN异质结;所述栅极为结型栅,源极和漏极为欧姆接触。
进一步的,衬底的掺杂浓度根据设计的击穿电压确定,典型值为
1×1015cm-3~1×1017cm-3
进一步的,外延层的掺杂浓度根据设计的击穿电压确定,典型值为
1×1015cm-3~1×1017cm-3
进一步的,P型区的掺杂浓度根据设计的击穿电压确定,典型值为
1×1016cm-3~1×1018cm-3
进一步的,所述AlGaN/GaN异质结的横向尺寸占整个器件长度的比例典型值为1/2~3/4。
进一步的,AlGaN/GaN异质结与P型区的间距为0~3μm。
进一步的,外延层的厚度根据设计的击穿电压确定,典型值为0.2μm~1.5μm;异质外延的AlGaN层的厚度为10~30nm。
进一步的,所述衬底的材料为氮化镓、碳化硅、蓝宝石或硅。
一种制作上述具有结型栅AlGaN/GaN异质结的横向晶体管的方法,包括以下步骤:
(1)取半导体材料制备衬底;
(2)在衬底上形成GaN材料的外延层;
(3)在外延层上通过异质外延形成AlGaN层;
(4)在指定区域刻除AlGaN层,在掩膜的保护下,通过离子注入形成P型区,在P型区表面形成栅极欧姆接触;
(5)在外延层左侧淀积金属,形成源极欧姆接触;在AlGaN层右侧淀积金属,形成漏极欧姆接触;
(6)器件表面淀积钝化层。
本发明技术方案的有益效果如下:
本发明将AlGaN/GaN异质结应用于器件的部分漂移区,氮化镓外延层与衬底之间的异质结优化了晶体管的纵向电场分布,提高了器件的击穿电压,提高了击穿电压。在器件导通时,结型栅使得沟道在于体内,具有良好的噪声性能,高电子迁移率的2DEG,大幅度降低了器件的导通损耗。
本发明在相同漂移区长度的情况下,具有更高的耐压和更低的导通损耗,且能获得增强型器件。
附图说明
图1是本发明的结构示意图。
其中,1-源极;2-栅极;3-P型区;4-外延层;5-AlGaN层;6-漏极;7-衬底;8-衬底电极。
具体实施方式
下面结合附图以N沟道结型栅和AlGaN/GaN异质结的横向晶体管为例介绍本发明。
如图1所示,本实施例的结构包括:
氮化镓材料的衬底;
氮化镓材料的外延层;
位于外延层表面的源极;
位于外延层表面的栅极;
位于外延层表面的漏极;
所述栅极为结型栅,外延层对应于栅极下方的区域通过离子注入形成P型区;漂移区由N型GaN与AlGaN/GaN异质结两部组成;AlGaN/GaN异质结的横向尺寸占整个器件长度的比例典型值为1/2~3/4;AlGaN/GaN异质结与P型区直接相接或者保持不超过3μm的距离。
衬底的掺杂浓度为1×1015cm-3~1×1017cm-3;外延层的掺杂浓度为1×1015cm-3~1×1017cm-3;P型区的掺杂浓度为1×1016cm-3~1×1018cm-3
外延层的厚度为0.2μm~1.5μm;异质外延的AlGaN层的厚度为10~30nm。
该器件的制备过程如下:
(1)取半导体材料作为衬底;
(2)在衬底上形成外延层;
(3)在外延层上通过异质外延形成AlGaN层;
(4)在指定区域刻除AlGaN层,在掩膜的保护下,通过离子注入形成P型区,在P型区的表面形成栅极欧姆接触;
(5)在外延层最左侧淀积金属,形成源极欧姆接触;在AlGaN层最右侧淀积金属,形成漏极欧姆接触;
(6)器件表面淀积钝化层,并刻蚀接触孔。
本发明中,AlGaN/GaN异质结通过自发极化和压电极化效应在异质结界面处形成高密度二维电子气(two dimensional electron gas,2DEG),二维电子气具有很高的迁移率,从而使具有结型栅和AlGaN/GaN异质结的横向晶体管具有很低的导通电阻。氮化镓外延层与衬底之间的异质结优化了晶体管的纵向电场分布,提高了器件的击穿电压;同时结型栅使得获得增强型器件。
经ISE TCAD仿真表明,本发明提出的新型器件的性能较之于传统宽禁带横向晶体管明显提升,当两种器件具有相等的击穿电压时,新型器件的导通电阻下降了30%以上。
本发明采用的半导体材料还可以是能形成二维电子气的其他半导体材料,如砷化镓等,基于同样的发明构思,也应视为属于本申请权利要求的保护范围。
本发明所述的横向晶体管当然也可以为P型沟道,其结构与N沟道横向晶体管等同,也应当视为属于本申请权利要求的保护范围,在此不再赘述。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换的方案也落入本发明的保护范围。

Claims (6)

1.具有结型栅AlGaN/GaN异质结的横向晶体管,包括:
半导体材料的衬底;
位于衬底上表面的GaN材料的外延层;
位于外延层表面的源极、漏极和栅极;
其特征在于:
所述外延层对应于栅极下方的区域通过离子注入形成P型区;所述外延层的掺杂浓度为1×1015cm-3~1×1017cm-3
靠近漏极一侧的外延层表面还通过异质外延形成AlGaN层与漏极相接,形成AlGaN/GaN异质结,应用于器件的部分漂移区,与P型区保持不超过3μm的距离;所述AlGaN/GaN异质结的横向尺寸占整个器件长度的比例为1/2~3/4;
所述栅极为结型栅,源极和漏极为欧姆接触。
2.根据权利要求1所述的具有结型栅AlGaN/GaN异质结的横向晶体管,其特征在于:所述衬底的掺杂浓度为1×1015cm-3~1×1017cm-3
3.根据权利要求1所述的具有结型栅AlGaN/GaN异质结的横向晶体管,其特征在于:所述P型区的掺杂浓度为1×1016cm-3~1×1018cm-3
4.根据权利要求1所述的具有结型栅AlGaN/GaN异质结的横向晶体管,其特征在于:所述外延层的厚度为0.2μm~1.5μm;异质外延的AlGaN层的厚度为10~30nm。
5.根据权利要求1所述的具有结型栅AlGaN/GaN异质结的横向晶体管,其特征在于:所述衬底的材料为氮化镓、碳化硅、蓝宝石或硅。
6.一种制作权利要求1所述的具有结型栅AlGaN/GaN异质结的横向晶体管的方法,包括以下步骤:
(1)取半导体材料制备衬底;
(2)在衬底上形成GaN材料的外延层;
(3)在外延层上通过异质外延形成AlGaN层;
(4)在指定区域刻除AlGaN层,在掩膜的保护下,通过离子注入形成P型区,在P型区表面形成栅极欧姆接触;
(5)在外延层左侧淀积金属,形成源极欧姆接触;在AlGaN层右侧淀积金属,形成漏极欧姆接触;
(6)器件表面淀积钝化层。
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CN106449747A (zh) * 2016-11-28 2017-02-22 电子科技大学 一种逆阻型氮化镓高电子迁移率晶体管
CN108110054A (zh) * 2017-12-22 2018-06-01 苏州闻颂智能科技有限公司 一种GaN基HEMT器件及其制备方法

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