CN106784069A - Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method - Google Patents
Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method Download PDFInfo
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- CN106784069A CN106784069A CN201510809853.4A CN201510809853A CN106784069A CN 106784069 A CN106784069 A CN 106784069A CN 201510809853 A CN201510809853 A CN 201510809853A CN 106784069 A CN106784069 A CN 106784069A
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- 230000003647 oxidation Effects 0.000 title claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 23
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000002156 mixing Methods 0.000 claims abstract description 20
- 239000002002 slurry Substances 0.000 claims abstract description 16
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 15
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 15
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 15
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 15
- 238000001035 drying Methods 0.000 claims abstract description 11
- 238000007639 printing Methods 0.000 claims abstract description 11
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 10
- 230000001603 reducing effect Effects 0.000 claims abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 7
- 239000011521 glass Substances 0.000 claims abstract description 6
- 235000008216 herbs Nutrition 0.000 claims abstract description 6
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 238000007650 screen-printing Methods 0.000 claims abstract description 6
- 210000002268 wool Anatomy 0.000 claims abstract description 6
- 239000000243 solution Substances 0.000 claims description 22
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 17
- 239000000203 mixture Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 10
- 239000011259 mixed solution Substances 0.000 claims description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 7
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 125000004429 atom Chemical group 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 125000004437 phosphorous atom Chemical group 0.000 claims description 5
- 238000007704 wet chemistry method Methods 0.000 claims description 5
- 238000005984 hydrogenation reaction Methods 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 230000008859 change Effects 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000006798 recombination Effects 0.000 abstract description 2
- 238000005215 recombination Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- -1 tetramethyl hydrogen Chemical compound 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
Interdigital formula back junction back contact battery production method is passivated the present invention relates to back surface tunnel oxidation, damage layer and the making herbs into wool of silicon chip is removed, then N is formed in front side of silicon wafer+Front-surface field, removes PSG layers of phosphorosilicate glass and carries out side insulation and polished backside, and ultra-thin tunnel oxidation layer SiO is grown at the back side of silicon chip2, re-form B doping and P doping to polysilicon layer constitute interdigital formula polysilicon layer, to silicon chip formed N+The surface deposition alundum (Al2O3) layer and hydrogenated amorphous silicon nitride passivated reflection reducing of front-surface field penetrate layer, the back side growth silicon dioxide layer of silicon chip；Correspond to the region printing Ag/Al slurries for mixing B using the back side of the method battery of silk-screen printing, Ag slurries are printed corresponding to the region for mixing P, then dried in drying oven.The present invention uses one layer of ultra-thin tunnel oxidation SiO2With one layer of interdigital formula phosphorus doping and boron doped silicon layer, greatly change the interface quality of silicon base, and can greatly reduce the metal-semiconductor surface recombination of back surface.
Description
Technical field
The present invention relates to a kind of preparation method of crystal silicon battery, more particularly, to a kind of passivation of back surface tunnel oxidation
Interdigital formula back junction back contact battery production method.
Background technology
Solar cell is existing using more product, and Chinese patent CN102800716A discloses one kind too
Positive energy battery and preparation method thereof.The substrate of solar cell has heavily doped region and lightly doped district.Anode and negative electrode
May be contained within the back side of substrate, therefore, can increase substrate it is positive enter light quantity.Anode and negative electrode and heavily doped region
Contact and form selective emitter structure, therefore with relatively low contact resistance.In addition, not light with electrode contact
Doped region has relatively low saturation current, therefore, the compound of electron-hole pair can be reduced, while can simultaneously increase right
In ultrared absorption.But this kind of solar cell is still present the problem that electrical property has much room for improvement.
The content of the invention
The purpose of the present invention is exactly that a kind of compatible biography is provided for the defect for overcoming above-mentioned prior art to exist
The back surface tunnel oxidation passivation that unit for electrical property parameters can be greatly lifted on the basis of system cell making process is interdigital
Formula back junction back contact battery production method.
The purpose of the present invention can be achieved through the following technical solutions：
Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method, using following steps：
(1) utilize silicon chip in KOH or NaOH aqueous slkalis and H2O2Removed in solution and damage layer, then used
TMAH and isopropanol constitute mixed solution and front making herbs into wool are carried out to silicon chip, and being formed has 1-4 μm
Pyramid matte；
(2) method for taking diffusion or ion implanting in front side of silicon wafer, forms N+Front-surface field；
(3) using HF solution PSG layers of phosphorosilicate glass of removal, HNO is used3Mixed solution with HF carries out side
Insulation and polished backside；
(4) it is ultra-thin in one layer of the back side growth of silicon chip using the method for wet chemistry or the method for dry method thermal oxide
Tunnel oxidation layer SiO2, then form B doping at the back side of silicon chip with the method for mask pattern and P doping be right
Polysilicon layer, the mode of doping takes diffusion, and ion implanting or PECVD technique control thickness 10~30
Nm, forms the polysilicon layer of interdigital formula；
(5) ald or PECVD technique is taken to form N to silicon chip+The surface deposit thickness of front-surface field
It is the alundum (Al2O3) layer of 20-30nm；
(6) PECVD or magnetron sputtering method growth thickness are used for the hydrogenation of 75-85nm is non-in front side of silicon wafer
Polycrystalline silicon nitride passivated reflection reducing penetrates layer；
(7) take the method for thermal oxide to grow a layer thickness at the back side of silicon chip to be used in the silicon dioxide layer of 2-5nm
In the polysilicon layer for being passivated interdigital formula；
(8) the region printing Ag/Al slurries for mixing B are corresponded to using the back side of the method battery of silk-screen printing, it is right
Ying Yu mixes the region printing Ag slurries of P, is then dried in drying oven, it is ensured that the two-sided of cell piece is all formed
Good contact.
Step takes fluosilicic acid H in (4)2SiO6Solution, concentration is 1.3-1.7M, and front side of silicon wafer is protected with mask
Shield is put into silicate fluoride solution after getting up, and the time according to deposition is come precise control SiO2The thickness of film layer, typically
The time that we within 2nm thickness control is 5-8 minutes.The polysilicon layer mixed B and mix P is to be based on
PECVD is with high-purity Si H4Formed by annealing at 900-1100 DEG C after being prepared at 500-600 DEG C for source of the gas.
It should be noted that：When B is mixed, the non-region for mixing B is blocked with mask, then remove mask, then will mix
The region of B stamps mask and carries out mixing P, thus overleaf forms the interdigital formula structure mixed B He mix P.
Tunnel oxidation layer SiO2Thickness be less than 2nm.Tunnel oxidation layer in addition to thickness requirement, the layer and silicon chip
Layer contact interface requirements it is higher, in microstructure from the point of view of be easily caused than more uniform and no significant defect etc. it is compound
Impurity.
B adulterate and P doping to polysilicon layer in characterized in that, P atoms contain in the polysilicon layer of P doping
Measure is 5 × 1018-1×1019cm-3, the content of B atoms is 1 × 10 in the polysilicon layer of B doping19-5×1019cm-3
It is 180-200 DEG C to control depositing temperature during step (5) deposition alundum (Al2O3) layer.
Control temperature for 350-400 DEG C when growth hydrogenated amorphous silicon nitride passivated reflection reducing is penetrated layer in step (6).
The temperature of drying is 200-300 DEG C in step (8).
Compared with prior art, the back-passivated mechanism of present invention substitution N-type back junction back contact crystal silicon cell,
Using one layer it is ultra-thin (<Tunnel oxidation SiO 2nm)2With one layer of interdigital formula phosphorus (P) doping and boron (B)
The silicon layer of doping, such structure can greatly change the interface quality of silicon base, and can greatly reduce back of the body table
The metal-semiconductor surface recombination in face.It is most clear advantage is that compatible traditional back contacts back of the body crystalline solid silicon electricity
Unit for electrical property parameters (Implied V can be greatly lifted on the basis of the manufacture craft of pondoc>710mV,Implied
FF>82%, efficiency eta>24%).
Due in interdigital formula P+Emitter junction and N+One layer is increased between the region of back surface field BSF and silicon base to surpass
Thin oxide layer (<2nm), this layer of increase of super thin oxide layer so that interface quality is greatly improved,
The open-circuit voltage Voc of cell piece can be greatly increased, can also increase fill factor, curve factor FF, technological feasibility is stronger,
The equipment and process compatible with existing producing line are easier, open-circuit voltage most importantly can be greatly lifted and be turned
Efficiency is changed, is a kind of product of low-cost high-efficiency monocrystalline silicon battery.
Brief description of the drawings
Fig. 1 is the structural representation for preparing battery.
In figure, 1- hydrogenated amorphous silicon nitride passivated reflection reducings penetrate layer, 2- alundum (Al2O3)s layer, 3-N+Front-surface field, 4-N
Type silicon chip, 5- tunnel oxidations SiO2Layer, 6-B doped polysilicon layers, 7-P doped polysilicon layers, 8- silica
Layer, 9-Ag/Al slurries, 10-Ag slurries.
Specific embodiment
The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.
Embodiment 1
Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method, using following steps：
(1) utilize silicon chip in KOH aqueous slkalis and H2O2Removed in solution and damage layer, then use tetramethyl hydrogen
Amine-oxides and isopropanol constitute mixed solution and front making herbs into wool are carried out to silicon chip, form the pyramid matte with 1 μm；
(2) method for taking diffusion or ion implanting in front side of silicon wafer, forms N+Front-surface field；
(3) using HF solution PSG layers of phosphorosilicate glass of removal, HNO is used3Mixed solution with HF carries out side
Insulation and polished backside；
(4) it is ultra-thin in one layer of the back side growth of silicon chip using the method for wet chemistry or the method for dry method thermal oxide
Tunnel oxidation layer SiO2, in the present embodiment, take fluosilicic acid H2SiO6Solution, concentration is 1.3M, by silicon chip
Front mask protection is put into silicate fluoride solution after getting up, and the time according to deposition is come precise control SiO2Film layer
Thickness, typically the time within 2nm thickness be 5 minutes, the SiO for obtaining2The boundary of film layer silicon wafer layer contact
Face require it is higher, in microstructure from the point of view of be easily caused compound impurity than more uniform and no significant defect etc..
The polysilicon layer mixed B and mix P is with high-purity Si H based on PECVD4For source of the gas is prepared at 500 DEG C
Formed by being annealed at 900 DEG C afterwards.It should be noted that：When B is mixed, the non-region for mixing B is hidden with mask
Gear, then removes mask, then will mix the region of B and stamp mask and carry out mixing P, thus overleaf forms and mixes
B and mix the interdigital formula structure of P, the content of thickness P atoms in 10nm, the polysilicon layer of P doping for 5 ×
1018cm-3, the content of B atoms is 1 × 10 in the polysilicon layer of B doping19cm-3。
(5) depositing temperature is controlled for 180 DEG C, takes ald or PECVD technique to form N to silicon chip+
The surface deposit thickness of front-surface field is the alundum (Al2O3) layer of 20nm；.
(6) control temperature for 350 DEG C, front side of silicon wafer use PECVD or magnetron sputtering method growth thickness for
The hydrogenated amorphous silicon nitride passivated reflection reducing of 75nm penetrates layer；
(7) take the method for thermal oxide to grow a layer thickness at the back side of silicon chip is used in the silicon dioxide layer of 2nm
It is passivated the polysilicon layer of interdigital formula；
(8) the region printing Ag/Al slurries for mixing B are corresponded to using the back side of the method battery of silk-screen printing, it is right
Ying Yu mixes the region printing Ag slurries of P, is then dried in drying oven, and the temperature of drying is 200 DEG C, really
Protect the two-sided of cell piece and all form good contact.
The back surface tunnel oxidation for preparing be passivated the structure of interdigital formula back junction back contact battery as shown in figure 1,
The upper surface plating of silicon chip 4 is provided with N+Front-surface field 3, alundum (Al2O3) layer 2 and hydrogenated amorphous silicon nitride passivation
Antireflection layer 1, lower surface is followed successively by tunnel oxidation SiO2Layer 5, B doped polysilicon layers 6, P DOPOS doped polycrystalline silicons
Layer 7, silicon dioxide layer 8, Ag/Al slurries 9 are printed corresponding to the region for mixing B, printed corresponding to the region for mixing P
Brush Ag slurries 10.
Embodiment 2
Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method, using following steps：
(1) utilize silicon chip in NaOH aqueous slkalis and H2O2Removed in solution and damage layer, then use tetramethyl
Ammonium hydroxide and isopropanol constitute mixed solution and front making herbs into wool are carried out to silicon chip, form the pyramid suede with 2 μm
Face；
(2) method for taking diffusion or ion implanting in front side of silicon wafer, forms N+Front-surface field；
(3) using HF solution PSG layers of phosphorosilicate glass of removal, HNO is used3Mixed solution with HF carries out side
Insulation and polished backside；
(4) it is ultra-thin in one layer of the back side growth of silicon chip using the method for wet chemistry or the method for dry method thermal oxide
Tunnel oxidation layer SiO2, in the present embodiment, take fluosilicic acid H2SiO6Solution, concentration is 1.5M, by silicon chip
Front mask protection is put into silicate fluoride solution after getting up, and the time according to deposition is come precise control SiO2Film layer
Thickness, the time that we typically within 2nm thickness control is 6 minutes.The SiO for obtaining2Film layer silicon chip
The interface requirements that is contacted with silicon wafer layer of layer are higher, in microstructure from the point of view of easily led than more uniform and no significant defect etc.
Cause compound impurity.
The polysilicon layer mixed B and mix P is with high-purity Si H based on PECVD4For source of the gas is prepared at 600 DEG C
Formed by being annealed at 1000 DEG C afterwards.It should be noted that：When B is mixed, the non-region for mixing B is hidden with mask
Gear, then removes mask, then will mix the region of B and stamp mask and carry out mixing P, thus overleaf forms and mixes
B and mix the interdigital formula structure of P, the content of thickness P atoms in 20nm, the polysilicon layer of P doping for 8 ×
1018cm-3, the content of B atoms is 3 × 10 in the polysilicon layer of B doping19cm-3。
(5) depositing temperature is controlled for 190 DEG C, takes ald or PECVD technique to form N to silicon chip+
The surface deposit thickness of front-surface field is the alundum (Al2O3) layer of 25nm；
(6) control temperature for 360 DEG C, front side of silicon wafer use PECVD or magnetron sputtering method growth thickness for
The hydrogenated amorphous silicon nitride passivated reflection reducing of 80nm penetrates layer；
(7) take the method for thermal oxide to grow a layer thickness at the back side of silicon chip is used in the silicon dioxide layer of 3nm
It is passivated the polysilicon layer of interdigital formula；
(8) the region printing Ag/Al slurries for mixing B are corresponded to using the back side of the method battery of silk-screen printing, it is right
Ying Yu mixes the region printing Ag slurries of P, is then dried in drying oven, and the temperature of drying is 240 DEG C, really
Protect the two-sided of cell piece and all form good contact.
Embodiment 3
Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method, using following steps：
(1) utilize silicon chip in KOH aqueous slkalis and H2O2Removed in solution and damage layer, then use tetramethyl hydrogen
Amine-oxides and isopropanol constitute mixed solution and front making herbs into wool are carried out to silicon chip, form the pyramid matte with 4 μm；
(2) method for taking diffusion or ion implanting in front side of silicon wafer, forms N+Front-surface field；
(3) using HF solution PSG layers of phosphorosilicate glass of removal, HNO is used3Mixed solution with HF carries out side
Insulation and polished backside；
(4) it is ultra-thin in one layer of the back side growth of silicon chip using the method for wet chemistry or the method for dry method thermal oxide
Tunnel oxidation layer SiO2, in the present embodiment, take fluosilicic acid H2SiO6Solution, concentration is 1.7M, by silicon chip
Front mask protection is put into silicate fluoride solution after getting up, and the time according to deposition is come precise control SiO2Film layer
Thickness, the time that we typically within 2nm thickness control is 8 minutes.The SiO for preparing2Film layer
The interface requirements contacted with silicon wafer layer are higher, in microstructure from the point of view of be easily caused than more uniform and no significant defect etc.
Compound impurity.
The polysilicon layer mixed B and mix P is with high-purity Si H based on PECVD4For source of the gas is prepared at 600 DEG C
Formed by being annealed at 1100 DEG C afterwards.It should be noted that：When B is mixed, the non-region for mixing B is hidden with mask
Gear, then removes mask, then will mix the region of B and stamp mask and carry out mixing P, thus overleaf forms and mixes
B and the interdigital formula structure for mixing P, thickness content of P atoms in 30nm, the polysilicon layer of P doping is 1
×1019cm-3, the content of B atoms is 5 × 10 in the polysilicon layer of B doping19cm-3。
(5) depositing temperature is controlled for 200 DEG C, takes ald or PECVD technique to form N to silicon chip+
The surface deposit thickness of front-surface field is the alundum (Al2O3) layer of 30nm；
(6) control temperature for 400 DEG C, front side of silicon wafer use PECVD or magnetron sputtering method growth thickness for
The hydrogenated amorphous silicon nitride passivated reflection reducing of 75-85nm penetrates layer；
(7) take the method for thermal oxide to grow a layer thickness at the back side of silicon chip is used in the silicon dioxide layer of 5nm
It is passivated the polysilicon layer of interdigital formula；
(8) the region printing Ag/Al slurries for mixing B are corresponded to using the back side of the method battery of silk-screen printing, it is right
Ying Yu mixes the region printing Ag slurries of P, is then dried in drying oven, and the temperature of drying is 300 DEG C, really
Protect the two-sided of cell piece and all form good contact.
The present invention is most clear advantage is that compatible traditional back contacts carry on the back the basis of crystalline solid silion cell manufacture craft
On can greatly lift unit for electrical property parameters, (Implied Voc>710mV,Implied FF>82%.From embodiment
The performance detection data of the battery prepared in 1-3 is it can be seen that the open-circuit voltage V of the batteryocIt is very high, filling
The factor it is very high (>80%), therefore, conversion efficiency Eff can reach more than 24%.
Voc=685 ± 2mV, Jsc=42.5 ± 0.4mA/cm2, FF=81.5 ± 0.5%, Eff=24.5 ± 0.5%.
Claims (8)
1. back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method, it is characterised in that the party
Method uses following steps：
(1) utilize silicon chip in KOH or NaOH aqueous slkalis and H2O2Removed in solution and damage layer, then used
TMAH and isopropanol constitute mixed solution and front making herbs into wool are carried out to silicon chip, and being formed has 1-4 μm
Pyramid matte；
(2) method for taking diffusion or ion implanting in front side of silicon wafer, forms N+Front-surface field；
(3) using HF solution PSG layers of phosphorosilicate glass of removal, HNO is used3Mixed solution with HF carries out side
Insulation and polished backside；
(4) it is ultra-thin in one layer of the back side growth of silicon chip using the method for wet chemistry or the method for dry method thermal oxide
Tunnel oxidation layer SiO2, then form B doping at the back side of silicon chip with the method for mask pattern and P doping be right
Polysilicon layer, the mode of doping takes diffusion, and ion implanting or PECVD technique control thickness 10~30
Nm, forms the polysilicon layer of interdigital formula；
(5) ald or PECVD technique is taken to form N to silicon chip+The surface deposit thickness of front-surface field
It is the alundum (Al2O3) layer of 20-30nm；
(6) PECVD or magnetron sputtering method growth thickness are used for the hydrogenation of 75-85nm is non-in front side of silicon wafer
Polycrystalline silicon nitride passivated reflection reducing penetrates layer；
(7) take the method for thermal oxide to grow a layer thickness at the back side of silicon chip to be used in the silicon dioxide layer of 2-5nm
In the polysilicon layer for being passivated interdigital formula；
(8) the region printing Ag/Al slurries for mixing B are corresponded to using the back side of the method battery of silk-screen printing, it is right
Ying Yu mixes the region printing Ag slurries of P, is then dried with drying oven, it is ensured that the two-sided of cell piece is all formed
Good contact.
2. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that be put into silicate fluoride solution after front side of silicon wafer mask protection is got up in step (4),
Time according to deposition is come precise control SiO2The thickness of film layer.
3. back surface tunnel oxidation according to claim 2 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that the concentration of described silicate fluoride solution is 1.3-1.7M, and silicon chip is deposited on into silicate fluoride solution
Middle 5-8min, controls SiO2The thickness of film layer is within 2nm.
4. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that the polysilicon layer that B is mixed in step (4) and P is mixed is with high-purity Si H based on PECVD4
Formed by being annealed at 900-1100 DEG C after being prepared at 500-600 DEG C for source of the gas, when B is mixed, mix B's by non-
Region mask is blocked, and then removes mask, then will be mixed the region of B and stamped mask and carry out mixing P, is thus existed
The back side is into the interdigital formula structure for mixing B He mix P.
5. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that the content of P atoms is 5 × 10 in the polysilicon layer of P doping18-1×1019cm-3, B mixes
The content of B atoms is 1 × 10 in miscellaneous polysilicon layer19-5×1019cm-3。
6. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that it is 180-200 DEG C to control depositing temperature during step (5) deposition alundum (Al2O3) layer.
7. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that control the temperature to be when growth hydrogenated amorphous silicon nitride passivated reflection reducing is penetrated layer in step (6)
350-400℃。
8. back surface tunnel oxidation according to claim 1 is passivated interdigital formula back junction back contact battery making side
Method, it is characterised in that the temperature of drying is 200-300 DEG C in step (8).
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