CN115224151A - Back surface structure manufacturing method, solar cell manufacturing method and solar cell - Google Patents

Back surface structure manufacturing method, solar cell manufacturing method and solar cell Download PDF

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CN115224151A
CN115224151A CN202110346659.2A CN202110346659A CN115224151A CN 115224151 A CN115224151 A CN 115224151A CN 202110346659 A CN202110346659 A CN 202110346659A CN 115224151 A CN115224151 A CN 115224151A
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boron
substrate
phosphorus
region
area
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解观超
盛健
张小明
林纲正
陈刚
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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Abstract

The invention is applicable to the technical field of solar cells and provides a back surface structure manufacturing method, a solar cell manufacturing method and a solar cell. The manufacturing method of the interdigital back structure with the tunneling layer comprises the following steps: manufacturing a tunneling layer on the surface of the substrate; depositing an amorphous silicon layer on the substrate with the tunneling layer; graphically printing boron slurry and phosphorus slurry on the amorphous silicon layer to form a boron slurry area and a phosphorus slurry area, wherein the boron slurry area and the phosphorus slurry area are crossed; processing the boron slurry area and the phosphorus slurry area to enable the amorphous silicon layer to be converted into a polycrystalline silicon layer, and enabling boron atoms in the boron slurry area and phosphorus atoms in the phosphorus slurry area to diffuse into the polycrystalline silicon layer to form a P-type area and an N-type area; and cleaning the surface of the substrate on which the P-type region and the N-type region are formed. Therefore, the performance and the manufacturing efficiency of the interdigital back structure can be improved.

Description

Back surface structure manufacturing method, solar cell manufacturing method and solar cell
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a manufacturing method of an interdigital back surface structure with a tunneling layer, a manufacturing method of a solar cell and the solar cell.
Background
In the existing solar cell manufacturing technology, when an interdigital back surface structure is manufactured, a tunneling layer (SiOx) is manufactured on a P-type substrate; depositing amorphous silicon on the P-type substrate, doping phosphorus when depositing the amorphous silicon, and changing the amorphous silicon into polycrystalline silicon after high-temperature treatment; removing part of the N + region according to the graphical design; and then injecting aluminum paste into the part where the N + region is removed, so that the region of the P-type substrate, which is in contact with the aluminum paste, becomes a P + region.
However, the potential energy of the P + region formed after the aluminum paste contacts the P-type substrate is poor, and minority carriers enter the P + region to cause a recombination phenomenon. Moreover, laser etching is required to remove part of the N + region, which is cumbersome and easily damages the silicon wafer. In addition, since the aluminum paste and the P-type substrate can form the P + region, the method can be applied to the P-type substrate only. This results in poor performance and manufacturing efficiency of the interdigital back structure.
Therefore, how to improve the performance and the manufacturing efficiency of the interdigital back structure becomes a problem to be solved urgently.
Disclosure of Invention
The invention provides a manufacturing method of an interdigital back structure with a tunneling layer, a manufacturing method of a solar cell and the solar cell, and aims to solve the problem of how to improve the performance and the manufacturing efficiency of the interdigital back structure.
In a first aspect, the manufacturing method of the interdigital back structure with the tunneling layer provided by the invention comprises the following steps:
manufacturing a tunneling layer on the surface of the substrate;
depositing an amorphous silicon layer on the substrate with the tunneling layer;
graphically printing boron slurry and phosphorus slurry on the amorphous silicon layer to form a boron slurry area and a phosphorus slurry area, wherein the boron slurry area and the phosphorus slurry area are crossed;
processing the boron slurry area and the phosphorus slurry area to enable the amorphous silicon layer to be converted into a polycrystalline silicon layer, and enabling boron atoms in the boron slurry area and phosphorus atoms in the phosphorus slurry area to diffuse into the polycrystalline silicon layer to form a P-type area and an N-type area;
and cleaning the surface of the substrate on which the P-type region and the N-type region are formed.
Optionally, the step of processing the boron slurry region and the phosphorus slurry region specifically includes:
and putting the substrate printed with the boron slurry area and the phosphorus slurry area into an environment with a preset temperature.
Optionally, the preset temperature is in the range of 700 ℃ to 1200 ℃, and the maintaining time is in the range of 20 to 180min.
Optionally, the step of processing the boron slurry region and the phosphorus slurry region specifically includes:
and emitting laser to the boron slurry area and the phosphorus slurry area respectively.
Optionally, in the step of emitting laser light to the boron paste region and the phosphorus paste region, respectively, the laser light is controlled to be blue light, green light or violet light, and the pulse width is nanosecond, picosecond or femtosecond.
Optionally, the step of processing the boron slurry region and the phosphorus slurry region specifically includes:
and carrying out ion bombardment on the boron slurry area and the phosphorus slurry area.
Optionally, a gap is provided between the boron slurry region and the phosphorus slurry region.
Optionally, the manufacturing method further comprises the following steps:
and drying the boron slurry area and the phosphorus slurry area on the substrate.
Optionally, the step of cleaning the surface of the substrate on which the P-type region and the N-type region are formed specifically includes:
and respectively cleaning the substrate with the P-type region and the N-type region in alkaline liquid medicine, hydrofluoric acid liquid medicine and hydrochloric acid liquid medicine.
In a second aspect, the present invention provides a method for fabricating a solar cell, including the steps of:
manufacturing a suede surface on the front side of the substrate;
the manufacturing method of any one of the interdigital back surface structures with the tunneling layer is used for manufacturing an interdigital back surface structure;
depositing a passivated antireflection film on the front surface and the back surface of the substrate respectively;
and manufacturing an electrode on the back of the substrate.
Optionally, after the step of depositing the passivated antireflection film on the front surface and the back surface of the substrate respectively, the method further includes:
and carrying out graphical grooving on the passivated antireflection film on the back surface of the substrate.
Optionally, before the step of depositing the passivated antireflection film on the front surface and the back surface of the substrate respectively, the method further includes:
and diffusing on the front surface of the substrate to form a doped layer.
Optionally, the passivated antireflection film comprises at least one of a SiNx film, an AlOx film, a SiOx film, a SiOxNy film and an amorphous silicon film.
In a third aspect, the present invention provides a solar cell manufactured by any one of the above methods for manufacturing a solar cell.
According to the interdigital back structure manufacturing method with the tunneling layer, the solar cell manufacturing method and the solar cell, the boron slurry and the phosphorus slurry are printed in a graphical mode, the boron slurry area and the phosphorus slurry area are processed, amorphous silicon is changed into polycrystalline silicon, and boron atoms and phosphorus atoms are diffused into the polycrystalline silicon. Thus, the potential of the P + region formed by boron slurry doping is better. And moreover, a tunneling layer is reserved below the interdigital back structure, so that the recombination phenomenon can be reduced. In addition, the steps are simpler because laser etching is not needed. In addition, the manufacturing method of the embodiment of the invention can be applied to a P-type substrate or an N-type substrate. Therefore, the performance and the manufacturing efficiency of the interdigital back structure can be improved.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for fabricating an interdigital back structure with a tunneling layer according to an embodiment of the present invention;
FIG. 2 is a schematic illustration of a boron paste region and a phosphorous paste region of a method of fabricating an interdigital back surface structure having a tunneling layer in accordance with an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a method for fabricating an interdigital back structure with a tunneling layer, in accordance with an embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a method for fabricating an interdigital back structure with a tunneling layer, in accordance with an embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating a method for fabricating an interdigital back structure with a tunneling layer, in accordance with an embodiment of the present invention;
fig. 6 is a schematic flow chart illustrating a method for fabricating an interdigital back structure with a tunneling layer, in accordance with an embodiment of the present invention;
FIG. 7 is a schematic flow chart of a method for fabricating a solar cell according to an embodiment of the present invention;
FIG. 8 is a schematic flow chart of a method for fabricating a solar cell according to an embodiment of the present invention;
fig. 9 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the invention;
fig. 10 is a schematic structural view of a solar cell according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a solar cell according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
The manufacturing method of the interdigital back structure in the prior art is low in efficiency and poor in performance of the interdigital back structure. According to the method for manufacturing the interdigital back structure with the tunneling layer, disclosed by the embodiment of the invention, the boron slurry and the phosphorus slurry are printed in a graphical mode, so that amorphous silicon is changed into polycrystalline silicon, and boron atoms and phosphorus atoms are diffused into the polycrystalline silicon, and the performance and the manufacturing efficiency of the interdigital back structure can be improved.
Referring to fig. 1, a method for fabricating an interdigital back structure with a tunneling layer according to an embodiment of the present invention includes the following steps:
step S12: manufacturing a tunneling layer on the surface of a substrate;
step S14: depositing an amorphous silicon layer on the substrate with the tunneling layer;
step S16: the method comprises the steps of graphically printing boron slurry and phosphorus slurry on an amorphous silicon layer to form a boron slurry area and a phosphorus slurry area, wherein the boron slurry area and the phosphorus slurry area are intersected;
step S18: processing the boron slurry area and the phosphorus slurry area to enable the amorphous silicon layer to be converted into a polycrystalline silicon layer, and enabling boron atoms in the boron slurry area and phosphorus atoms in the phosphorus slurry area to diffuse into the polycrystalline silicon layer to form a P-type area and an N-type area;
step S19: and cleaning the surface of the substrate on which the P-type region and the N-type region are formed.
According to the manufacturing method of the interdigital back structure with the tunneling layer, disclosed by the embodiment of the invention, the boron slurry and the phosphorus slurry are printed in a graphical mode, the boron slurry area and the phosphorus slurry area are processed, amorphous silicon is changed into polycrystalline silicon, and boron atoms and phosphorus atoms are diffused into the polycrystalline silicon. Thus, the potential of the P + region formed by doping of the boron paste is better. And moreover, the tunneling layer is reserved below the interdigital back structure, so that the recombination phenomenon can be reduced. In addition, the steps are simpler because laser etching is not needed. In addition, the manufacturing method of the embodiment of the invention can be applied to a P-type substrate or an N-type substrate. Therefore, the performance and the manufacturing efficiency of the interdigital back structure can be improved.
Specifically, in step S12 of the embodiment of the present invention, the tunneling layer includes a silicon oxide (SiOx) layer. The SiOx layer selectively transmits majority charge and minority charge, thereby reducing recombination, improving passivation effect and being beneficial to improving conversion efficiency of the battery. In other embodiments, the tunneling layer may comprise silicon nitride, silicon oxynitride. The particular structure of the tunneling layer is not limited herein.
Specifically, in step S14, an amorphous silicon layer may be deposited using a Physical Vapor Deposition (PVD) method or a Chemical Vapor Deposition (CVD) method. In this embodiment, a tubular PECVD apparatus can be used to inject SiH gas at 200 deg.C 4 And H 2 Growing intrinsic amorphous silicon, siH 4 And H 2 The gas flow ratio is 2.
Specifically, in step S16, "pattern printing" refers to screen designing a pattern and printing is performed according to the pattern. Further, techniques of printing include, but are not limited to, screen printing, ink jet printing, and 3D printing techniques. It will be appreciated that the printed pattern includes a primary and secondary grid, with positive and negative electrodes corresponding to the pattern design of the P + and N + regions on the back side of the POLO-IBC cell.
In this embodiment, screen printing may be used, in which one of the boron paste and the phosphorus paste is printed, and then dried, and then the other of the boron paste and the phosphorus paste is printed, and then dried.
Referring to fig. 2, in the present embodiment, a boron paste and a phosphorous paste are pattern-printed on an amorphous silicon layer 161, and a boron paste region 162 and a phosphorous paste region 163 are formed in parallel and alternately. Specifically, the boron paste region 162 and the phosphorus paste region 163 are parallel to each other, and one boron paste region 162 is spaced between two adjacent phosphorus paste regions 163.
It is understood that in other embodiments, the boron slurry region and the phosphorus slurry region may intersect in other manners, such as non-parallel and non-intersecting manners, and the specific intersection manner of the boron slurry region and the phosphorus slurry region is not limited herein.
Specifically, in step S18, the boron slurry region and the phosphorus slurry region may be processed separately, or the boron slurry region and the phosphorus slurry region may be processed simultaneously.
Specifically, in step S19, the substrate surface on which the P-type region and the N-type region are formed may be cleaned with a chemical solution. Further, the substrate surface on which the P-type region and the N-type region are formed may be rinsed or rinsed with a chemical solution. Thus, the excess residues such as boron slurry residue and phosphorus slurry residue, and borosilicate glass and phosphosilicate glass generated after high-temperature reaction can be removed.
Referring to fig. 3, optionally, step S18 specifically includes:
step S182: and placing the substrate printed with the boron slurry area and the phosphorus slurry area into an environment with preset temperature.
Thus, the boron slurry area and the phosphorus slurry area are processed through the preset temperature, the amorphous silicon layer is converted into a polycrystalline silicon layer, and the boron atoms in the boron slurry area and the phosphorus atoms in the phosphorus slurry area diffuse into the polycrystalline silicon layer to form a P-type area and an N-type area. Therefore, the diffusion movement of atoms at high temperature is utilized, the process is simpler, and the damage to the silicon wafer is smaller.
Optionally, the preset temperature is in the range of 700 ℃ to 1200 ℃, and the maintaining time is in the range of 20 to 180min. Thus, the diffusion effect is better.
Specifically, the predetermined temperature is, for example, 700 ℃, 720 ℃, 760 ℃, 810 ℃, 880 ℃, 925 ℃, 956 ℃, 1010 ℃, 1150 ℃, 1180 ℃ and 1200 ℃. The specific value of the preset temperature is not limited as long as the aforementioned range is satisfied.
Specifically, when the boron slurry region and the phosphorus slurry region are treated with the preset temperature, the preset temperature may be kept constant, and may also be made to fluctuate within a range of 700 ℃ to 1200 ℃.
Specifically, the maintaining time is, for example, 20min, 40min, 60min, 80min, 100min, 120min, 140min, 160min, 180min. The specific value of the holding time is not limited as long as the above range is satisfied.
In this embodiment, a silicon wafer is placed in a diffusion furnace tube at 850 ℃ for high-temperature diffusion, the diffusion time is 60 minutes, nitrogen and oxygen are introduced during the diffusion process, the flow ratio of the nitrogen to the oxygen is 5.
In this embodiment, a P + region and an N + region of the POLO-IBC battery can be manufactured by screen printing a boron paste and a phosphorus paste and by a high-temperature diffusion process, so that the P + region and the N + region both have polysilicon and can form good ohmic contact with a metal electrode, thereby effectively reducing the series resistance of the battery, improving the Fill Factor (FF), and improving the conversion efficiency of the battery. Moreover, the invention avoids the process of removing the polysilicon on the back surface by using a laser ablation process, simplifies the process and saves the production cost.
Referring to fig. 4, optionally, step S18 specifically includes:
step S184: and emitting laser to the boron slurry area and the phosphorus slurry area respectively.
Thus, the boron slurry area and the phosphorus slurry area are processed through laser, the amorphous silicon layer is converted into a polycrystalline silicon layer, and boron atoms in the boron slurry area and phosphorus atoms in the phosphorus slurry area are diffused into the polycrystalline silicon layer to form a P-type area and an N-type area. Moreover, the irradiation range and the irradiation energy can be accurately controlled by the laser, so that the treatment of the boron slurry area and the phosphorus slurry area can be more accurate, and the diffusion effect can be improved.
Optionally, in step S184, the laser is controlled to be blue light, green light or violet light, and the pulse width is nanosecond, picosecond or femtosecond. Therefore, various lasers and various pulse widths are provided, selection can be carried out according to actual conditions, and the diffusion effect can be guaranteed.
Note that when the boron paste region and the phosphorus paste region are processed by laser light, the type of laser light may be kept constant, or may be varied among blue light, green light, or violet light. Similarly, when the boron slurry region and the phosphorus slurry region are processed by the laser, the pulse width of the laser can be kept constant, and can also be made at nanosecond, picosecond or femtosecond.
Alternatively, laser light having the same parameters may be emitted to the boron paste region and the phosphorus paste region. Therefore, the operation is simple, and the manufacturing efficiency is high. Specifically, the laser light can be controlled to be blue light or green light, and the pulse width is nanosecond or picosecond.
Alternatively, laser light having corresponding parameters may be emitted to the boron paste region and the phosphorus paste region according to the pattern of the boron paste region and/or the phosphorus paste region. Therefore, the laser emitted to the boron slurry area is suitable for the boron slurry area, and the laser emitted to the phosphor slurry area is suitable for the phosphor slurry area, so that the diffusion effect of the two slurry areas can be optimal for the two slurry areas which emit the laser in a targeted manner. Specifically, the laser can be controlled to be green light or violet light, and the pulse width is picoseconds or femtoseconds.
Referring to fig. 5, optionally, step S18 specifically includes:
step S186: and carrying out ion bombardment on the boron slurry area and the phosphorus slurry area.
Thus, the diffusion layer is formed by ion bombardment, the doping depth and concentration can be accurately controlled, and the uniformity and repeatability of the impurity concentration are good. Specifically, the plasma may be accelerated by a plasma device to bombard the boron slurry region and the phosphorous slurry region. Further, the boron slurry region and the phosphorus slurry region may be subjected to ion bombardment simultaneously, or the boron slurry region and the phosphorus slurry region may be subjected to ion bombardment separately, which is not limited herein.
Optionally, a gap is provided between the boron slurry region and the phosphorus slurry region. Thus, the P region and the N region can be prevented from contacting, and electric leakage can be avoided.
Referring to fig. 6, optionally, the manufacturing method further includes the following steps:
step S17: and drying the boron slurry area and the phosphorus slurry area on the substrate.
Therefore, the boron slurry is attached to the boron slurry area and does not flow to the phosphorus slurry area, the phosphorus slurry is attached to the phosphorus slurry area and does not flow to the boron slurry area, and subsequent diffusion is facilitated. In this embodiment, the boron slurry region and the phosphorus slurry region on the substrate may be baked using a baking oven.
Specifically, the drying temperature may be in the range of 150 ℃ to 300 ℃, and the drying time may be in the range of 1 to 10min. The drying temperature is, for example, 150 deg.C, 152 deg.C, 161 deg.C, 178 deg.C, 185 deg.C, 190 deg.C, 235 deg.C, 264 deg.C, 298 deg.C, 300 deg.C. The drying time is, for example, 1min, 1.5min, 1.8min, 2min, 2.3min, 3min, 4.5min, 5min, 5.3min, 6.2min, 7.1min, 8min, 9.2min, 9.8min, 10min. Specific values of the drying temperature and the drying time are not limited as long as the aforementioned ranges are satisfied.
Optionally, step S19 specifically includes:
and respectively cleaning the substrate with the P-type region and the N-type region in alkaline liquid medicine, hydrofluoric acid liquid medicine and hydrochloric acid liquid medicine.
Therefore, the cleaning effect is better. Specifically, the substrate with the P-type region and the N-type region is placed in an alkaline solution to remove organic substances. And placing the substrate with the P-type region and the N-type region in hydrofluoric acid liquid medicine, removing borosilicate glass (BSG) and phosphosilicate glass (PSG), and neutralizing alkaline liquid medicine remained on the surface of the silicon wafer. And placing the substrate with the P-type region and the N-type region in hydrochloric acid liquor to remove residual metal ions on the surface.
Further, the substrate on which the P-type region and the N-type region are formed may be left in an alkaline chemical solution for 30 seconds or more; the substrate with the P-type region and the N-type region can be placed in hydrofluoric acid liquid medicine for more than 10 seconds; the substrate on which the P-type region and the N-type region are formed may be left in the hydrochloric acid solution for 10 seconds or more. Therefore, the cleaning device can be cleaned completely, and the cleaning effect is good. Further, the alkaline chemical solution includes a KOH chemical solution having a volume concentration of 10%.
In this embodiment, an HF chemical solution with a volume concentration of 5% may be used to remove PSG and BSG on the surface of the silicon wafer, and then a mixture of HF and HCl is used to clean the remaining portions of the boron slurry and the phosphorus slurry and remove the metal ions remaining on the surface of the silicon wafer, wherein the volume concentration of HF in the mixture of HF and HCl is 5% and the volume concentration of HCl is 10%.
Referring to fig. 7, a method for manufacturing a solar cell according to an embodiment of the present invention includes the following steps:
step S22: manufacturing a suede surface on the front side of the substrate;
step S10: the manufacturing method of any one of the interdigital back surface structures with the tunneling layer is used for manufacturing an interdigital back surface structure;
step S24: depositing a passivated antireflection film on the front surface and the back surface of the substrate respectively;
step S26: and manufacturing an electrode on the back of the substrate.
According to the manufacturing method of the solar cell, the boron slurry and the phosphorus slurry are printed in a graphical mode, the boron slurry area and the phosphorus slurry area are processed, amorphous silicon is changed into polycrystalline silicon, and boron atoms and phosphorus atoms are diffused into the polycrystalline silicon. Thus, the potential of the P + region formed by boron slurry doping is better. And moreover, a tunneling layer is reserved below the interdigital back structure, so that the recombination phenomenon can be reduced. In addition, the steps are simpler because laser etching is not needed. In addition, the manufacturing method of the embodiment of the invention can be applied to a P-type substrate or an N-type substrate. Therefore, the performance and the manufacturing efficiency of the interdigital back structure can be improved. Thus, the performance and the manufacturing efficiency of the solar cell are improved.
Specifically, in step S22, the damaged layer and the surface oil stain of the substrate may be removed, the front side texturing and the back side polishing are performed on the substrate, and the metal ions remaining on the surface of the substrate are removed. Therefore, the substrate is prevented from being damaged by dirt, and subsequent operation is facilitated.
Further, the substrate comprises a P-type silicon wafer or an N-type silicon wafer. The substrate has a resistivity in the range of 1-8 Ω -cm, for example, 1 Ω -cm, 1.2 Ω -cm, 1.9 Ω -cm, 2.1 Ω -cm, 3.5 Ω -cm, 4 Ω -cm, 5.3 Ω -cm, 6.2 Ω -cm, 7.5 Ω -cm, 7.9 Ω -cm, 8 Ω -cm. The thickness of the substrate ranges from 120-250um, such as 120um, 122um, 131um, 156um, 178um, 193um, 205um, 213um, 224um, 236um, 245um, 248um, 250um.
Further, a concentration of 10% by volume may be usedCarrying out rough polishing treatment on the substrate by KOH liquid medicine, and removing a damaged layer; KOH and H can be used 2 O 2 Cleaning the substrate by the mixed solution to remove oil stains on the surface, wherein the volume concentration of KOH in the mixed solution of KOH and H2O2 is 2%, and the volume concentration of H2O2 is 10%; the RCA1# solution can be used to clean the substrate to remove oil stains on the surface.
Further, in the case that the substrate is a polycrystalline silicon wafer, a hole-shaped suede can be made by acid liquor; when the substrate is a monocrystalline silicon wafer, the pyramid-shaped texture surface can be made by alkaline liquid medicine.
In this embodiment, a KOH solution with a volume ratio of 2% may be used to mix with the texturing additive, and under the conditions of a temperature of 80 ℃ and a time of 400s, pyramid-shaped textures are formed on the front and back surfaces of the silicon wafer. HF and HNO may be used 3 And mixing the solution, and performing rough polishing on the back surface of the silicon wafer, wherein the volume concentration of HF is 10% and the volume concentration of HNO3 is 40%. The back of the silicon chip can be polished by using KOH solution with the temperature of 80 ℃. And cleaning by using a mixed solution of HF and HCL to neutralize residual alkali liquor on the surface of the silicon wafer, wherein the volume concentration of HF is 5%, and the volume concentration of HCL is 10%. The RCA2# liquid can be used for cleaning the silicon wafer and removing metal ions on the surface of the silicon wafer.
For the explanation and explanation of step S10, please refer to the foregoing, and the description is omitted here for the sake of avoiding redundancy.
Specifically, in step S24, the passivated antireflection film may be one layer or a plurality of layers. Further, PECVD can be adopted for deposition to form the passivated antireflection film.
Alternatively, the passivated antireflection film may include at least one of a SiNx film, an AlOx film, a SiOx film, a SiOxNy film, and an amorphous silicon film.
In this embodiment, the passivated antireflection film is two layers, and includes an AlOx film and a SiNx film deposited in sequence, where the AlOx film and the SiNx film may be deposited in sequence on the back surface, and then the AlOx film and the SiNx film may be deposited in sequence on the front surface. The thickness of the back deposited AlOx film is 8nm, and the thickness of the SiNx film is 100nm. The thickness of the front deposited AlOx film was 6nm and the thickness of the SiNx film was 80nm. AlOx thin films can be grown on the back and the front of a silicon wafer by using tubular PECVD (plasma enhanced chemical vapor deposition)The SiNx film has a process temperature of 450 ℃. SiH may be introduced 4 And NH 3 Gas, siH 4 And NH 3 The gas flow ratio was 1. TMA and N may be introduced 2 O gas, TMA and N 2 The flow ratio of O gas is 1.
Specifically, in step S26, the electrode on the P region may be made of aluminum paste, and the electrode on the N region may be made of silver paste. Further, the electrode may be formed by screen printing and high-temperature sintering.
In this embodiment, a screen printing method may be used to fabricate an aluminum electrode above the P + region, and then enter a drying oven to dry, and then fabricate a silver electrode above the N + region. Wherein the printing speed is 450mm/s, the pressure is 60N, the printing pattern corresponds to the pattern of the laser grooving, and finally the metal electrode is solidified in a sintering furnace.
Referring to fig. 8, optionally, after step S24, the method further includes:
step S25: and carrying out graphical grooving on the passivated antireflection film on the back surface of the substrate.
Therefore, through the graphical grooving, the silicon substrate can form good ohmic contact with the electrode after the electrode slurry is sintered. Further, the grooves may be scored by laser, or may be scored by a metal needle. The particular manner of slotting is not limited herein.
In this example, the P + region and the N + region were grooved by laser light, which was green light, 532nm in wavelength, and nanosecond in pulse width. Therefore, the slotting effect is better.
Referring to fig. 9, optionally, before step S24, the method further includes:
step S23: and diffusing on the front surface of the substrate to form a doped layer.
Therefore, the conversion efficiency of the battery is improved. Specifically, boron diffusion can be performed on an N-type substrate to form a surface floating junction, or phosphorus diffusion can be performed on the N-type substrate to form a surface electric field layer; boron diffusion can be carried out on the P-type substrate to form a surface electric field layer, or phosphorus diffusion can be carried out on the P-type substrate to form a surface floating junction.
Referring to fig. 10 and 11, a solar cell 100 according to an embodiment of the present invention is manufactured by any one of the above methods for manufacturing a solar cell.
According to the solar cell 100 of the embodiment of the invention, the boron slurry and the phosphorus slurry are printed in a patterned manner, and the boron slurry area and the phosphorus slurry area are processed, so that amorphous silicon is changed into polycrystalline silicon, and boron atoms and phosphorus atoms are diffused into the polycrystalline silicon. Thus, the potential of the P + region formed by doping of the boron paste is better. And moreover, the tunneling layer is reserved below the interdigital back structure, so that the recombination phenomenon can be reduced. In addition, the steps are simpler because laser etching is not needed. In addition, the manufacturing method of the embodiment of the invention can be applied to a P-type substrate or an N-type substrate. Therefore, the performance and the manufacturing efficiency of the interdigital back structure can be improved. Thus, the performance and the manufacturing efficiency of the solar cell are improved.
Specifically, the solar cell 100 includes a passivated anti-reflective film 101, a doped layer 102, a substrate 103, a P-type region 104, an N-type region 105, an aluminum electrode 106, a silver electrode 107, and a tunneling layer 108. Further, the passivated antireflection film 101 includes Si 3 N 4 Film 1011 and Al 2 O 3 Film 1012. Note that the substrate 103 in fig. 10 is an n-type silicon wafer, and the substrate 103 in fig. 11 is a p-type silicon wafer. Note that the broken lines in fig. 10 and 11 indicate the specific structure in which the partial region is omitted. Specifically, the P-type regions 104 and the N-type regions 105, which are alternately disposed, and the aluminum electrodes 106 disposed corresponding to the P-type regions 104 and the silver electrodes 107 disposed corresponding to the N-type regions 105 are omitted.
For further explanation and explanation of the solar cell 100, reference is made to the above description, and redundant description is omitted here.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A manufacturing method of an interdigital back structure with a tunneling layer is characterized by comprising the following steps:
manufacturing a tunneling layer on the surface of the substrate;
depositing an amorphous silicon layer on the substrate for preparing the tunneling layer;
graphically printing boron slurry and phosphorus slurry on the amorphous silicon layer to form a boron slurry area and a phosphorus slurry area, wherein the boron slurry area and the phosphorus slurry area are intersected;
processing the boron slurry area and the phosphorus slurry area to enable the amorphous silicon layer to be converted into a polycrystalline silicon layer, and enabling boron atoms in the boron slurry area and phosphorus atoms in the phosphorus slurry area to diffuse into the polycrystalline silicon layer to form a P-type area and an N-type area;
and cleaning the surface of the substrate on which the P-type region and the N-type region are formed.
2. The method for fabricating an interdigital back surface structure with a tunneling layer according to claim 1, wherein the step of processing the boron paste region and the phosphorus paste region comprises:
and placing the substrate printed with the boron slurry area and the phosphorus slurry area into an environment with preset temperature.
3. The method according to claim 2, wherein the predetermined temperature is in a range of 700 ℃ to 1200 ℃ and the holding time is in a range of 20 to 180min.
4. The method for fabricating an interdigital back surface structure with a tunneling layer according to claim 1, wherein the step of processing the boron paste region and the phosphorus paste region comprises:
and emitting laser to the boron slurry area and the phosphorus slurry area respectively.
5. The method for fabricating an interdigital back surface structure having a tunneling layer according to claim 4, wherein in the step of emitting laser light to the boron paste region and the phosphorus paste region, respectively, the laser light is controlled to be blue light, green light or violet light, and the pulse width is nanosecond, picosecond or femtosecond.
6. The method of fabricating an interdigital back structure with a tunneling layer of claim 1, wherein said step of processing said boron paste region and said phosphorous paste region comprises:
and carrying out ion bombardment on the boron slurry area and the phosphorus slurry area.
7. The method of fabricating an interdigitated back structure with a tunneling layer according to claim 1, wherein a gap is provided between said boron paste region and said phosphorous paste region.
8. The method for fabricating an interdigital back surface structure with a tunneling layer according to any one of claims 1-7, further comprising the steps of:
and drying the boron slurry area and the phosphorus slurry area on the substrate.
9. The method for manufacturing the interdigital back surface structure with a tunneling layer according to any one of claims 1 to 7, wherein the step of cleaning the surface of the substrate on which the P-type region and the N-type region are formed specifically comprises:
and respectively cleaning the substrate with the P-type region and the N-type region in alkaline liquid medicine, hydrofluoric acid liquid medicine and hydrochloric acid liquid medicine.
10. A manufacturing method of a solar cell is characterized by comprising the following steps:
manufacturing a suede surface on the front side of the substrate;
the method of any of claims 1 to 9, forming an interdigitated back structure;
depositing a passivated antireflection film on the front surface and the back surface of the substrate respectively;
and manufacturing an electrode on the back of the substrate.
11. The method for manufacturing a solar cell according to claim 10, wherein the step of depositing a passivation antireflection film on the front surface and the back surface of the substrate respectively further comprises:
and carrying out graphical grooving on the passivated antireflection film on the back surface of the substrate.
12. The method of claim 10, wherein the step of depositing the passivated anti-reflective film on the front side and the back side of the substrate further comprises:
and diffusing the front surface of the substrate to form a doped layer.
13. The method of claim 10, wherein the passivation anti-reflective film comprises at least one of a SiNx film, an AlOx film, a SiOx film, a SiOxNy film, and an amorphous silicon film.
14. A solar cell, characterized by being produced by the method of any one of claims 10 to 13.
CN202110346659.2A 2021-03-31 2021-03-31 Back surface structure manufacturing method, solar cell manufacturing method and solar cell Pending CN115224151A (en)

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CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
CN111816554A (en) * 2020-09-03 2020-10-23 东方日升新能源股份有限公司 Front-side local re-expansion method of P-type back-junction contact passivated battery and battery preparation method
CN112164728A (en) * 2020-10-29 2021-01-01 天合光能股份有限公司 Patterned passivated contact solar cells and methods of making same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106784069A (en) * 2015-11-20 2017-05-31 上海神舟新能源发展有限公司 Back surface tunnel oxidation is passivated interdigital formula back junction back contact battery production method
CN106876501A (en) * 2017-03-10 2017-06-20 泰州乐叶光伏科技有限公司 One kind passivation contact all back-contact electrodes solar battery structure and preparation method thereof
CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
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