CN106783576B - Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip - Google Patents
Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip Download PDFInfo
- Publication number
- CN106783576B CN106783576B CN201611183968.8A CN201611183968A CN106783576B CN 106783576 B CN106783576 B CN 106783576B CN 201611183968 A CN201611183968 A CN 201611183968A CN 106783576 B CN106783576 B CN 106783576B
- Authority
- CN
- China
- Prior art keywords
- corrosion
- silicon wafer
- mesa
- etching
- primary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000007797 corrosion Effects 0.000 title claims abstract description 39
- 238000005260 corrosion Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 88
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 86
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 85
- 239000000843 powder Substances 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000011521 glass Substances 0.000 claims abstract description 47
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000007790 scraping Methods 0.000 claims description 30
- 238000005245 sintering Methods 0.000 claims description 29
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000009766 low-temperature sintering Methods 0.000 claims description 7
- 239000002002 slurry Substances 0.000 claims description 6
- 239000005357 flat glass Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000011049 filling Methods 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 60
- 239000000243 solution Substances 0.000 description 21
- 239000002253 acid Substances 0.000 description 15
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 239000011259 mixed solution Substances 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 6
- 229960000583 acetic acid Drugs 0.000 description 6
- 239000012362 glacial acetic acid Substances 0.000 description 6
- 239000005457 ice water Substances 0.000 description 6
- 229910017604 nitric acid Inorganic materials 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
Abstract
A secondary mesa etching process for a high-voltage-resistance semiconductor discrete device chip comprises the following steps: carrying out primary corrosion on the surface of a silicon wafer with an oxide layer on the surface, wherein the primary corrosion depth is 75-85 mu m; carrying out secondary corrosion on the silicon wafer subjected to the primary corrosion V-shaped groove through a photoetching mask, wherein the secondary corrosion depth is 7-10 mu m, and the width of the secondary corrosion table top is larger than that of the primary corrosion table top; and after the two mesa etchings are finished, performing glass passivation. Through the secondary corrosion of the mesa, small-angle steps caused by different corrosion rates of silicon and silicon dioxide at the position close to the surface of the silicon wafer are removed, a physical buffer area is formed at the joint of the surface of the silicon wafer and the mesa of the V-shaped groove by the fused passivation process of filling glass powder in the groove, the contact area of the glass powder and the corrosion mesa is increased, the contact capacity is increased, the dielectric strength is improved, and the surface leakage is reduced, so that the excellent high-temperature and high-pressure performance and high reliability of the high-pressure-resistant semiconductor discrete device chip are ensured.
Description
Technical Field
The invention relates to a secondary mesa etching process for a high-voltage-resistance semiconductor discrete device chip.
The invention relates to a processing method of a semiconductor device, in particular to a secondary mesa etching process of a high-voltage-resistance semiconductor discrete device chip.
Background
A traditional mesa semiconductor discrete device chip adopts a one-step V-shaped groove etching process, and the etching depth is generally 80-90 mu m. Because the corrosion rates of silicon dioxide and silicon are different, small-angle steps are formed on the interface of the silicon dioxide and the silicon in the corrosion process, the filling effect of the subsequent glass powder on the V-shaped groove is influenced, and the position, close to the surface of the silicon wafer, of the V-shaped groove cannot be completely filled and covered by the glass powder, so that when a product is subjected to voltage test, sparks are easily generated on the edge of the V-shaped groove, the breakdown voltage of the product is reduced due to the increase of surface leakage, and the reliability of the product is influenced.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a secondary mesa etching process for a high-voltage-resistance semiconductor discrete device chip, which enlarges the contact area between glass powder and an etched mesa, increases the contact capacity, improves the dielectric strength and reduces the surface electric leakage, thereby ensuring the excellent high-temperature and high-voltage performance and high reliability of the high-voltage-resistance semiconductor discrete device chip.
The technical solution of the invention is as follows:
a secondary mesa etching process for a high-voltage-resistance semiconductor discrete device chip comprises the following steps:
1. carrying out primary corrosion on the surface of a silicon wafer with an oxide layer on the surface, wherein the primary corrosion depth is 75-85 mu m;
2. carrying out secondary corrosion on the silicon wafer subjected to the primary corrosion V-shaped groove through a photoetching mask, wherein the secondary corrosion depth is 7-10 mu m, and the width of the secondary corrosion table top is larger than that of the primary corrosion table top;
3. and after the two mesa etchings are finished, performing glass passivation.
Furthermore, the time for the first etching is 3-4 min, and the time for the second etching is 0.5-0.8 min.
Furthermore, the width difference between the secondary etching table and the primary etching table is 60-80 μm.
Further, a knife scraping method is adopted during glass passivation, and the process steps are as follows:
1. powder scraping, namely coating a proper amount of glass powder slurry on the surface of a silicon wafer by using a clean glass rod, uniformly scraping and coating the surface of the silicon wafer in a groove by using a single-sided blade at an angle of 45 degrees with the horizontal direction, and repeatedly scraping and coating for 15-20 times until the groove is full; then, baking the silicon wafer on an electric furnace of 300-500W for 3-5 min until the glass powder is dried to be white;
2. sintering at low temperature, namely sintering the silicon chip subjected to powder scraping at 480-520 ℃ for 20-30 minutes at low temperature, and introducing N2 as protective gas in the sintering process;
3. powder wiping: placing the silicon wafer sintered at low temperature on a clean and flat glass plate, and wiping off glass powder on the surface of the silicon wafer lightly and flatly by using an eraser;
4. and (3) high-temperature sintering: sintering the silicon wafer subjected to powder wiping at the high temperature of 720-880 ℃ for 15-20 minutes, and introducing N2 or O2 as a protective gas in the sintering process;
5. the above process is repeated two to three times.
The invention has the beneficial effects that: through the secondary corrosion of the mesa, small-angle steps caused by different corrosion rates of silicon and silicon dioxide at the position close to the surface of the silicon wafer are removed, a physical buffer area is formed at the joint of the surface of the silicon wafer and the mesa of the V-shaped groove by the fused passivation process of filling glass powder in the groove, the contact area of the glass powder and the corrosion mesa is increased, the contact capacity is increased, the dielectric strength is improved, and the surface leakage is reduced, so that the excellent high-temperature and high-pressure performance and high reliability of the high-pressure-resistant semiconductor discrete device chip are ensured.
Drawings
FIG. 1 is a schematic view of a primary etched mesa structure of a silicon wafer;
FIG. 2 is a schematic diagram of a secondary etched mesa structure of a silicon wafer;
FIG. 3 is a schematic diagram of a silicon wafer etching mesa after being filled with glass powder.
In the figure: 1-silicon chip, 2-oxide layer, 3-primary corrosion table, 4-secondary corrosion table and 5-fused glass powder.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings:
example 1
The secondary mesa etching process for the high-voltage-resistance semiconductor discrete device chip comprises the following steps:
1. as shown in figure 1, a silicon wafer 1 with an oxide layer 2 on the surface is subjected to one V-shaped groove corrosion by mixed acid solution, and the thickness dsio of the oxide layer on the surface of the silicon wafer2The thickness is 0.5 mu m, the mixed acid solution is a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, the volume ratio is 5:3:2, a container for containing the mixed acid solution is placed in the mixed ice-water solution, the silicon wafer is corroded in the mixed acid solution for 3min at the timing, the corrosion depth of the measuring groove reaches 75 mu m, the width reaches 180 mu m, and a primary corrosion table top 3 is formed.
2. As shown in fig. 2, after a silicon wafer 1 forming a primary etching mesa 3 is subjected to photoetching mask, a V-shaped groove is subjected to secondary etching by using a mixed acid solution, wherein the mixed acid solution is a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, the volume ratio is 5:3:2, a container containing the mixed acid solution is placed in the mixed ice-water solution, the silicon wafer is subjected to timed etching for 0.5min in the mixed acid solution, the etching depth of the measuring groove reaches 7 micrometers, the width of the groove surface reaches 240 micrometers, and a secondary etching mesa 4 is formed. The difference between the width of the secondary etching mesa 4 and the width of the primary etching mesa 3 was 60 μm.
3. As shown in fig. 3, a doctor blade glass passivation process is used, and the V-shaped groove after the secondary etching is filled with glass powder to perform fused passivation to form fused glass powder 5.
The specific process comprises the following steps: powder scraping → low temperature sintering → powder scraping → high temperature sintering.
And (3) powder scraping, namely coating a proper amount of glass powder slurry on the surface of the silicon wafer by using a clean glass rod, uniformly scraping and coating the silicon wafer in the groove by using a single-sided blade at an angle of 45 degrees with the horizontal direction, and repeatedly scraping and coating for 15 times until the groove is full. Then the silicon chip is placed on a 300W electric furnace to be baked for 5min, and the glass powder is dried to be white.
And (3) low-temperature sintering: and sintering the silicon chip subjected to powder scraping at 480 ℃ for 30 minutes at low temperature, wherein N2 is introduced as protective gas in the sintering process.
Powder wiping: and (3) placing the silicon wafer sintered at low temperature on a clean and flat glass plate, and lightly and flatly wiping the glass powder on the surface of the silicon wafer by using an eraser without wiping the glass powder in the groove.
And (3) high-temperature sintering: and sintering the silicon wafer subjected to powder wiping at the high temperature of 720 ℃ for 20 minutes, wherein N2 or O2 is introduced as protective gas in the sintering process.
The above process was repeated two times.
Example 2
The secondary mesa etching process for the high-voltage-resistance semiconductor discrete device chip comprises the following steps:
1. as shown in figure 1, the surface of a silicon wafer with an oxide layer 2 on the surface is subjected to one V-shaped groove corrosion by using a mixed acid solution, and the thickness dsio of the oxide layer on the surface of the silicon wafer20.65 μm, mixed acid solution of nitric acid, hydrofluoric acid and glacial acetic acid at volume ratio of 5:3:2, placing the container in ice-water mixture, and placing silicon wafer in the containerEtching for 4min in the mixed acid solution, measuring the etching depth of the groove to 85 μm and the etching width to 200 μm, and forming a primary etching table top 3.
2. As shown in fig. 2, after a silicon wafer 1 forming a primary etching mesa 3 is subjected to photoetching mask, a V-shaped groove is subjected to secondary etching by using a mixed acid solution, wherein the mixed acid solution is a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid, the volume ratio is 5:3:2, a container containing the mixed acid solution is placed in the mixed ice-water solution, the silicon wafer is subjected to chronoetching for 48 seconds in the mixed acid solution, the etching depth of the measuring groove reaches 10 micrometers, the width of the groove surface reaches 280 micrometers, and a secondary etching mesa 4 is formed. The difference between the width of the secondary etching mesa 4 and the width of the primary etching mesa 3 was 80 μm.
3. As shown in fig. 3, a doctor blade glass passivation process is used, and the V-shaped groove after the secondary etching is filled with glass powder to perform fused passivation to form fused glass powder 5.
The specific process comprises the following steps: powder scraping → low temperature sintering → powder scraping → high temperature sintering.
And (3) powder scraping, namely coating a proper amount of glass powder slurry on the surface of the silicon wafer by using a clean glass rod, uniformly scraping and coating the silicon wafer in the groove by using a single-sided blade at an angle of 45 degrees with the horizontal direction, and repeatedly scraping and coating for 20 times until the groove is full. Then the silicon chip is placed on a 500W electric furnace to be baked for 3min, and the glass powder is dried to be white.
And (3) low-temperature sintering, namely sintering the silicon chip subjected to powder scraping at 520 ℃ for 20 minutes, and introducing N2 as protective gas in the sintering process.
Powder wiping: and (3) placing the silicon wafer sintered at low temperature on a clean and flat glass plate, and lightly and flatly wiping the glass powder on the surface of the silicon wafer by using an eraser without wiping the glass powder in the groove.
And (3) high-temperature sintering: and sintering the silicon wafer subjected to powder wiping at 880 ℃ for 15 minutes, wherein N2 or O2 is introduced as protective gas during sintering.
This process was repeated three times.
Example 3
The secondary mesa etching process for the high-voltage-resistance semiconductor discrete device chip comprises the following steps:
1.3 DD1 in two-piece taking process55I products are respectively marked as a silicon chip I and a silicon chip II, and the thickness dsio of the oxide layers on the surfaces of the two silicon chips2Are all 0.55 μm.
2. And carrying out one-time V-shaped groove corrosion on the two silicon wafers after the mesa photoetching. Placing a container containing a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 5:3:2 in an ice-water mixed solution, placing two silicon wafers on a wafer frame, placing the wafer frame into an etching solution for timing etching, taking out the silicon wafers after timing for 3min and 40 sec, and measuring the depth and width of a V-shaped groove, wherein the depth of the groove surface mesa of the two silicon wafers is 81 micrometers, and the width of the groove surface mesa of the two silicon wafers is 192 micrometers.
3. And (3) placing the silicon wafer I in high-purity water to be cleaned, cleaning and processing the silicon wafer II, and then carrying out secondary groove photoetching on a mask.
4. And carrying out secondary V-shaped groove corrosion on the silicon wafer II subjected to the secondary groove mask photoetching. And placing a container containing a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 5:3:2 in an ice-water mixed solution, placing a silicon wafer II on a wafer frame, placing the silicon wafer II in an etching solution for timing etching, taking out the silicon wafer after timing for 35 seconds, and measuring the depth and the width of a V-shaped groove, wherein the depth of the groove surface of the secondary V-shaped groove of the silicon wafer II is 8.5 micrometers, and the width of the table surface of the groove surface is 270 micrometers.
5. And (3) cleaning the silicon wafer I and the silicon wafer II after the V-shaped groove is corroded, filling glass powder into the V-shaped groove by adopting a scraping glass passivation process, and performing fusion passivation.
The specific process comprises the following steps: powder scraping → low temperature sintering → powder scraping → high temperature sintering.
And (3) powder scraping, namely coating a proper amount of glass powder slurry on the surface of the silicon wafer by using a clean glass rod, uniformly scraping and coating the silicon wafer in the groove by using a single-sided blade at an angle of 45 degrees with the horizontal direction, and repeatedly scraping and coating for 18 times until the groove is full. Then the silicon chip is placed on a 350W electric furnace to be baked for 4min, and the glass powder is dried to be white.
And (3) low-temperature sintering, namely sintering the silicon chip subjected to powder scraping at 510 ℃ for 25 minutes, wherein N2 is introduced as protective gas in the sintering process.
Powder wiping: and (3) placing the silicon wafer sintered at low temperature on a clean and flat glass plate, and lightly and flatly wiping the glass powder on the surface of the silicon wafer by using an eraser without wiping the glass powder in the groove.
And (3) high-temperature sintering: and sintering the silicon wafer subjected to powder wiping at 820 ℃ for 18 minutes, wherein N2 is introduced as a protective gas during sintering.
This process was repeated three times.
6. After glass passivation, 10 dies are respectively extracted from the silicon wafer I and the silicon wafer II to carry out BVCBO test, and the test results of the BVCBO values are shown in a table 1: unit (V)
Note: test condition ICB 1mA
Description of the drawings: when the silicon wafer I is tested, sparks are generated on the edge of the V-shaped groove on the surface of the chip obviously, but the phenomenon is not generated on the silicon wafer II, and the BVCBO value of the silicon wafer II is 80-100V higher than that of the silicon wafer I.
7. Finishing the chip production flow by the silicon chip I and the silicon chip II, respectively selecting 10 branch tube cores for packaging, and then carrying out product parameter test, wherein the test values of BVCBO and ICBO are selected and recorded in a table 2:
note: and (3) testing conditions are as follows: BVCBO: ICB 1mA requires BVCBO >1100V
ICBO VCB 100V ICBO <100 μ A
The above-described embodiments are intended to illustrate rather than to limit the invention, and any modifications and variations of the present invention are within the spirit of the invention and the scope of the appended claims.
Claims (4)
1. A secondary mesa etching process for a high-voltage-resistance semiconductor discrete device chip is characterized by comprising the following steps:
1.1) carrying out primary corrosion on the surface of a silicon wafer with an oxide layer on the surface, wherein the primary corrosion depth is 75-85 μm;
1.2) carrying out secondary corrosion on the silicon wafer subjected to the primary corrosion V-shaped groove through a photoetching mask, wherein the secondary corrosion depth is 7-10 mu m, and the width of the secondary corrosion table top is larger than that of the primary corrosion table top;
1.3) and after the two mesa etchings are finished, performing glass passivation.
2. The secondary etching mesa process of the chip of the high-voltage semiconductor discrete device as claimed in claim 1, wherein the time for the primary etching is 3min to 4min, and the time for the secondary etching of the mesa is 0.5min to 0.8 min.
3. The secondary etching mesa process of the chip of the high-voltage semiconductor discrete device as claimed in claim 1, wherein the difference between the widths of the secondary etching mesa and the primary etching mesa is 60 μm to 80 μm.
4. The secondary etching mesa process of high voltage semiconductor discrete device chip as claimed in claim 1, wherein a knife-scraping method is adopted during glass passivation, and the process steps are as follows:
4.1) scraping powder, namely coating a proper amount of glass powder slurry on the surface of a silicon wafer by using a clean glass rod, uniformly scraping and coating the glass powder slurry in a groove by using a single-sided blade at an angle of 45 degrees with the horizontal direction, and repeatedly scraping and coating for 15-20 times until the groove is full; then, the silicon chip is placed on an electric furnace of 300W-500W to be baked for 3 min-5 min until the glass powder is dried to be white;
4.2) low-temperature sintering, namely sintering the silicon chip subjected to powder scraping at 480-520 ℃ for 20-30 minutes, and introducing N2 as a protective gas in the sintering process;
4.3), powder scraping: placing the silicon wafer sintered at low temperature on a clean and flat glass plate, and wiping off glass powder on the surface of the silicon wafer lightly and flatly by using an eraser;
4.4), high-temperature sintering: sintering the silicon wafer subjected to powder wiping at the high temperature of 720-880 ℃ for 15-20 minutes, and introducing N2 or O2 as protective gas in the sintering process;
4.5) repeating the above process for two times to three times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611183968.8A CN106783576B (en) | 2016-12-20 | 2016-12-20 | Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611183968.8A CN106783576B (en) | 2016-12-20 | 2016-12-20 | Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106783576A CN106783576A (en) | 2017-05-31 |
| CN106783576B true CN106783576B (en) | 2021-01-26 |
Family
ID=58896168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611183968.8A Active CN106783576B (en) | 2016-12-20 | 2016-12-20 | Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106783576B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341735B (en) * | 2020-03-12 | 2021-03-26 | 扬州国宇电子有限公司 | Passivation structure for preventing scratching table top and preparation method and application thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85100410A (en) * | 1985-04-01 | 1986-07-09 | 山东师范大学 | Process for passivating mesa semiconductor devices with glass |
| CN101038892A (en) * | 2007-04-25 | 2007-09-19 | 天津中环半导体股份有限公司 | Knife scraping method glass passivation process for silicon current rectifier |
| CN101393929A (en) * | 2008-11-10 | 2009-03-25 | 吉林华微电子股份有限公司 | Thyristor for terminal semi-conductor discrete device with dual positive oblique angle slots and manufacturing method thereof |
| CN104269356A (en) * | 2014-09-29 | 2015-01-07 | 西安卫光科技有限公司 | Method for manufacturing 50A high-current fast recovery diode |
| CN104810281A (en) * | 2015-03-11 | 2015-07-29 | 苏州启澜功率电子有限公司 | Transient voltage suppression diode array chip according to mesa trench isolation method and production technology thereof |
| CN205428951U (en) * | 2016-03-14 | 2016-08-03 | 江苏捷捷微电子股份有限公司 | VR is greater than 2600V's square piece formula glass passivation diode chip |
| CN205582943U (en) * | 2016-04-05 | 2016-09-14 | 江苏东晨电子科技有限公司 | Integrated gate stull face thyristor |
| CN106024865A (en) * | 2016-07-19 | 2016-10-12 | 如皋市大昌电子有限公司 | Mesa diode processing technology |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI401749B (en) * | 2004-12-27 | 2013-07-11 | Third Dimension 3D Sc Inc | Process for high voltage superjunction termination |
-
2016
- 2016-12-20 CN CN201611183968.8A patent/CN106783576B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85100410A (en) * | 1985-04-01 | 1986-07-09 | 山东师范大学 | Process for passivating mesa semiconductor devices with glass |
| CN101038892A (en) * | 2007-04-25 | 2007-09-19 | 天津中环半导体股份有限公司 | Knife scraping method glass passivation process for silicon current rectifier |
| CN101393929A (en) * | 2008-11-10 | 2009-03-25 | 吉林华微电子股份有限公司 | Thyristor for terminal semi-conductor discrete device with dual positive oblique angle slots and manufacturing method thereof |
| CN104269356A (en) * | 2014-09-29 | 2015-01-07 | 西安卫光科技有限公司 | Method for manufacturing 50A high-current fast recovery diode |
| CN104810281A (en) * | 2015-03-11 | 2015-07-29 | 苏州启澜功率电子有限公司 | Transient voltage suppression diode array chip according to mesa trench isolation method and production technology thereof |
| CN205428951U (en) * | 2016-03-14 | 2016-08-03 | 江苏捷捷微电子股份有限公司 | VR is greater than 2600V's square piece formula glass passivation diode chip |
| CN205582943U (en) * | 2016-04-05 | 2016-09-14 | 江苏东晨电子科技有限公司 | Integrated gate stull face thyristor |
| CN106024865A (en) * | 2016-07-19 | 2016-10-12 | 如皋市大昌电子有限公司 | Mesa diode processing technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106783576A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104766790B (en) | A kind of phosphorus, boron liquid source perfect diffusion technique | |
| CN105826172A (en) | Passivation protection method capable of increasing reliability and yield rate of semiconductor chip | |
| CN106024624B (en) | A kind of manufacturing method of highly reliable Flouride-resistani acid phesphatase transient voltage suppressor | |
| CN108010841B (en) | A kind of manufacturing method of diode and thus obtained diode | |
| CN106783576B (en) | Secondary corrosion table-board process for high-voltage-resistance semiconductor discrete device chip | |
| CN106024865A (en) | Mesa diode processing technology | |
| CN105355654A (en) | Low-voltage transient-suppression diode chip with low electric leakage and high reliability and production method | |
| CN104269356B (en) | Method for manufacturing 50A high-current fast recovery diode | |
| CN105470150A (en) | Glass passivation method for silicon mesa diodes | |
| CN114335190A (en) | Knife-scraping diode chip with simplified manufacturing process and manufacturing method thereof | |
| CN102569531B (en) | Passivating method for polycrystalline silicon chips | |
| CN108365015A (en) | Semiconductor diode chip and preparation method thereof | |
| CN107887281B (en) | A kind of manufacturing method and high voltage silicon rectifier stack of low-power consumption high-speed switch plastic sealed high-voltage silicon stack | |
| CN205385026U (en) | Two -way discharge tube chip | |
| CN105932070A (en) | Low-power-consumption and high-surge capacity diode rectifier chip and production technology thereof | |
| CN208706655U (en) | A kind of controlled silicon chip of punch-through | |
| CN102509707A (en) | Process of carrying out passivation protection on rectification chip by use of polyimide | |
| TWI529972B (en) | Glass passivated semiconductor diode chip and manufacturing method thereof | |
| CN108573857B (en) | High-reliability GPP chip preparation method | |
| CN113299567A (en) | Passivation layer manufacturing method | |
| CN101944557A (en) | High-order side corrosion method for side of high-power gallium nitride based chip | |
| CN103117220B (en) | The minimizing technology of super junction sacrificial oxide layer | |
| CN104282534B (en) | The processing method of cracks of metal surface | |
| CN103094409B (en) | A kind of edge etching process being applied to polysilicon solar cell | |
| CN103700740A (en) | Manufacturing method of thyristor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 121000 No. 58, Songshan street, Taihe District, Jinzhou City, Liaoning Province Patentee after: Jinzhou Liaojing Electronic Technology Co.,Ltd. Address before: 121000 No. five, section 10, Renmin Street, Guta District, Liaoning, Jinzhou Patentee before: JINZHOU LIAOJING ELECTRONIC TECHNOLOGY CO.,LTD. |
|
| CP03 | Change of name, title or address |