CN108573857B - High-reliability GPP chip preparation method - Google Patents
High-reliability GPP chip preparation method Download PDFInfo
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- CN108573857B CN108573857B CN201810399395.5A CN201810399395A CN108573857B CN 108573857 B CN108573857 B CN 108573857B CN 201810399395 A CN201810399395 A CN 201810399395A CN 108573857 B CN108573857 B CN 108573857B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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Abstract
The invention discloses a GPP chip preparation method, which comprises the following steps: 1) coating photoresist on the diffused PN junction silicon wafer; 2) with HF HNO3Corrosion by HAc mixed corrosive liquidEtching a groove; 3) carrying out oxygen doping and nitrogen doping in the groove by adopting an LPCVD growth mode; 4) scraping and coating glass powder, and sintering glass; 5) adopting PECVD to grow soft Si after sintering in the step 4)3N4(ii) a 6) Carrying out secondary photoetching and Ni plating, then plating an N-Si alloy, and plating Ni again after the Ni-Si alloy is plated; 7) testing; 8) and (4) back laser scribing. The invention uses PECVD to grow soft silicon nitride (Si) on the surface of glass3N4) Therefore, the high-reliability 1A-50A and 300-1800V GPP chips with low leakage current, high voltage, good moisture resistance and low stress are formed, and the advantages of wide application range, low cost, good stability, high reliability and the like are achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a preparation method of a high-reliability glass passivation (GPP) chip.
Background
GPP (glass passivation) chips are the mainstream of high and new technologies at present. The GPP process is divided into three process implementation methods: the method comprises a knife scraping method, a photoresist method and an electrophoresis method, wherein the three methods have advantages and disadvantages, the knife scraping method has low cost and non-uniform electric leakage; the photoresist method has better parameter consistency but higher cost; the electrophoresis method has large one-time investment, high environmental protection cost and difficult waste treatment.
At present, the requirements for passivation of semiconductor surfaces are increasing more and more, and GPP chips should have: 1. good electrical performance and reliability, including resistivity, dielectric strength, ion mobility and the like, and the introduction of the material does not bring side effects to the device; secondly, the chemical stability is good, and the chemical corrosion resistance is certain; thirdly, operability, simple process, good repeatability, compatibility with the device manufacturing process, and the expansion coefficient of the material is consistent with or close to that of the silicon material; fourthly, the method is economical, can be produced in large scale, has low manufacturing cost and market competitiveness, and has strong vitality and development potential of materials and processes. However, the GPP chip prepared by the method on the market has the problems and cannot meet the requirements.
Disclosure of Invention
The invention aims to provide a preparation method of a glass passivation (GPP) chip, which has low cost, good stability and high reliability and can be produced in large scale.
The technical scheme for realizing the purpose is as follows:
a preparation method of a high-reliability GPP chip comprises the following steps:
1) coating photoresist on the diffused PN junction silicon wafer;
2) with HF HNO3Etching the groove by using the HAc mixed etching solution;
3) carrying out oxygen doping and nitrogen doping in the groove by adopting an LPCVD growth mode;
4) scraping and coating glass powder, and sintering glass;
5) adopting PECVD to grow soft Si after sintering in the step 4)3N4；
6) Carrying out secondary photoetching and Ni plating, then plating Ni-Si alloy, and plating Ni again after the Ni-Si alloy is plated;
7) testing;
8) and (4) back laser scribing.
HNO as HF in the step 2)3HAc in a volume ratio of 0.8-1.2: 1.8-2.2, the HF and HNO3And the mass fraction concentration of HAc is 40-45%, 83-93% and 33-45% respectively.
The step 3) adopts LPCVD growth mode to carry out oxygen doping and nitrogen doping in the groove under the condition of 650-750 ℃,
the temperature of the step 4) is 820-850 ℃, N2+O2Sintering the glass under the condition;
the working condition of the PECVD in the step 5) is 380-420 ℃,
in the step 6), the temperature is 580-620 ℃ and N is2+H2Plating Ni-Si alloy under the condition.
The invention has the beneficial effects that: growing oxygen-doped and nitrogen-doped polysilicon in the exposed groove by LPCVD; coating glass powder by a knife scraping method; soft silicon nitride (Si) growth on glass surface by PECVD3N4) Therefore, the high-reliability 1A-50A and 300-1800V GPP chips with low leakage current, high voltage, good moisture resistance and low stress are formed, and the chip has the advantages of wide application range, low cost, large-scale batch production, good stability, high reliability and the like.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to be limiting.
The experimental procedures in the following examples are conventional unless otherwise specified.
Example 1 preparation of highly reliable glass passivated (GPP) chips
Preparing a high-reliability glass passivation (GPP) chip, and operating according to the following steps:
1) coating primary photoresist with the viscosity of 350-450 cps on the diffused PN junction (P-N +) silicon chip;
2) then adopting HF to HNO according to volume ratio3HAc 1:1:2 ratio of etching solution to etch the groove at low temperature under the condition of 2-10 deg.C, HF, HNO3And the mass fraction concentrations of HAc were 42%, 88%, and 38%, respectively.
3) Carrying out oxygen and nitrogen doping in the groove by adopting an LPCVD (low pressure chemical vapor deposition) growth mode at 650-750 ℃;
4) scraping glass powder on the basis of the step 3), and carrying out N coating at the temperature of 820-850 DEG C2+O2) Sintering the glass under the condition;
5) growing soft Si on the surface of the glass powder in the step 4) by adopting PECVD (380-420℃)3N4；
6) Performing secondary photoetching and Ni plating after the step 5), and then performing N plating at 580-620 DEG C2+H2Plating Ni-Si alloy under the condition, and then plating Ni again;
7) testing;
8) and (4) back laser scribing.
The prepared GPP chip has the following characteristics through detection:
A. due to soft Si of the surface3N4The moisture resistance is good, and the capacity of PCT 96Hrs can be stably achieved;
B. due to good transition between the SiPOS film and the Si substrate, the low of the drain electrode of the P/N junction can reach Ir ≦ 0.2uA, especially the Ir ≦ 20uA at high temperature of 150 ℃;
C. the refractive indexes of the composite films with the three-layer passivation structure are different, and the composite films can be widely used for special purposes of resisting external electron radiation, single particle radiation interference and the like.
The invention adopts PECVD (380-420 ℃), to grow soft Si3N4So that the chip has stronger radiation resistance and particle interference resistance, and the manufacture method is also usedThe method has low process cost, can realize large-scale batch production, and the prepared chip has good stability and high reliability.
Claims (3)
1. A GPP chip preparation method is characterized by comprising the following steps:
1) coating photoresist on the diffused PN junction silicon wafer;
2) etching the groove by using a mixed etching solution of HF, HNO3 and HAc; the volume ratio of the HF to the HNO3 to the HAc is 0.8-1.2: 1.8-2.2, and the mass fraction concentrations of the HF to the HNO3 to the HAc are 40-45%, 83-93% and 33-45% respectively;
3) adopting LPCVD growth mode, at 650-750 deg.C,
growing oxygen-doped and nitrogen-doped polycrystalline silicon in the groove under the condition;
4) scraping and coating glass powder, and sintering glass;
5) growing soft Si3N4 by adopting PECVD after sintering in the step 4); the working condition of the PECVD is 380-420 ℃,
6) carrying out secondary photoetching and Ni plating, then plating Ni-Si alloy, and plating Ni again after the Ni-Si alloy is plated;
7) testing;
8) and (4) back laser scribing.
2. The method of claim 1, wherein the step 4) is performed by sintering glass at 820 ℃ to 850 ℃ under N2+ O2.
3. The GPP chip preparation method of claim 1, wherein in the step 6), Ni-Si alloy is plated at 580-620 ℃ under N2+ H2.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103730430A (en) * | 2013-12-16 | 2014-04-16 | 启东吉莱电子有限公司 | Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
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| JPS62114233A (en) * | 1985-11-13 | 1987-05-26 | Nec Corp | Semiconductor device strengthened in radiation resistance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103730430A (en) * | 2013-12-16 | 2014-04-16 | 启东吉莱电子有限公司 | Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
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