CN108573857A - High reliability GPP chip preparation method - Google Patents
High reliability GPP chip preparation method Download PDFInfo
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- CN108573857A CN108573857A CN201810399395.5A CN201810399395A CN108573857A CN 108573857 A CN108573857 A CN 108573857A CN 201810399395 A CN201810399395 A CN 201810399395A CN 108573857 A CN108573857 A CN 108573857A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a kind of high reliability GPP chip preparation methods, include the following steps：1) photoresist will be coated on the PN junction silicon chip spread；2) HF is used:HNO3:The corrosive liquid of HAC mixing carries out erosion grooves；3) it carries out mixing oxygen nitrating in the trench using LPCVD growth patterns；4) glassing, sintered glass are scraped；5) soft Si is grown using PECVD after step 4) sintering3N4；6) it carries out secondary photoetching and plates Ni, then plate Ni Si alloys, Ni is plated again after having plated Ni Si alloys；7) it tests；8) backside laser scribing.The present invention grows tufftride silicon (Si in glass surface PECVD3N4), to form good low-leakage current, high pressure, moisture resistance, high reliability 1A~50A of low stress and 300~1800V GPP chips, have many advantages, such as that wide adaptation range, low cost, stability are good and highly reliable.
Description
Technical field
The present invention relates to technology of semiconductor chips fields, and in particular to a kind of high reliability glassivation (GPP) chip system
Preparation Method.
Background technology
GPP (glassivation) chip is the mainstream of current new and high technology.GPP techniques are divided into three kinds of process implementation methods：①
Knife scraping method 2. light blockage method 3. electrophoresis, however these three methods have advantage and disadvantage, knife scraping method is at low cost but electric leakage is uneven；Photoresist
Though method parameter consistency is preferably but cost is higher；Electrophoresis one-time investment is big, and environmental protection is of high cost, and waste is not disposable.
Higher and higher to the requirement of semiconductor surface passivation at present, GPP chip should have：1, good electric property and can
By property, including resistivity, dielectric strength, ionic mobility etc., the introducing of material should not bring side effect to device；Second is that good
Chemical stability, have certain resistance to chemical attack；Third, operability, simple for process, reproducible, energy and device
Manufacturing process is compatible, and the coefficient of expansion of material is consistent or close with silicon materials；Fourth, economy, can be mass-produced, system
It causes originally to want low, there is the market competitiveness, material and technique to have powerful vitality and potentiality to be exploited.However present side on the market
There is this or that in GPP chip prepared by method, cannot meet the needs.
Invention content
The purpose of the present invention is provide regarding to the issue above it is a kind of it is at low cost, can large-scale batch production, stability it is good,
High reliability glassivation (GPP) chip preparation method.
Realizing the technical solution of the purpose is：
A kind of high reliability GPP chip preparation method, includes the following steps：
1) photoresist will be coated on the PN junction silicon chip spread；
2) HF is used:HNO3:The corrosive liquid of HAC mixing carries out erosion grooves；
3) it carries out mixing oxygen nitrating in the trench using LPCVD growth patterns；
4) glassing, sintered glass are scraped；
5) soft Si is grown using PECVD after step 4) sintering3N4；
6) it carries out secondary photoetching and plates Ni, then plate Ni-Si alloys, Ni is plated again after having plated Ni-Si alloys；
7) it tests；
8) backside laser scribing.
HF in the step 2):HNO3:The volume ratio of HAC is 0.8~1.2:0.8~1.2:1.8~2.2, the HF,
HNO3, HAC mass fraction concentration be respectively 40~45%, 83~93%, 33~45%.
The step 3) uses LPCVD growth patterns to carry out mixing the condition of oxygen nitrating in the trench as 650 DEG C~750 DEG C,
The step 4) is at 820 DEG C~850 DEG C, N2+O2Under the conditions of be sintered glass；
The operating condition of the step 5) PECVD is 380 DEG C~420 DEG C,
In 580~620 DEG C, N in the step 6)2+H2Under the conditions of plate Ni-Si alloys.
The beneficial effects of the invention are as follows：By mixing oxygen doped polysilicon with LPCVD growths in exposed groove；Knife is used again
Scrape method coating glass powder；Tufftride silicon (Si is grown in glass surface PECVD3N4), to form low-leakage current, high pressure, moisture resistance
Moist good, low stress high reliability 1A~50A and 300~1800V GPP chip, have wide adaptation range, low cost, can
The advantages that large-scale mass production, stability are good and highly reliable.
Specific implementation mode
With reference to embodiment, the invention will be further described, but not thereby limiting the invention.
Experimental method in following embodiments is unless otherwise instructed conventional method.
Embodiment 1 prepares highly reliable glassivation (GPP) chip
Highly reliable glassivation (GPP) chip is prepared, is operated in accordance with the following steps：
1) it is photoetching of 350~450cps in PN junction (P-N--N+) the silicon chip stickiness laid on spread
Glue；
2) and then using HF by volume:HNO3:HAC=1:1:2 proportioning corrosive liquids carry out low under the conditions of 2 DEG C~10 DEG C
The mass fraction concentration of warm erosion grooves, HF, HNO3, HAC is respectively 42%, 88%, 38%.
3) use LPCVD (650 DEG C~750 DEG C,) growth pattern carries out mixing oxygen nitrating in the trench；
4) glassing is scraped on the basis of step 3), and (820 DEG C~850 DEG C, N2+O2) under the conditions of be sintered glass
Glass；
5) the glass powder surface of step 4) using PECVD (380 DEG C~420 DEG C,) growth it is soft
Si3N4；
6) secondary light quarter is carried out afterwards in step 5) and plate Ni, then in 580~620 DEG C, N2+H2Under the conditions of plate Ni-Si conjunction
Gold then carries out plating Ni again；
7) it tests；
8) backside laser scribing.
The GPP chip being prepared has following features after testing：
A, because of the soft SI on surface3N4Moisture resistance is good, can stably reach PCT 96Hrs abilities；
B, due to the good transition between SIPOS films and SI substrates, the electric leakage of P/N knots it is extremely low can reach Ir≤
0.2uA, especially 150 DEG C of high temperature, Ir≤20uA；
C, the refractive index of three layers of passivating structure composite membrane is different, can be widely used for anti-external electrical radiation and single-particle radiation
The specific uses such as interference.
The present invention using PECVD (380 DEG C~420 DEG C,) the soft Si of growth3N4, so that chip is had stronger
Radioresistance and anti-particle interference performance, while the manufacture craft is at low cost, can large-scale batch production, chip obtained
Stability is good, reliability is high.
Claims (6)
1. a kind of high reliability GPP chip preparation method, which is characterized in that include the following steps：
1) photoresist will be coated on the PN junction silicon chip spread；
2) HF is used:HNO3:The corrosive liquid of HAC mixing carries out erosion grooves；
3) it carries out mixing oxygen nitrating in the trench using LPCVD growth patterns；
4) glassing, sintered glass are scraped；
5) soft Si is grown using PECVD after step 4) sintering3N4；
6) it carries out secondary photoetching and plates Ni, then plate Ni-Si alloys, Ni is plated again after having plated Ni-Si alloys；
7) it tests；
8) backside laser scribing.
2. high reliability GPP chip preparation method as described in claim 1, which is characterized in that HF in the step 2):HNO3:
The volume ratio of HAC is 0.8~1.2:0.8~1.2:1.8~2.2, described HF, HNO3, HAC mass fraction concentration be respectively 40
~45%, 83~93%, 33~45%.
3. high reliability GPP chip preparation method as described in claim 1, which is characterized in that the step 3) uses LPCVD
The condition that growth pattern carries out mixing oxygen nitrating in the trench is 650 DEG C~750 DEG C,
4. high reliability GPP chip preparation method as described in claim 1, which is characterized in that the step 4) 820 DEG C~
850 DEG C, N2+O2Under the conditions of be sintered glass.
5. high reliability GPP chip preparation method as described in claim 1, which is characterized in that the work of the step 5) PECVD
It is 380 DEG C~420 DEG C to make condition,
6. high reliability GPP chip preparation method as described in claim 1, which is characterized in that in the step 6) 580~
620℃、N2+H2Under the conditions of plate Ni-Si alloys.
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| CN201810399395.5A CN108573857B (en) | 2018-04-28 | 2018-04-28 | High-reliability GPP chip preparation method |
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| CN201810399395.5A CN108573857B (en) | 2018-04-28 | 2018-04-28 | High-reliability GPP chip preparation method |
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| CN108573857A true CN108573857A (en) | 2018-09-25 |
| CN108573857B CN108573857B (en) | 2020-11-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786295A (en) * | 2019-01-11 | 2019-05-21 | 电子科技大学 | Grooved glass passivation system and corresponding passivation technology using 3D rubbing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62114233A (en) * | 1985-11-13 | 1987-05-26 | Nec Corp | Semiconductor device strengthened in radiation resistance |
| CN103730430A (en) * | 2013-12-16 | 2014-04-16 | 启东吉莱电子有限公司 | Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
-
2018
- 2018-04-28 CN CN201810399395.5A patent/CN108573857B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62114233A (en) * | 1985-11-13 | 1987-05-26 | Nec Corp | Semiconductor device strengthened in radiation resistance |
| CN103730430A (en) * | 2013-12-16 | 2014-04-16 | 启东吉莱电子有限公司 | Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786295A (en) * | 2019-01-11 | 2019-05-21 | 电子科技大学 | Grooved glass passivation system and corresponding passivation technology using 3D rubbing method |
| CN109786295B (en) * | 2019-01-11 | 2023-09-12 | 电子科技大学 | Groove glass passivation system adopting 3D coating method and corresponding passivation process |
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| CN108573857B (en) | 2020-11-10 |
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