CN106716612A - 安装基板和制造安装基板的方法 - Google Patents

安装基板和制造安装基板的方法 Download PDF

Info

Publication number
CN106716612A
CN106716612A CN201580048381.3A CN201580048381A CN106716612A CN 106716612 A CN106716612 A CN 106716612A CN 201580048381 A CN201580048381 A CN 201580048381A CN 106716612 A CN106716612 A CN 106716612A
Authority
CN
China
Prior art keywords
scaling powder
solder projection
solder
installation base
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201580048381.3A
Other languages
English (en)
Other versions
CN106716612B (zh
Inventor
足立研
松本治
松本一治
儿玉健
冈修
冈修一
大鸟居英
斋藤成
斋藤一成
佐藤圭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of CN106716612A publication Critical patent/CN106716612A/zh
Application granted granted Critical
Publication of CN106716612B publication Critical patent/CN106716612B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05566—Both on and outside the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/82051—Forming additional members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/82399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

根据本技术的一个实施例的制造安装基板的方法包括以下三个步骤：(1)在半导体层上形成多个电极并且然后在面对电极的每个位置处形成一个焊料凸块的步骤；(2)利用涂层覆盖所述焊料凸块并且使用涂层作为掩模选择性地蚀刻半导体层以将半导体层分离成多个元件的步骤；(3)去除涂层并且然后将多个元件安装在布线基板上以便焊料凸块面向布线基板从而形成安装基板的步骤。

Description

安装基板和制造安装基板的方法
技术领域
本技术涉及其中元件安装在布线基板上的安装基板以及制造安装基板的方法。
背景技术
在元件安装在布线基板上时，具体地，为了安装大量的精细元件，需要以高精度将元件安装在布线基板上。因此，已经提出了在布线基板上安装元件的各种技术(参考专利文献1)。
现有技术文献
专利文献
专利文献1：特开2013-232667号公报
发明内容
当大量精细元件安装在布线基板上时，小元件尺寸或元件之间的小间隙尺寸会导致各种故障。
因此，期望提供一种安装基板及其制造方法，其允许减少由小元件尺寸或小间隙尺寸导致的精细元件安装的故障。
根据本技术的第一实施例的制造安装基板的方法包括以下三个步骤：
(A1)第一步骤，在半导体层上形成多个电极，并且然后在与每个电极相对的位置形成焊料凸块；
(A2)第二步骤，用涂层覆盖所述焊料凸块，并然后使用所述涂层作为掩模选择性地蚀刻所述半导体层，以将所述半导体层分离成多个元件；以及
(A3)第三步骤，去除涂层，并然后将元件安装在布线基板上以使焊料凸块朝向布线基板，从而形成安装基板。
在根据本技术的第一实施例的制造安装基板的方法中，使用覆盖焊料凸块的涂层作为掩模进行元件分离。这使得可以最小化焊料凸块被暴露的情况。顺便提及，在元件尺寸小的情况下，焊料凸块的尺寸也小。因此，容易发生由焊料凸块的表面氧化引起的接合故障。但是，在本技术中，使焊料凸块露出的情况被最小化，从而抑制焊料凸块的表面氧化。因此，抑制了焊料凸块的接合故障。
根据本技术的第二实施例的制造安装基板的方法包括以下三个步骤：
(B1)第一步骤，在支撑基板上形成多个电极，在包括各个电极的表面上形成籽晶层，并且在籽晶层的面向相邻的两个电极之间的部分的部分中形成贯通凹槽；
(B2)第二步骤，在面对每个电极的位置处形成电耦接至籽晶层的多个焊料凸块中的一个；以及
(B3)第三步骤，使用所述贯通凹槽将所述籽晶层分离为多个籽晶部分，然后，使用其间的一个或多个所述焊料凸块将多个元件安装在支撑基板上。
在根据本技术的第二实施例的制造安装基板的方法中，在形成焊料凸块之前，在籽晶层的面向相邻的两个电极之间的部分的部分中形成贯通凹槽。顺便提及，在形成焊料凸块之后在籽晶层中形成上述贯通凹槽的情况下，例如，需要用涂层涂覆各个焊料凸块，在涂层中形成具有大长宽比的凹槽，并且通过所述凹槽蚀刻所述籽晶层。在元件之间的间隙尺寸小的情况下，槽的宽度也小；因此，难以蚀刻籽晶层。但是，在本技术中，在形成焊料凸块之前在籽晶层中形成上述通槽，这使得可以容易地蚀刻籽晶层。
根据本技术的实施例的安装基板包括：布线基板；多个元件，每个元件布置于面对所述布线基板的顶表面的位置处；以及多个焊料凸块，一个或多个焊料凸块设置在所述布线基板和每个所述元件之间，以将所述布线基板和每个所述元件彼此电耦接。每个元件包括：半导体层，一个或多个电极，设置成与所述半导体层的底表面的一部分接触，和绝缘层，设置成与所述半导体层的底表面的除了一个或多个电极之外的整个部分接触，而不与所述半导体层的侧表面接触。
在根据本技术的实施例的安装基板中，绝缘层被设置成与所述半导体层的底表面的除了一个或多个电极之外的整个部分接触，而不与所述半导体层的侧表面接触。例如，这里假设由元件和焊料凸块配置的复合元件安装在涂覆有助焊剂的布线基板上，以使焊料凸块朝向布线基板，从而制造本技术的安装基板。在这种情况下，例如，使用例如覆盖焊料凸块的涂层作为掩模来选择性地蚀刻由半导体层、绝缘层和籽晶层配置的堆叠体，直到穿透所述堆叠体，这使得可以形成各个元件。在以这种方式形成各个元件的情况下，与半导体层、绝缘层和籽晶部分用不同的掩模选择性地蚀刻的情况相比，减小了焊料凸块的芯与元件的芯之间的未对准。在焊料凸块的芯与元件的芯之间的未对准较大的情况下，安装位置的精度容易降低。特别是，在元件的尺寸小的情况下，除了安装位置精度的大幅降低之外，元件更倾向于以倾斜状态安装。但是，在本技术中，由于焊料凸块的芯与元件的芯之间的未对准很小，因此安装位置的精度非常高，并且元件以倾斜状态安装的可能性非常低。
根据本技术的第一实施例的制造方法，即使元件尺寸小，也可以抑制由焊料凸块的表面氧化引起的接合故障，这使得可以抑制由小元件尺寸造成的故障。应当注意，这里描述的效果是非限制性的，并且可以是本技术中描述的效果中的一个或多个。
根据本技术的第二实施例的制造安装基板的方法，即使元件之间的间隙尺寸小，也可以容易地蚀刻籽晶层，这使得可以抑制由元件之间小间隙引起的故障。应当注意，这里描述的效果是非限制性的，并且可以是本技术中描述的效果中的一个或多个。
根据本技术的实施例的安装基板，可以减少安装位置的精度的降低以及即使元件尺寸小元件以倾斜状态安装的可能性，这使得可以抑制由小元件尺寸引起的故障。应当注意，这里描述的效果是非限制性的，并且可以是本技术中描述的效果中的一个或多个。
附图说明
[图1]是示出根据本技术的第一实施例的安装基板的顶部配置的实例的图。
[图2]是示出沿图1的安装基板的线A-A截取的横截面配置的实例的图。
[图3]是示出沿图1的安装基板的线B-B截取的横截面配置的实例的图。
[图4]是示出图1的安装基板的制造工序的实例的流程图。
[图5]是布线基板的配置的实例的横截面图。
[图6]是接着图5的工序的横截面图。
[图7]是接着图6的工序的横截面图。
[图8A]是接着图7的工序的横截面图。
[图8B]是示出图8A的平面配置的实例的图。
[图9]是接着图8A的过程的横截面图。
[图10]是接着图9的过程的横截面图。
[图11A]是接着图10的过程的横截面图。
[图11B]是示出图8A的平面配置的实例的图。
[图12]是接着图11A的过程的横截面图。
[图13]是接着图12的过程的横截面图。
[图14]是示出干燥期间、预加热期间和回流期间的温度的实例的图。
[图15]是接着图13的过程的横截面图。
[图16]是接着图15的过程的横截面图。
[图17]是接着图16的过程的横截面图。
[图18]是接着图17的过程的横截面图。
[图19]是示出根据本技术的第二实施例的安装基板的顶部配置的实例的图。
[图20]是示出沿图19的安装基板的线A-A截取的横截面配置的实例的图。
[图21]是示出沿图19的安装基板的线B-B截取的横截面配置的实例的图。
[图22]是示出图19的安装基板的制造过程的实例的流程图。
[图23]是布线基板的配置的实例的横截面图。
[图24]是接着图23的过程的横截面图。
[图25]是接着图24的过程的横截面图。
[图26]是接着图25的过程的横截面图。
[图27]是接着图26的过程的横截面图。
[图28]是接着图27的过程的横截面图。
[图29]是示出由元件和焊料凸块配置的复合元件的制造工序的实例的流程图。
[图30]是元件基板的配置的实例的横截面图。
[图31]是接着图30的过程的横截面图。
[图32]是接着图31的过程的横截面图。
[图33]是接着图32的过程的横截面图。
[图34]是接着图33的过程的横截面图。
[图35]是接着图34的过程的横截面图。
[图36]是接着图35的过程的横截面图。
[图37]是接着图36的过程的横截面图。
[图38]是示出根据本技术的第三实施例的电子设备的示意性配置的实例的图。
具体实施方式
在下文中，参考附图详细描述本技术的一些实施例。应注意，按照以下列顺序给出描述。
1.第一实施例(安装基板)
在形成凸块之前去除电极之间的籽晶层的实例
在布线基板上设置凸块之后进行安装的实例
2.第二实施例(安装基板)
使用覆盖凸块的光致抗蚀剂作为掩模进行元件分离的实例
在元件上设置凸块之后进行安装的实例
3.各实施例的通用变形实例(安装基板)
4.第三实施例(电子设备)
将根据上述实施例中的任一个的安装基板安装在电子设备中的实例
<1.第一实施例>
【配置】
首先，对根据本技术的第一实施例的安装基板1进行说明。图1示出了安装基板1的顶部配置的实例。图2示出了沿着安装基板1的线A-A截取的横截面配置的实例。图3示出了沿着安装基板1的线B-B截取的横截面配置的实例。安装基板1包括布线基板10、多个元件20和多个焊料凸块30。在安装基板1中，可利用其间的焊料凸块30安装布线基板10上的元件20。布线基板10通过焊料凸块30电耦接至各个元件20。
(布线基板10)
布线基板10可包括支撑基板11、多个电极焊盘12、多个电极焊盘13、绝缘层14和多个布线15。例如，可为每个元件20分配电极焊盘12中的一个、电极焊盘13中的一个和配线15中的一个。
支撑基板11可支撑多个元件20。支撑基板11可由例如硅基板、玻璃基板、石英基板或树脂基板构成。
电极焊盘12可形成为例如与支撑基板11接触。电极焊盘12可置于焊料凸块30的正下方，并且可与焊料凸块30接触。电极焊盘12可通过焊料凸块30电耦接至元件20的电极22(稍后描述)。多个电极焊盘12可以以与元件20的布置节距相同的布置节距来设置。
电极焊盘12分别可由在支撑基板11上依次堆叠的电极12A、籽晶部分12B和屏障部分12C配置。电极12A可形成为与支撑基板接触并且可置于面向焊料凸块30的位置处。电极12A可设置于面向绝缘层14的孔径14A(将在后面描述)的位置处。电极12A的顶表面可暴露在孔径14A中。电极12A可由例如诸如铜和铝的布线材料制成。例如，籽晶部12B可形成为与包括电极12A的顶表面的绝缘层14的顶表面的一部分接触。籽晶部12B可在电解电镀期间用作电极层。籽晶部12B可由例如按照该顺序堆叠的钛和铜配置。相邻的两个籽晶部12B之间的间隙可比例如焊料凸块30的尺寸(例如，约15μm的直径)窄，并且可例如为约2μm。屏障部分12C可形成为与籽晶部12B接触，并且可置于面对焊料凸块30的位置。屏障部分12C可以是例如用作焊料凸块30的基底的UBM(凸块下金属)。UBM可由例如镍制成，并且可用作焊料扩散抑制层。
电极焊盘13可例如与电极焊盘12一样形成为与支撑基板11接触。电极焊盘13可分贝设置于面向绝缘层的孔径14B(稍后描述)的位置处。每个电极焊盘13的顶表面可暴露在孔径14B中。电极焊盘13可设置于与焊料凸块30正下方不同的位置，并且可通过布线15电耦接至元件20的电极24(将在后面描述)。电极焊盘13可由，例如，诸如铜和铝的布线材料制成。
绝缘层14可在面对各个电极焊盘12的位置处具有孔径14A，并且可在面对各个电极焊盘13的位置处具有孔径14B。电极12A可设置于面对各个孔径14A的位置处。电极焊盘13可设置于面向孔径14B的位置。绝缘层14只要具有作为安装基板1所需的电特性和可靠性，并且能够承受焊料回流温度即可。绝缘层14可由例如玻璃环氧树脂、阻焊剂、聚酰亚胺、二氧化硅或氮化硅制成。
布线15可每个将电极焊盘13和电极24彼此电耦接。布线15可由例如诸如铜和铝的布线材料制成。布线15可置于中间而不接触元件20的侧表面。应当注意，安装基板1可包括嵌入层，嵌入例如各个元件20和布线15。
(元件20)
多个元件20可置于面对布线基板10的顶表面的位置。元件20可用其间的焊料凸块30例如从元件基板转移到布线基板10上。可替代地，元件20可通过除转移之外的方法(例如，安装器)安置在焊料凸块30上。元件20可在平面中彼此分开地安置。元件20每个可以是例如亚毫米尺寸的芯片。元件20每个可以是用作例如设备和电子电路的组成元件的单独组件，并且可以是芯片状组件。元件20每个可以是例如发光元件(诸如LED(发光二极管)，LD(激光二极管)和有机EL元件)，光接收元件(诸如PD(光电二极管))或电路元件(诸如电容器、晶体管、电阻器、IC(集成电路)和LSI(大规模集成))。此外，元件20可每个包括上述发光元件、光接收元件和电路元件中的两个或更多个。
元件20可分别包括例如布置在半导体层21的底表面上的半导体层21、电极22和绝缘层23，并且电极24和绝缘层25布置在半导体层21的顶表面上，如图2所示。可替代地，元件20可分别包括在半导体层24的底表面上的电极22和电极24。可替代地，元件20可分别包括在半导体层21的底表面上的多个电极22。下面的描述给出了元件20每个在半导体层21的底表面和顶表面上包括一个电极22和一个电极24的情况。
半导体层21可以是具有上述示例的元件20的功能的部分，并且可包括例如LED、LD，有机EL元件、PD，电容、晶体管、电阻器、IC或LSI。
电极22可布置为与半导体层21的底表面的一部分接触。电极22可使半导体层21和焊料凸块30彼此电耦接。注意，在元件20中的每一个包括多个电极22的情况下，一些电极22可以是无助于半导体层21的功能的虚拟件。在这种情况下，虚拟电极22和置于虚拟电极22上的焊料凸块30可用作由金属制成的突起。突起可确保元件20的稳定性。
电极22可由例如从半导体层21侧依次堆叠的电极22A、籽晶部分22B和屏障部分22C构成。电极22A可设置为与半导体层21的底表面的一部分接触，并且可置于面向绝缘层23的孔径的位置。籽晶部分22B可在电镀期间用作电极层。籽晶部分22B可由例如按照该顺序堆叠的钛和铜配置。籽晶部分22B可设置为与电极22A和绝缘层23接触。籽晶部分22B可电耦接至电极22A、屏障部分22C和焊料凸块30。屏障部分分22C可以是UBM(凸块下金属)。
绝缘层23可在面向电极22A的位置处具有孔径。电极22A可暴露在绝缘层23的孔径中。绝缘层23可设置成与半导体层21的底表面的不与电极22A接触的整个部分接触，并且与半导体层21的侧面接触。绝缘层23可由例如二氧化硅或氮化硅制成。
电极24可使半导体层21和电极15彼此电耦接。电极24可设置成与半导体层21的顶表面的一部分接触，并且可设置于面向绝缘层25的孔径的位置。绝缘层25可在面向电极的位置处具有孔径。绝缘层25可由例如氧化硅或氮化硅制成。
(焊料凸块30)
多个焊料凸块30中的一个或多个可设置在布线基板10和每个元件20之间。更具体地，焊料凸块30中的一个可设置在面向每个电极22的位置。焊料凸块30可使布线基板10和元件20彼此电耦接。注意，在每个元件20中的一些电极22是虚拟电极的情况下，与虚拟电极22接触的焊料凸块30可各自用作由金属制成的突起，其确保元件20的稳定性。焊料凸块30中的每一个的直径可例如小于所谓的微凸块的尺寸，即，例如，大约15μm。焊料凸块30的高度可优选为不使电极焊盘12与元件20的电极22直接接触的高度，即，例如为约5μm。相邻的两个焊料凸块30之间的间隙可例如比每个焊料凸块30的尺寸(例如，约15μm的直径)更窄，即例如约10μm。焊料凸块30可由例如包括锡和银的合金制成，并且可通过例如电解电镀形成。
【制造方法】
接着，对安装基板1的制造方法的实例进行描述。
图4示出了制造安装基板1的工序的示例的流程图。图5至图13以及图15至图18分别示出了安装基板1的制造工序的实例的横截面图。图14示出了干燥期间、预热期间和回流期间的温度的实例。
首先，可以在支撑基板11上形成多个电极12A(步骤S101，图5)。接下来，可在包括各个电极12A的整个表面上形成绝缘层14，然后可在与每个电极12A的顶表面相对的位置处形成孔径14A(图6)。因此，每个电极12A可暴露在每个孔径14A中。此后，可通过例如溅射在包括各个电极12A的整个表面上形成籽晶层12B’(步骤S102，图7)。
接下来，可在整个表面上形成光致抗蚀剂层110，然后，可在光致抗蚀剂层110的面对相邻的两个电极12A之间的部分中形成凹槽110A(参见图8A和图8B)。凹槽110A可以是穿透光致抗蚀剂层110的贯通凹槽。接下来，可使用光致抗蚀剂层110作为掩模来选择性地蚀刻籽晶层12B’。更具体地，可蚀刻籽晶层12B’的面向相邻两个电极12A之间的部分的部分。因此，可在籽晶层12B’的与相邻的两个电极12A之间的部分相对的部分中形成穿透籽晶层12B’的贯通凹槽12-1(步骤S103，图8A和图8B)。例如，过氧化氢-磷酸基水溶液可用作其中籽晶层12B’由铜制成的部分的蚀刻剂。例如，可将氟基化合物用作其中籽晶层12B’由钛制成的部分的蚀刻剂。
接下来，在去除光致抗蚀剂层110之后，可在整个表面上形成光致抗蚀剂层120，并且可在光致抗蚀剂层120的与每个电极12A相对的部分中形成孔径120A(图9)。接着，可使用例如电解电镀法形成屏障部分(barrier section)12C和焊料凸块30。更具体地，可使用电解电镀法在每个孔径120A中暴露的籽晶层12B’上依次形成屏障部分12C和每个焊料凸块30(步骤S103，图10)。因此，多个屏障部分12C中的一个和电耦接至籽晶层12B’的多个焊料凸块30中的一个可形成在面对每个电极12A的位置处。此外，各个焊料凸块30可使用电解电镀方法形成，以使各个焊料凸块30的顶表面成为平坦表面30A。各平坦表面30A在后面的过程中分别具有作为安装表面的作用。
顺便提及，在使用电解电镀方法形成多个焊料凸块30的情况下，除了形成焊料凸块30之外，焊料凸块30可优选地在通电状态下从电镀槽提起。换句话说，即使在电镀结束时，也可优选地继续通电。此后，可去除光致抗蚀剂层120。因此，可形成布线基板10，并且可在布线基板10上形成焊料凸块30。随后，为了防止在各个焊料凸块30的表面上的氧化的进行，可将光致抗蚀剂层150涂布到包括各个焊料凸块30的整个表面，直到执行施加后述的焊剂130的过程(参照图11A)。在这种情况下，可使用光致抗蚀剂层150作为掩模选择性地进一步蚀刻籽晶层12B’，以使贯通凹槽12-1彼此连通，从而将籽晶层12B’分离成多个籽晶部分12B。例如，首先，可在包括面对光致抗蚀剂层150的贯通凹槽12-1的端部的部分的部分中形成凹槽150A(参照图11B)。例如，凹槽150A可具有围绕面向电极12A的部分的栅格形状。接下来，可通过凹槽150A选择性地蚀刻籽晶层12B’。因此，可使用各个贯通凹槽12-1将籽晶层12B’分离成多个籽晶部12B。在这种情况下，籽晶部12B中的一个可设置在面对每个电极12A的位置。
接下来，在去除光致抗蚀剂层150之后，可将助焊剂(flux)130涂布到包括各个焊料凸块30的整个表面上(图12)。助焊剂130可在保持元件20和改善焊料可润湿性方面起作用。
在焊料凸块30的尺寸小于微凸块并且分配给一个元件20的焊料凸块30的数量为两个或更少的情况下，元件20非常难以在将元件20安装在焊料凸块30上直到执行回流的时间段中保持自立(self-standing)。因此，对助焊剂130赋予高粘度以确保元件20通过助焊剂130的自立，从而防止元件20的位移。这里，助焊剂130的适当粘度可在约50Pa·s至1000Pa·s包括这二者。可通过元件20的形状和尺寸，焊料凸块30的状态和任何其它因素来选择适当的粘度。存在一些涂布助焊剂130的方法，诸如旋涂、喷涂、刮刀、狭缝涂布机和焊剂片。焊剂130可通过上述任何方法涂布。
接下来，在涂布了焊剂130的状态下，多个元件20中的每一个可利用其间的一个或多个焊料凸块30安装在布线基板10上(步骤S105，图13)。例如，多个元件20可利用其间的焊料凸块30被转移到布线基板10上。可替代地，元件20可通过除了转移之外的方法安装在焊料凸块30上。接着，进行干燥，然后进行预热和回流(步骤S106)。包括干燥、预热和回流的加热过程可在回流炉中进行。可替代地，可在回流炉外部进行干燥，并且可在回流炉中进行预热和回流。可不必在执行干燥之后立即在布线基板10上执行预热。经过干燥的布线基板10可存储在预定的存储位置，之后可进行预热。预热和回流可优选在回流炉中连续进行。应当注意，在执行预热和回流而不进行干燥的情况下，不会引起问题，可省略干燥。
图14示出了如上所述的干燥期间、预热期间和回流期间的温度的实例。在执行安装之后，依次经过干燥时间段Δt3，预热时间段Δt4和回流时间段Δt5。干燥时间段Δt3可以是在进行安装之后，在低于焊剂130的软化点T1的温度下加热助焊剂130以使助焊剂130中包含的溶剂挥发的时间段(助焊剂130被干燥的时间段)。干燥时间段Δt3对应于助焊剂固相时间段Δt1的部分。预热时间段t4可以是其中助焊剂130在高于助焊剂130的软化点T1并且低于焊料凸块30的熔点(焊料熔点T2)的温度下被加热以活化助焊剂130的时间段，并且挥发例如包含在助焊剂130中的松香。通过挥发例如助焊剂130中包含的松香来降低助焊剂130的液面。回流时间段Δt5可以是执行回流(reflow)的时间段。预热时间Δt4和回流时间Δt5对应于助焊剂液相时间段Δt2中的部分。因此，在执行安装之后，可在低于待干燥的助焊剂130的软化点T1的温度下加热助焊剂130，然后可在高于助焊剂130的软化点T1且低于焊料凸块30的熔点(焊料熔点T2)的温度下加热焊剂130，以活化助焊剂130并降低助焊剂130的液面。之后，可进行回流。
在本实施例中，通过提供干燥时间段Δt3，例如在比助焊剂130的软化点T1低的温度下使溶剂缓慢挥发，使助焊剂130干燥，从而固定元件20。
根据助焊剂130的组成，存在元件20在干燥期间移动的可能性。在为了追求粘度而使用具有高粘度和低挥发性的溶剂的情况下，当助焊剂130被强制挥发，助焊剂130可能引起对流，这导致元件20的移动。因此，有必要充分考虑溶剂的选择，并且重要的是适当地设定助焊剂130的干燥温度、助焊剂130的溶剂的蒸汽压力、助焊剂130的固体比率和任何其它因素。特别地，在通过例如旋涂或喷涂涂布具有低粘度的助焊剂130之后，助焊剂130的粘度增加至用于保持元件20的合适的粘度，并且助焊剂130在安装之后被干燥，助焊剂130与在每个步骤中的温度或压力下立即挥发而不引起对流的溶剂混合可能是有效的。助焊剂130的溶剂没有特别规定；但是，诸如IPA或稀释剂的高挥发性溶剂可能不是优选的，因为这样的溶剂可在安装元件20的阶段中改变粘度或干燥。可优选使用在室温下具有温和挥发性并且在50℃至100℃的低温下具有不同且温和的蒸气压的多种溶剂的组合。干燥时间段Δt3中的干燥条件可通过助焊剂130和溶剂以及要安装的元件20之间的关系来确定。
此外，在本实施例中，在干燥期间Δt3结束后，依次进行预热和回流。
元件20和支撑基板10可通过回流过程利用在其间的焊料凸块30而接合在一起。回流轮廓可根据所使用的焊料适当设定。预热轮廓(profile)必须与助焊剂130的性能相匹配。首先，在典型的助焊剂中，在松香软化后，显示出活性的效果。因此，预热温度的下限必须超过松香的软化点。相反，已经保持元件20的助焊剂130可通过加热而软化或蒸发；但是，当松香的软化点高，助焊剂130不挥发，在回流期间重复对流而不显示为具有高粘度的粘性液体的效果。当在这种状态下温度达到焊料熔点T2时，助焊剂130可能导致元件结合性的降低。这可能导致安装故障，诸如接合故障、元件位移和元件倾斜。为了防止这种情况，助焊剂130可优选地减少(挥发)至一定的量，在该量下，助焊剂130稍稍覆盖焊料凸块30和电极22之间的接合表面30B直到到达焊料熔点T2。但是，在回流期间，助焊剂130的液面被定位在比焊料凸块30和元件20之间的接合表面30B高的位置是必要的(图15)。因此，预热温度的上限可由松香的种类(软化点)和松香的还原量决定。预热时间可优选设定为松香(助焊剂130)的量达到适当量的时间。
因此，助焊剂130可优选具有的不引起每个元件20偏离焊料凸块30(接合区)直到回流的完成的粘度。进一步地，助焊剂130可优选具有如下挥发性：所述助焊剂的液面在回流期间降低到获得自对准效果的范围内。
最后，可去除助焊剂130(图16)。此后，可形成光致抗蚀剂层140以便以穹顶状方式覆盖每个元件20(图17)。在这种情况下，可在与光致抗蚀剂层140的电极24相对的部分中提供孔径140A。接下来，布线15可提供在电极焊盘13、光致抗蚀剂层140和暴露的电极24的表面上在孔径140A中(图18)。可根据需要提供嵌入各个元件20的嵌入层。因此，可形成安装基板1。
【效果】
接着，对安装基板1的制造方法的效果进行描述。
在现有技术的籽晶金属的蚀刻中，在许多情况下，在形成焊料凸块之后，使用化学试剂，使用焊料凸块作为掩模选择性地去除籽晶金属。但是，籽晶金属形成在整个表面上，并且籽晶金属的许多部分应该被去除。因此，在选择性地蚀刻籽晶金属的同时，大大地去除籽晶金属的焊料凸块正下方的部分，并进行侧蚀刻。在焊料凸块具有大尺寸的情况下，侧蚀刻不会影响强度的可靠性；但是，在焊料凸块的尺寸例如小于30μm的情况下，侧蚀刻难以保持必要的强度。
因此，例如，焊料凸块被例如光致抗蚀剂覆盖，并且使用焊料凸块作为掩模执行蚀刻。这使得可防止在焊料凸块正下方的侧蚀刻。但是，例如，在焊料凸块之间的间隙窄到例如小于约30μm的情况下，可能极难形成覆盖焊料凸块的图案，并且蚀刻液可能不会充分展开。这可能导致应该从籽晶金属去除的部分不能完全移除。
相反，在本实施例中，在形成焊料凸块30之前，在籽晶层12B’的面对相邻的两个电极12A之间的部分中形成贯通凹槽12-1。这使得可容易地对籽晶层12B’执行蚀刻，即使元件20之间的间隙尺寸小。结果，可防止由元件20之间的小间隙尺寸导致的故障。
此外，在不进行通电的情况下进行诸如银的贵金属的电镀生长。因此，在通电结束后，从电镀槽提起焊料凸块30的情况下，优选地在焊料凸块30的表面上堆积银，使其表面富有银组成。在焊料凸块的体积大的情况下，焊料凸块中的表面部分的比例小，并且表面部分的组成变化的影响可忽略。但是，当焊料凸块的体积等于或小于微凸块的体积时，表面部分的组成变化的影响不可忽略，并且表面部分的组成变化显著影响焊料凸块的回流温度。
但是，在本实施例中，在形成焊料凸块30时，在通电状态下从电镀槽提升多个焊料凸块30的情况下(即，在继续通电的情况下即使在电镀结束时)，可以在如下的状态下完成电镀：焊料凸块30的表面中的金属组成比并不与焊料凸块30内的金属组成比不同。这使得可以降低发生回流故障的可能性。此外，在本实施例中，在使用电解电镀法形成各焊料凸块30的情况下，各焊料凸块30的顶表面成为平坦表面30A。因此，由于元件20的安装表面是平坦表面30A，所以与元件20安装在焊料球上的情况相比，可以降低元件20在焊料凸块30的顶表面上倾斜的可能性。这使得可以降低发生回流故障的可能性。
进一步地，在一般的焊料安装中，助焊剂130不被干燥。但是，如本实施例那样使用尺寸极小的焊料凸块30的情况下，当将涂覆有助焊剂130的焊料凸块30突然放入焊料回流炉中时，溶剂的快速挥发可能导致元件20的移动。因此，在本实施例中，在提供干燥时间段Δt3的情况下，溶剂在低于助焊剂130的软化点T1的温度下缓慢地挥发，从而使助焊剂130干燥，从而固定元件20。这使得可能防止元件20在预热期间和回流期间移动。因此，可以降低发生回流故障的可能性。另外，在本实施例中，在助焊剂130具有上述粘度和上述挥发度的情况下，可以将助焊剂130的液面130A降低至抑制由助焊剂130的对流引起的元件20的移动的程度。因此，可以在预热期间和回流期间抑制元件20的移动。
<2.第二实施例>
【配置】
接下来，对本技术的第二实施例的安装基板2进行描述。图19示出了安装基板2的顶部配置的实例。图20示出了沿着安装基板2的线A-A截取的横截面配置的实例。图21示出了沿着安装基板2的线B-B截取的横截面配置的实例。安装基板2可包括布线基板40、多个元件50和多个焊料凸块60。在安装基板2中，由元件50和焊料凸块60配置的多个复合元件可安装在布线基板40上，以将焊料凸块60引向布线基板40。布线基板40和每个元件50可通过一个或两个焊料凸块60彼此电耦接。
(布线基板40)
布线基板40可包括支撑基板41、多个电极焊盘42、多个电极焊盘43、绝缘层44和多个布线45。例如，可为每个元件50分配电极焊盘42中的一个、电极焊盘43中的一个和布线45中的一个。
支撑基板14可以支撑多个元件40。支撑基板41可由例如硅基板、玻璃基板、石英基板或树脂基板构成。
例如，电极焊盘42可形成为与支撑基板41接触。电极焊盘42可置于焊料凸块60的正下方，并且可与焊料凸块60接触。电极焊盘42可通过焊料凸块60电耦接至元件50的电极22。多个电极焊盘42可以与元件50的布置节距相同的布置节距设置。相邻的两个电极焊盘42之间的间隙可基本上等于或窄于例如焊料凸块60的尺寸(例如，直径约15μm)。
电极焊盘42可分别由在支撑基板41上依次堆叠的电极42A、屏障部分42B和电镀部分42C构成。电极42A可形成为与支撑基板41接触，并且可置于面向焊料凸块40的位置处。电极42A可置于面对绝缘层44的孔径44A(将在后面描述)的位置处。电极42A的顶表面可暴露在孔径44A。电极42A可由例如诸如铜和铝的布线材料制成。屏障部分42B可形成为与电极42A的顶表面的一部分接触。屏障部分42B可以是例如用作焊料凸块60的基底的UBM(凸块下金属)。UBM可由例如镍制成，并且可用作焊料扩散抑制层。电镀部分42C可形成为与例如屏障部分42B的顶表面接触。电镀部分42C可由例如金制成。
电极焊盘43可形成为与支撑基板41接触，例如，与电极焊盘42一样。电极焊盘43可每个置于面对绝缘层44的孔径44B(稍后描述)的位置处。每个电极焊盘43的顶表面可暴露在孔径44B中。电极焊盘43可安置在与焊料凸块60正下方的位置不同的位置，并且可通过布线45电耦接至元件50的电极24。电极焊盘43可由诸如铜和铝的布线材料制成。
绝缘层44可在面对各个电极焊盘42的位置处具有孔径44A，并且可在面对各个电极焊盘43的位置处具有孔径44B。电极42A可置于面对各个孔径44A的位置。电极焊盘43可置于面对相应的孔径44B的位置。绝缘层44只要具有作为安装基板2所需的并且能够承受焊料回流温度的电特性和可靠性即可。绝缘层44可由例如玻璃环氧树脂、阻焊剂、聚酰亚胺、二氧化硅或氮化硅制成。
布线45可每个将电极焊盘43和电极24彼此电耦接。布线45可置于中间而不接触元件50。应当注意，安装基板2可包括嵌入层，例如嵌入各个元件50和布线45。
(元件50)
多个元件50可置于面对布线基板40的顶表面的位置处。元件50可分别包括绝缘层53，以代替前述实施例的元件20中的绝缘层23。绝缘层53可在面向电极22A的位置处具有孔径。电极22A可暴露在绝缘层53的孔径中。绝缘层53可设置成与半导体层21的底表面的不与电极22A接触的整个部分接触，而不与半导体层21的侧表面接触。换句话说，半导体层21的侧表面和绝缘层23的侧表面可位于同一平面中。绝缘层23可由例如二氧化硅或氮化硅制成。
在每个元件50中，电极22可由例如从半导体层21侧依次堆叠的电极22A、籽晶部分22B和屏障部分22C构成。电极22A可设置成与半导体层21的底表面的一部分接触，并且可置于面向绝缘层53的孔径的位置。籽晶部分22B可在电镀期间用作电极层。籽晶部分22B可由例如按照该顺序堆叠的钛和铜配置。籽晶部分22B可提供为与电极22A和不包括绝缘层53的端部边缘的部分接触。籽晶部分22B可电耦接至电极22A、屏障部分22C和焊料凸块60。屏障部分22C可以是例如UBM(凸起下金属)。
(焊料凸块60)
多个焊料凸块60中的一个可设置在面对每个电极22的位置处。在为每个元件50设置一个电极22的情况下，可将焊料凸块60之一设置在布线基板40和每个元件50之间。在为每个元件50设置两个或更多个电极22的情况下，两个或更多个(与针对每个元件50提供的电极22的数量相同)焊料凸块60可设置在布线基板40和每个元件50之间。应当注意，在为每个元件50设置两个或更多个电极22的情况下，当每个元件50中的一些电极22是上述虚拟电极时，与虚拟电极22接触的焊料凸块60可每个用作由确保元件50的稳定性的金属制成的突起。每个焊料凸块60的直径可例如小于所谓的微凸块的尺寸，即，例如，大约15μm。焊料凸块60的高度可优选地为不使电极焊盘42与元件50的电极22直接接触的高度，即例如约5μm。焊料凸块60可由例如包括锡和银的合金制成，并且可通过例如电解电镀形成。
【制造方法】
接着，对安装基板2的制造方法进行描述。
图22示出了制造安装基板2的工序的实例的流程图。图23至图28每个示出了制造安装基板2的工序的实例的横截面图。
首先，多个电极42A可形成在支撑基板41上(参照图23)。接下来，可在包括各个电极42A的整个表面上形成绝缘层44，然后可在与每个电极42A的顶表面相对的位置处形成孔径(参见图23)。因此，每个电极42A可暴露在每个孔径中。此后，可通过例如电解电镀法在每个电极42A的顶表面上依次形成屏障部分42B和电镀部42C(参见图23)。因此，可形成布线基板40。
接下来，可将助焊剂210涂布到包括各个电极42的整个表面上(图23)。助焊剂210可在保持元件50和改善焊料润湿性方面起作用。
在焊料凸块60的尺寸小于微凸块并且分配给一个元件20的焊料凸块60的数量为两个或更少的情况下，元件50非常难以在将焊料凸块60在其上形成的元件50安装在电极焊盘上直到执行回流的时间段中保持自立。因此，对助焊剂210赋予高粘度以确保元件50通过助焊剂210的自立，从而防止元件50的位移。这里，助焊剂210的适当粘度可在约50Pa·s至1000Pa·s包括这二者。可通过元件50的形状和尺寸，焊料凸块60的状态和任何其它因素来选择适当的粘度。存在一些涂布助焊剂210的方法，诸如旋涂、喷涂、刮刀、狭缝涂布机和焊剂片。助焊剂210可通过上述任何方法涂布。
接着，将由元件50和焊料凸块60配置的复合元件安装在布线基板40上，以将焊料凸块60引向布线基板40(步骤S201，图24)。例如，由元件50和焊料凸块30配置的复合元件可被转移到布线基板10上。可替代地，上述复合元件可通过除转移之外的方法安装在布线基板10上。接着，与上述实施例同样地进行干燥，然后进行预热和回流(步骤S202)。应当注意，在执行预热和回流而不进行干燥的情况下，不会引起问题，可省略干燥。在进行安装之后，与前述实施例一样，可在低于待干燥的助焊剂130的软化点T1的温度下加热助焊剂130，之后，可在高于助焊剂130的软化点T1且低于焊料凸块60的熔点(焊料熔点T2)的温度下加热助焊剂130，以活化助焊剂130并降低助焊剂130的液面。之后，可执行回流。
在本实施例中，与前述实施例一样，元件50可通过提供干燥时间段Δt3固定，并且例如在低于助焊剂210的软化点T1的温度下温和地挥发溶剂，以干燥助焊剂210。
根据助焊剂210的组成，元件50有在干燥期间移动的可能性。在为了追求粘性而使用具有高粘度和低挥发性的溶剂的情况下，当助焊剂210被迫挥发时，助焊剂210可能引起对流，这导致元件50的移动。因此，需要充分考虑溶剂的选择，并且重要的是适当地设定助焊剂210的干燥温度、助焊剂210的溶剂、助焊剂210的固体比和任何其它因素。特别地，在通过例如旋涂或喷涂涂布具有低粘度的助焊剂210的情况下，助焊剂210的粘度增加至用于保持元件50的合适的粘度，并且助焊剂210在将助焊剂210与在每个步骤中的温度或压力下立即挥发而不引起对流的溶剂混合可能是有效的。助焊剂210的溶剂没有特别规定；但是，诸如IPA或稀释剂的高挥发性溶剂可能不是优选的，因为这样的溶剂可能在安装元件50的阶段中改变粘度或被干燥。可优选使用在室温下具有温和挥发性并且在50℃至100℃的低温下具有不同且温和的蒸气压的多种溶剂的组合。干燥时间段Δt3中的干燥条件可通过助焊剂210和溶剂以及待安装的元件50之间的关系来确定。
另外，在本实施例中，在干燥时间段Δt3结束后，依次进行预热(预热时间段Δt4)和回流(回流时间段Δt5)。在本实施例中，干燥时间段Δt3可以是在进行安装之后在低于助焊剂210的软化点T1的温度下加热助焊剂210以使助焊剂210中所含的溶剂挥发的时间段(助焊剂210被干燥的时间段)。在本实施例中，预热时间段Δt4可以是这样的时间段，在该时间段中，助焊剂210在高于助焊剂210的软化点T1并且低于焊料凸块的熔点(焊料熔点T2)的温度下被加热以活化助焊剂210并使例如包含在助焊剂210中的松香挥发。通过挥发例如助焊剂210中包含的松香来降低助焊剂210的液面。
元件50和支撑基板40可通过回流过程利用在其间的焊料凸块60而接合在一起。回流温度概况可根据所使用的焊料适当设定。预热概况需要与助焊剂210的性质相匹配。首先，在典型的助焊剂中，在松香软化之后表现出活性的效果。因此，预热温度的下限必须超过松香的软化点。相反，保持元件50的助焊剂130可通过加热而软化或蒸发；但是，当松香的软化点高时，助焊剂210不挥发，并且在回流期间作为具有高粘度的粘性液体重复对流。当在这种状态下温度达到焊料熔点T2时，助焊剂210可能导致元件50的接合性降低。这可能导致安装故障，诸如接合故障、元件位移和元件倾斜。为了防止这种情况，优选将助焊剂210减少(挥发)至这样的量，在该量下，助焊剂210稍微覆盖焊料凸块60与电极42之间的接合表面60A直到达到焊料熔点T2。但是，在回流时间段中，可能需要助焊剂210的液面位于比焊料凸块60和元件50之间的接合表面60A高的位置(图25)。因此，预热温度的上限可由松香的种类(软化点)和松香的还原量决定。预热时间可优选设定为松香(助焊剂210)的量达到适当量的时间。
因此，助焊剂210优选具有不使每个元件50偏离布线基板40上的电极焊盘42(接合区域)直到回流完成的粘度。进一步地，助焊剂210可优选具有如下的挥发性：助焊剂210的液面210A在回流期间降低到获得自对准效果的范围内。
最后，可以去除助焊剂210(图26)。之后，可以以穹顶状方式形成光致抗蚀剂层220以覆盖每个元件50(图27)。在这种情况下，可在与光致抗蚀剂层220的电极24相对的部分中提供孔径220A。接下来，可在电极焊盘43、光致抗蚀剂层220和暴露在孔径220A中的电极24的表面上提供布线45(图28)。可根据需要提供嵌入各个元件50的嵌入层。由此，形成安装基板2。
接下来，给出制造由元件50和焊料凸块60配置的复合元件的方法的实例的描述。
图29示出了制造复合元件的工序的实例的流程图。图30至图37各自示出了制造复合元件的过程的实例的横截面图。
首先，可制备元件基板300(图30)。元件基板300可包括半导体层21’，以及设置在半导体层21’的一个表面上的多个电极24和绝缘层25’。半导体层21’可在与电极24相对的每个位置处具有与半导体层21相同的配置。电极24可提供为与半导体层21’的一个表面接触。绝缘层25’可提供成与半导体层21’的一个表面接触，并且可在面向每个电极24的位置处具有孔径。绝缘层25’可由与绝缘层25相同的材料制成。
接下来，元件基板300可接合到支撑基板410(步骤S301，参照图31)。更具体地，元件基板300可通过其间的粘合剂层420接合到支撑基板410，以将元件基板300的电极24一侧引向支撑基板410。粘合剂层420可保持元件基板300和通过元件分离获得的多个复合元件。粘合层420可由例如BCB(苯并环丁烯)制成。接下来，可在元件基板300(半导体层21’)上形成多个电极22A(步骤S302)，并且可在元件基板300上形成绝缘层53’(图31)。多个电极22A可设置成与半导体层21’的另一个表面接触，并且可置于例如面对电极24的位置。绝缘层53’可设置成与半导体层21’的另一个表面接触并且可在面对每个电极22A的位置处具有孔径。绝缘层53’可由与绝缘层53相同的材料制成。
接下来，可在包括各个电极22A的整个表面上形成籽晶层22B’(图32)。籽晶层22B’可在电解电镀期间用作电极层。籽晶层22B’可由与籽晶部分22相同的材料制成。接下来，可在整个表面上形成光致抗蚀剂层430，之后可在面对电极22A的位置处形成孔径430A(图33)。接下来，可通过例如电解电镀方法，在籽晶层22B’的每个孔径430A中暴露的位置处依次形成屏障部分22C和焊料凸块60(步骤S303，图34)。换句话说，焊料凸块60中的一个可在面对每个电极22A的位置处形成，其间具有籽晶层22B’。在这种情况下，每个焊料凸块60可电耦接至籽晶层22B’。此外，通过电解电镀法形成焊料凸块60，各个焊料凸块60的顶表面可用作平坦表面60B。各个平坦表面60B可用作焊接凸块60和电极焊盘42接合在一起的接合表面60A。
顺便提及，在使用电解电镀方法形成多个焊料凸块60的情况下，除了形成焊料凸块60之外，焊料凸块60可优选地从电镀槽中提升到通电状态。换句话说，即使在电镀结束时，也可优选地继续通电。此后，可去除光致抗蚀剂层430。
接下来，覆盖各个焊料凸块60的光致抗蚀剂层440可形成在包括各个焊料凸块60的整个表面上，然后可在光致抗蚀剂层440中面对相邻的两个焊料凸块60之间的部分中形成凹槽440A(步骤S304，图35)。在这种情况下，可防止每个焊料凸块60的侧表面从光致抗蚀剂层440暴露。凹槽440A可具有例如包围面对光致抗蚀剂层440的每个焊料凸块60的部分的栅格形状。接下来，可使用光致抗蚀剂层440作为掩模来选择性地蚀刻籽晶层22B’。更具体地，可选择性地蚀刻籽晶层22B’的面向相邻的两个焊料凸块60之间的部分。因此，籽晶层22B’可被分离为多个籽晶部分22B(参见图36)。例如，过氧化氢-磷酸基水溶液可用作其中籽晶层22B’由铜制成的部分的蚀刻剂。例如，可将氟基化合物用作其中籽晶层22B’由钛制成的部分的蚀刻剂。
接下来，可连续使用光致抗蚀剂层440作为掩模来选择性地蚀刻绝缘层23’、半导体层21’、绝缘层25’和粘合剂层420(步骤S305)。更具体地，可选择性地蚀刻绝缘层23’、半导体层21’、绝缘层25’和粘合剂层420的面向相邻的两个焊料凸块60之间的部分。因此，半导体层21’可被分离成多个元件50(图36)。此后，可去除光致抗蚀剂层440(步骤S306，图37)。因此，可形成由元件50和焊料凸块60制成的多个复合元件。
【效果】
接着，对安装基板2的制造方法的效果进行描述。
在相关技术中的籽晶金属的蚀刻中，在许多情况下，在形成焊料凸块之后，使用化学试剂，使用焊料凸块作为掩模来选择性地去除籽晶金属。但是，籽晶金属形成在整个表面上，并且籽晶金属的许多部分应该被去除。因此，在选择性地蚀刻籽晶金属的同时，大大地去除籽晶金属的焊料凸块正下方的部分，并进行侧蚀刻。在焊料凸块具有大尺寸的情况下，侧蚀刻不会影响强度的可靠性；但是，在焊料凸块的尺寸例如小于30μm的情况下，侧蚀刻难以保持必要的强度。
因此，在本实施例中，用光致抗蚀剂层440覆盖每个焊料凸块60，并且使用光致抗蚀剂层440作为掩模来选择性地蚀刻籽晶层22B’。这使得可防止在焊料凸块60的正下方进行侧蚀刻，即使元件50的尺寸小。这使得可抑制由元件50的小尺寸导致的故障。
此外，在本实施例中，通过连续使用光致抗蚀剂层440作为掩模来选择性地蚀刻半导体层21’。与使用不同的掩模用于籽晶层22B’的蚀刻和半导体层21’的蚀刻的情况相比，这使得可能最小化焊料凸块60被暴露的情况。在元件50的尺寸小的情况下，焊料凸块60的尺寸小。因此，容易发生由焊料凸块60的表面氧化引起的接合故障。但是，在本实施例中，焊料凸块60露出的情况被最小化，从而抑制由焊料凸块60的表面氧化引起的接合故障。这使得可以抑制由于元件50的小尺寸引起的故障。
进一步地，在通常的焊料安装中，助焊剂210不被干燥。但是，如本实施例那样使用极小的焊料凸块60的情况下，当将涂覆有助焊剂210的焊料凸块60突然放入焊料回流炉中时，溶剂的快速挥发可能导致元件的移动。因此，在本实施例中，提供干燥时间段Δt3，在低于助焊剂210的软化点T1的温度下使溶剂缓慢挥发，使助焊剂210干燥，从而固定元件50。可防止元件50在预热期间和回流期间移动。因此，可以降低发生回流故障的可能性。另外，在本实施例中，在助焊剂210具有上述粘度和上述挥发度的情况下，可能将助焊剂210的液面210A降低到这样的程度，在该程度下，由助焊剂210的对流引起的元件50的移动被抑制。因此，可能在预热期间和回流期间抑制元件50的移动。
另外，在本实施例中，在形成焊料凸块60时，在多个焊料凸块60从通电状态从电镀槽提起的情况下(即，即使在电镀的最后也持续通电的情况下)，可以在如下的状态下完成电镀：焊料凸块60的表面中的金属组成比并不与焊料凸块60内的金属组成比不同。这使得可以减少发生回流故障。此外，在本实施例中，在使用电解电镀法形成各焊料凸块60的情况下，各焊料凸块60的顶表面成为平坦表面60B。因此，由于每个平坦表面60B用作焊料凸块60和电极焊盘42接合在一起的接合表面60A，因此与提供焊料球代替焊料凸块60的情况相比，可以减小元件50倾斜的可能性。这使得可以降低发生回流故障的可能性。
此外，在本实施例中，绝缘层23与半导体层21的底面的不包括电极22A的整个部分接触，而不与半导体层21的侧面接触。例如，将由元件50和焊料凸块60配置的复合元件安装在涂覆有助焊剂210的布线基板40上，以将焊料凸块60引向布线基板40，由此制造安装基板2。在这种情况下，例如可使用例如覆盖焊料凸块60的光致抗蚀剂层440作为掩模来选择性地蚀刻由半导体层21’、绝缘层23’和籽晶层22B’配置的堆叠体，直到穿透堆叠体，这使得可以形成各个元件50。在以这种方式形成各个元件50的情况下，与使用不同的掩模选择性地蚀刻半导体层21’、绝缘层23’和籽晶层22B’相比，焊料凸块60的芯与元件50的芯之间的未对准被减少。在焊料凸块60的芯与元件50的芯之间的未对准大的情况下，安装位置的精度容易降低，特别是在元件50的尺寸小的情况下，除了安装位置精度的大幅降低之外，元件50以倾斜状态安装。但是，在本实施例中，由于焊料凸块60的芯与元件50的芯之间的未对准很小，安装位置的精度极高，并且元件30以倾斜状态安装的可能性极低。这使得即使元件50的尺寸小也可以减少安装故障。因此，可抑制由元件50的小尺寸引起的故障。
<3.各实施例的共同修改示例>
在前述实施例中，示例了助焊剂130和210中的每一个包含树脂的情况；但是，助焊剂130和210可以是任何其它助焊剂。
<4.第三实施例>
【配置】
接下来，给出根据本技术的第三实施例的电子设备3的描述。图38示出了电子设备3的示意性配置的示例。电子设备3包括在上述各实施例及其修改实例中描述的安装基板1和2中的一个，以及控制器4，其电耦接至安装基板1和2中的一个。控制器4可以是向安装基板1和2中的一个施加电压或电流并且接收来自安装基板1和2中的一个的输出的电路。在电子设备3中，通过控制器4向安装基板1和2中的一个施加电压或电流可使安装基板1和2中的一个用作例如发光面板、显示面板或光接收面板。
【制造方法】
接着，给出包括安装基板1和2中的一个的电子设备3的制造方法的实例的描述。首先，安装基板1和2中的一个通过上述各实施例及其修改实例中所述的方法之一形成。接下来，可准备控制器4，然后，安装基板1和2中的一个可电耦接至控制器4以形成电子设备3。
【效果】
接下来，对电子设备3的制造方法的效果进行描述。
在本实施例中，安装基板1和2中的一个通过上述各实施例及其修改实例中所述的方法之一形成。与通过现有方法形成安装基板相比，这使得电子设备3可以使用不太可能引起故障的安装基板1和2中的一个，所述故障是指由于元件20或50的小尺寸、元件20之间的小间隙尺寸或元件50之间的小间隙尺寸引起的故障。
尽管已经通过给出实施例及其修改实例进行了描述，本技术不限于此，并且可以以各种方式修改。应当注意，本说明书中描述的效果是说明性的，并且本技术的效果不限于此。本技术可以具有任何其他效果。
此外，本技术可具有以下配置。
(1)一种制造安装基板的方法，包括：
第一步骤，在半导体层上形成多个电极，然后在面对每个所述电极的位置处形成一个焊料凸块；
第二步骤，用涂层覆盖所述焊料凸块，然后使用所述涂层作为掩模选择性地蚀刻所述半导体层，以将所述半导体层分离成多个元件；以及
第三步骤，去除所述涂层，并然后以将所述焊料凸块引向所述布线基板一侧的方式将所述元件安装在布线基板上，从而形成所述安装基板。
(2)根据1所述的制造所述安装基板的方法，其中
在第一步骤中，在包括所述各个电极的整个表面上形成籽晶层，然后利用其间的籽晶层在面对每个所述电极的位置处形成一个所述焊料凸块，并且
在第二步骤中，使用所述涂层作为掩模选择性地蚀刻所述籽晶层和所述半导体层，以将所述籽晶层分离成多个籽晶部分，并将所述半导体层分离成所述多个元件。
(3)根据(1)或(2)所述的制造所述安装基板的方法，其中，在所述第一步骤中，使用电解电镀法形成各个焊料凸块，以使各个焊料凸块的顶表面成为平坦表面。
(4)根据(3)所述的制造所述安装基板的方法，其中，在所述第一步骤中，使用所述电解电镀法形成所述焊料凸块，并且在通电状态下从所述电镀槽提起所述焊料凸块。
(5)根据(1)至(4)中任一项所述的制造所述安装基板的方法，其中，在所述第三步骤中，在除去所述涂层之后，在将助焊剂涂布在所述布线基板上的状态下将所述元件安装在所述支撑基板上，并且之后在低于所述助焊剂的软化点的温度下加热所述助焊剂以干燥助焊剂，然后在高于所述助焊剂的软化点且低于所述焊料凸块的熔点的温度下活化所述助焊剂，并随后执行回流。
(6)根据(5)所述的制造所述安装基板的方法，其中，所述助焊剂具有在所述回流结束前不会引起所述元件中的每一个从所述布线基板的接合区域偏离的粘度，并且具有如下的挥发性：助焊剂的液面在回流期间降低到获得自对准效果的范围内。
(7)根据(6)所述的制造所述安装基板的方法，其中，在所述第三步骤中，在回流期间，所述焊剂的液面位于比所述焊料凸块与所述元件之间的接合表面高的位置处。
(8)一种制造安装基板的方法，包括：
第一步骤，在支撑基板上形成多个电极，在包括所述各个电极的表面上形成籽晶层，以及在所述籽晶层的面向相邻的两个所述电极之间的部分的部分中形成贯通凹槽；
第二步骤，在面对每个所述电极的位置处形成电耦接至所述籽晶层的多个焊料凸块中的一个；和
第三步骤，使用所述贯通凹槽将所述籽晶层分离成多个籽晶部分，然后利用其间的一个或多个所述焊料凸块将所述多个元件中的每一个安装在所述支撑基板上。
(9)根据(7)所述的制造所述安装基板的方法，其中，在所述第一步骤中，使用电解电镀法形成所述各个焊料凸块，以使所述各个焊料凸块的顶表面成为平坦表面。
(10)根据(9)所述的制造所述安装基板的方法，其中，在所述第二步骤中，使用所述电解电镀法形成所述焊料凸块，并在通电状态下从所述电镀槽提起所述焊料凸块。
(11)根据(8)至(10)中任一项所述的制造所述安装基板的方法，其中，在所述第三步骤中，在将助焊剂涂布在包括所述各个焊料凸块的整个表面的状态下，利用其间的所述焊料凸块将所述元件安装在所述支撑基板上，并且之后在低于所述助焊剂的软化点的温度下加热所述助焊剂以干燥助焊剂，然后在高于所述助焊剂的软化点且低于所述焊料凸块的熔点的温度下活化所述助焊剂，并随后执行回流。
(12)根据(11)所述的制造所述安装基板的方法，其中，所述助焊剂具有在所述回流结束前不会使所述元件中的每一个从所述焊料凸块偏离的粘度，并且具有如下的挥发性：所述助焊剂的液面在回流期间降低到获得自对准效果的范围内。
(13)根据(12)所述的制造所述安装基板的方法，其中，在所述第三步骤中，在回流期间，所述焊剂的液面位于比所述焊料凸块与所述元件的接合表面高的位置。
(14)一种安装基板，包括：
布线基板；
多个元件，每个元件布置于面对所述布线基板的顶表面的位置处；和
多个焊料凸块，所述一个或多个焊料凸块设置在所述布线基板和每个所述元件之间，以将所述布线基板和每个所述元件彼此电耦接，
每个所述元件包括：
半导体层，
一个或多个电极，设置成与所述半导体层的底表面的一部分接触，以及
绝缘层，设置成与所述半导体层的底表面的不与一个或多个电极接触的整个部分接触，而不与所述半导体层的侧表面接触。
本申请基于并要求于2014年9月19日在日本专利局提交的日本专利申请No.2014-190952的优选权，其全部内容通过引用并入本文。
本领域技术人员应当理解，根据设计要求和其他因素，可进行各种修改、组合、子组合和变更，只要它们在所附权利要求或其等同物的范围内。

Claims (14)

1.一种制造安装基板的方法，包括：
第一步骤，在半导体层上形成多个电极，并且然后在面对每个所述电极的位置处形成一个焊料凸块；
第二步骤，利用涂层覆盖所述焊料凸块，并且然后使用所述涂层作为掩模选择性地蚀刻所述半导体层，以将所述半导体层分离成多个元件；以及
第三步骤，去除所述涂层，并且然后将所述元件安装在布线基板上以使所述焊料凸块朝向所述布线基板，从而形成所述安装基板。
2.根据权利要求1所述的制造安装基板的方法，其中
在所述第一步骤中，在包括各个所述电极的整个表面上形成籽晶层，并且然后利用之间的所述籽晶层在面对每个所述电极的位置处形成一个所述焊料凸块，并且
在所述第二步骤中，使用所述涂层作为掩模选择性地蚀刻所述籽晶层和所述半导体层，以将所述籽晶层分离成多个籽晶部分并将所述半导体层分离成多个所述元件。
3.根据权利要求2所述的制造安装基板的方法，其中，在所述第一步骤中，使用电解电镀法形成各个所述焊料凸块，以使各个所述焊料凸块的顶表面成为平坦表面。
4.根据权利要求3所述的制造安装基板的方法，其中，在所述第一步骤中，使用所述电解电镀法形成所述焊料凸块，并且在通电状态下从电镀槽提起所述焊料凸块。
5.根据权利要求1所述的制造安装基板的方法，其中，在所述第三步骤中，在去除所述涂层之后，在将助焊剂涂布在所述布线基板上的状态下将所述元件安装在支撑基板上，并且随后在低于所述助焊剂的软化点的温度下加热所述助焊剂以干燥所述助焊剂，然后在高于所述助焊剂的软化点且低于所述焊料凸块的熔点的温度下活化所述助焊剂，并随后执行回流。
6.根据权利要求5所述的制造安装基板的方法，其中，所述助焊剂具有如下的粘度：在所述回流结束前不会使所述元件中的每一个从所述布线基板的接合区域偏离，并且所述助焊剂具有如下的挥发性：所述助焊剂的液面在所述回流期间降低到获得自对准效果的范围内。
7.根据权利要求6所述的制造安装基板的方法，其中，在所述第三步骤中，在所述回流期间，所述助焊剂的液面位于比所述焊料凸块与所述元件之间的接合表面高的位置处。
8.一种制造安装基板的方法，包括：
第一步骤，在支撑基板上形成多个电极，然后在包括各个所述电极的表面上形成籽晶层，进而在所述籽晶层的面向相邻的两个所述电极之间的部分的部分中形成贯通凹槽；
第二步骤，在面对每个所述电极的位置处形成电耦接至所述籽晶层的多个焊料凸块中的一个；以及
第三步骤，使用所述贯通凹槽将所述籽晶层分离成多个籽晶部分，并且然后利用之间的一个或多个所述焊料凸块将多个元件中的每一个安装在所述支撑基板上。
9.根据权利要求8所述的制造安装基板的方法，其中，在所述第一步骤中，使用电解电镀法形成各个所述焊料凸块，以使各个所述焊料凸块的顶表面成为平坦表面。
10.根据权利要求9所述的制造安装基板的方法，其中，在所述第二步骤中，使用所述电解电镀法形成所述焊料凸块，并且在通电状态下从电镀槽提起所述焊料凸块。
11.根据权利要求8所述的制造安装基板的方法，其中，在所述第三步骤中，在将助焊剂涂布在包括各个所述焊料凸块的整个表面的状态下，利用之间的所述焊料凸块将所述元件安装在所述支撑基板上，并且之后在低于所述助焊剂的软化点的温度下加热所述助焊剂以干燥所述助焊剂，然后在高于所述助焊剂的软化点且低于所述焊料凸块的熔点的温度下活化所述助焊剂，并随后执行回流。
12.根据权利要求11所述的制造安装基板的方法，其中，所述助焊剂具有如下的粘度：在所述回流结束前不会使所述元件中的每一个从所述焊料凸块偏离，并且所述助焊剂具有如下的挥发性，所述助焊剂的液面在所述回流期间降低到获得自对准效果的范围内。
13.根据权利要求12所述的制造安装基板的方法，其中，在所述第三步骤中，在所述回流期间，所述助焊剂的液面位于比所述焊料凸块与所述元件的接合表面高的位置处。
14.一种安装基板，包括：
布线基板；
多个元件，分别布置于面对所述布线基板的顶表面的位置处；和
多个焊料凸块，一个或多个所述焊料凸块设置在所述布线基板和每个所述元件之间，以将所述布线基板和每个所述元件彼此电耦接，
每个所述元件包括：
半导体层，
一个或多个电极，设置成与所述半导体层的底表面的一部分接触，以及
绝缘层，设置成与所述半导体层的底表面的不与所述一个或多个电极接触的整个部分接触，而不与所述半导体层的侧表面接触。
CN201580048381.3A 2014-09-19 2015-09-08 安装基板和制造安装基板的方法 Expired - Fee Related CN106716612B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014190952 2014-09-19
JP2014-190952 2014-09-19
PCT/JP2015/075463 WO2016043092A1 (ja) 2014-09-19 2015-09-08 実装基板およびその製造方法

Publications (2)

Publication Number Publication Date
CN106716612A true CN106716612A (zh) 2017-05-24
CN106716612B CN106716612B (zh) 2019-11-19

Family

ID=55533131

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580048381.3A Expired - Fee Related CN106716612B (zh) 2014-09-19 2015-09-08 安装基板和制造安装基板的方法

Country Status (4)

Country Link
US (1) US10134662B2 (zh)
JP (1) JP6586957B2 (zh)
CN (1) CN106716612B (zh)
WO (1) WO2016043092A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5874683B2 (ja) * 2013-05-16 2016-03-02 ソニー株式会社 実装基板の製造方法、および電子機器の製造方法
DE112016001482T5 (de) * 2015-04-01 2017-12-28 Murata Manufacturing Co., Ltd. Duplexer
MY192389A (en) * 2016-07-01 2022-08-18 Intel Corp Systems, methods, and apparatuses for implementing a pad on solder mask (posm) semiconductor substrate package
DE102018115976A1 (de) * 2017-07-10 2019-01-10 Osram Opto Semiconductors Gmbh Verfahren zum Bestücken eines Trägers mit Bauelementen, Pigment für das Bestücken eines Trägers mit einem Bauelement und Verfahren zur Herstellung eines Pigments
CN116829298A (zh) * 2021-01-19 2023-09-29 长濑化成株式会社 半导体转印用助焊剂片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291740A (ja) * 2000-04-05 2001-10-19 Sony Corp 半導体素子の実装方法
CN1483220A (zh) * 2000-11-14 2004-03-17 亨克尔洛克泰特公司 硅晶片应用的助焊和填缝材料,和用其制造的层状电子组件
JP2006196693A (ja) * 2005-01-13 2006-07-27 Sony Corp 半導体素子の形成方法および半導体素子のマウント方法
CN102163578A (zh) * 2010-02-09 2011-08-24 索尼公司 半导体装置及其制造方法、叠层芯片安装结构及其形成方法
CN102332435A (zh) * 2010-07-13 2012-01-25 台湾积体电路制造股份有限公司 电子元件及其制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634268A (en) * 1995-06-07 1997-06-03 International Business Machines Corporation Method for making direct chip attach circuit card
JP3732639B2 (ja) * 1998-01-08 2006-01-05 株式会社日立製作所 はんだ付け方法および電子装置の製造方法
US7126164B2 (en) * 2003-09-26 2006-10-24 Flipchip International Llc Wafer-level moat structures
JP4347075B2 (ja) * 2004-01-29 2009-10-21 Ｔｄｋ株式会社 電気メッキ方法及び電気メッキ装置
JP4247690B2 (ja) * 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
CN102282659B (zh) * 2009-02-04 2013-11-20 松下电器产业株式会社 半导体基板结构及半导体装置
JP2011231137A (ja) * 2010-04-23 2011-11-17 Hitachi Chem Co Ltd 半導体封止充てん用エポキシ樹脂組成物及び半導体装置
US10163744B2 (en) * 2011-09-07 2018-12-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure
JP2014143316A (ja) * 2013-01-24 2014-08-07 Sanyu Rec Co Ltd フリップチップ部品の樹脂封止方法
JP5508583B2 (ja) 2013-06-27 2014-06-04 東レエンジニアリング株式会社 実装装置および実装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291740A (ja) * 2000-04-05 2001-10-19 Sony Corp 半導体素子の実装方法
CN1483220A (zh) * 2000-11-14 2004-03-17 亨克尔洛克泰特公司 硅晶片应用的助焊和填缝材料,和用其制造的层状电子组件
JP2006196693A (ja) * 2005-01-13 2006-07-27 Sony Corp 半導体素子の形成方法および半導体素子のマウント方法
CN102163578A (zh) * 2010-02-09 2011-08-24 索尼公司 半导体装置及其制造方法、叠层芯片安装结构及其形成方法
CN102332435A (zh) * 2010-07-13 2012-01-25 台湾积体电路制造股份有限公司 电子元件及其制作方法

Also Published As

Publication number Publication date
US10134662B2 (en) 2018-11-20
JPWO2016043092A1 (ja) 2017-07-06
JP6586957B2 (ja) 2019-10-09
US20170287823A1 (en) 2017-10-05
CN106716612B (zh) 2019-11-19
WO2016043092A1 (ja) 2016-03-24

Similar Documents

Publication Publication Date Title
CN106716612B (zh) 安装基板和制造安装基板的方法
TW494557B (en) Flip chip type semiconductor device and method of manufacturing the same
JP5629580B2 (ja) 二重ポスト付きフリップチップ相互接続
KR101865234B1 (ko) 이중 또는 복수회 에칭된 플립-칩 컨넥터를 갖는 마이크로전자 패키지 및 그 제조 방법
CN103283007B (zh) 不流动底充胶
JP5923725B2 (ja) 電子部品の実装構造体
TW200525666A (en) Bump-on-lead flip chip interconnection
CN101772995A (zh) 具有管脚接口的多层布线元件
TW200941670A (en) Die substrate with reinforcement structure
JP2008277677A (ja) 半導体チップおよびその製造方法
TWI578475B (zh) 基板及具有用於增加的柱高之介電質移除之基板的總成
US8853002B2 (en) Methods for metal bump die assembly
US6258703B1 (en) Reflow of low melt solder tip C4&#39;s
CN101859733B (zh) 半导体封装构造、半导体封装构造用载板及其制造方法
JP2009064989A (ja) 半導体装置およびその製造方法
KR102210802B1 (ko) 반도체 장치 및 그 제조 방법
US20150223329A1 (en) Carrier Plate, Device Having the Carrier Plate and Method for Producing a Carrier Plate
US20050026416A1 (en) Encapsulated pin structure for improved reliability of wafer
JP2015144157A (ja) 回路基板、電子装置及び電子装置の製造方法
JP2008177619A (ja) チップキャリア及び半導体装置並びにチップキャリアの製造方法
JP2011091087A (ja) 半導体装置とその製造方法
TWI220304B (en) Flip-chip package substrate and flip-chip bonding process thereof
US6960518B1 (en) Buildup substrate pad pre-solder bump manufacturing
JP2010087147A (ja) 半導体装置の製造方法
CN106449420B (zh) 嵌埋式封装结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20191119