CN106711214A - 栅极全包覆式纳米线场效晶体管装置 - Google Patents

栅极全包覆式纳米线场效晶体管装置 Download PDF

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CN106711214A
CN106711214A CN201510769624.4A CN201510769624A CN106711214A CN 106711214 A CN106711214 A CN 106711214A CN 201510769624 A CN201510769624 A CN 201510769624A CN 106711214 A CN106711214 A CN 106711214A
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nano wire
grid
effect transistor
field effect
transistor device
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CN106711214B (zh
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杨柏宇
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Blue Gun Semiconductor Co ltd
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United Microelectronics Corp
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Abstract

本发明公开一种栅极全包覆式纳米线场效晶体管装置，包含有一半导体基板、一纳米线，位于该半导体基板上、一栅极结构，环绕该纳米线的一中间部位，以及一源、漏极区域，位于该栅极结构的一侧。该源、漏极区域内至少具有一插排面。

Description

栅极全包覆式纳米线场效晶体管装置
技术领域
本发明涉及一种半导体元件及制作工艺，特别是一种具有源极与漏极差排(source and drain dislocation)的栅极全包覆式(Gate-All-Around,GAA)纳米线(nanowire)场效晶体管装置及其制作方法。
背景技术
已知，在金属-氧化物-半导体(MOS)晶体管的通道区域诱导适当类型的应力，能够提高载流子迁移，从而增加驱动电流。
通常情况下，优选是在NMOS元件通道区域的源极-漏极方向诱导拉伸应力，并在PMOS元件的通道区域的源极-漏极方向诱导压缩应力。应力扭曲半导体晶体晶格，从而影响半导体的能带对准和电荷传输特性。
此外，已知可以将差排(dislocation)引入MOS晶体管的源、漏极区域，以进一步改善元件的性能。
发明内容
本发明的主要目的在于提供一种栅极全包覆式(Gate-All-Around,GAA)纳米线(nanowire)场效晶体管(field effect transistor,FET)装置，具有源极与漏极差排(source and drain dislocation)，以进一步提升栅极全包覆式纳米线场效晶体管装置的效能。
为达上述目的，本发明的一实施例提供一种栅极全包覆式纳米线场效晶体管装置，包含有一半导体基板；一纳米线，位于该半导体基板上；一栅极结构，环绕该纳米线的一中间部位；一源、漏极区域，位于该栅极结构的一侧；以及至少一插排面，设于该源、漏极区域内。该插排面为一渐缩椎体形插排面，横跨该纳米线的整个厚度。
根据本发明的一实施例，所述插排面为一渐缩椎体形插排面。所述栅极全包覆式纳米线场效晶体管装置为一NMOS场效晶体管装置。栅极全包覆式纳米线场效晶体管装置为一NMOS场效晶体管装置。
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
附图说明
图1至图13为本发明一实施例中形成栅极全包覆式纳米线场效晶体管装置的制作工艺示意图，其中图2为图1中沿A-A’切线所视的剖面示意图，图6为图5中沿B-B’切线所视的的剖面示意图；
图14为栅极全包覆式纳米线场效晶体管装置的纳米线内的插排面透视示意图；
图15为本发明另一实施例所绘示的栅极全包覆式纳米线场效晶体管装置的剖面示意图；
图16为本发明又另一实施例所绘示的栅极全包覆式纳米线场效晶体管装置的剖面示意图。
主要元件符号说明
100 半导体基板
101 基底
102 绝缘层
103 单晶硅层
110 轴心体
130 掩模层
131 连接部
133 延伸部
150 纳米线结构
151 连接垫
153 纳米线
153a 外延应力诱发材料
157 通道区域
170 栅极结构
171 栅极介电层
173 栅极
175 间隙壁
182 源、漏极区域
190 图案化掩模
200 应力层
250 预非晶化注入制作工艺
260 退火制作工艺
300 插排面
302a～302c 插排面
402a～402c 插排面
404a～404d 插排面
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参照图1至图10，其为依据本发明实施例所绘示的形成栅极全包覆式(Gate-All-Around,GAA)纳米线(nanowire)场效晶体管(field effecttransistor,FET)装置的制作工艺示意图。如图1及图2所示，首先，提供一半导体基板100，例如一硅覆绝缘(silicon-on-insulator,SOI)基板，包括一基底(base)101、一绝缘层102与一单晶硅层103。接着，在单晶硅层103上形成至少一轴心体110。
轴心体110的材质可包含氧化硅，或是其他与下方半导体层103具蚀刻选择比的材质，例如，多晶硅(polysilicon)等。具体来说，各轴心体110之间相互分隔，使任两相邻的轴心体110之间大体上具有一间距，但不以此为限。
需注意的是，上述硅覆绝缘基板仅为例示说明，在另一实施例中，也可以使用其它基板。
接着，如图3所示，在单晶硅层103上形成一掩模层130，以作为后续形成纳米线结构的掩模。掩模层130可包含氮化硅或是其他与轴心体110及下方单晶硅层103具蚀刻选择比的材质，其形成方式，例如先在半导体基板100上形成一掩模材料层(未绘示)，覆盖半导体基板100及轴心体110，并进行一光刻及蚀刻制作工艺，部分移除该掩模材料层，形成部分覆盖轴心体110的掩模层130。
需特别注意的是，掩模层130除了包含部分覆盖各轴心体110的一连接部131之外，还具有一延伸部133，其紧邻且环绕各轴心体110侧壁。
然后，如图4所示，移除轴心体110，并利用掩模层130作为掩模进行一蚀刻制作工艺。由此，可移除一部分的单晶硅层103，并在硅覆绝缘基板100的单晶硅层103形成一纳米线结构150，其包含一连接垫151，以及位于连接垫151之间的至少一纳米线153。根据本发明实施例，纳米线153为一硅纳米线。
具体来说，本实施例是在轴心体110移除之后，分别进行两阶段的蚀刻制作工艺，例如是先进行一各向异性蚀刻制作工艺，例如干蚀刻，使硅覆绝缘基板100未被掩模层130覆盖的区域内的绝缘层102被暴露出。
在一实施例中，在进行该各向异性蚀刻制作工艺时，优选可调整蚀刻制作工艺的参数，以形成底切，并随即移除掩模层130。而后，继续进行一各向同性蚀刻制作工艺或是侧向蚀刻制作工艺，例如湿蚀刻，以进一步等向蚀刻纳米线结构150的侧壁。
然而，本发明的蚀刻制作工艺并不限于前述步骤。在另一实施例中，也可选择在掩模层130的遮蔽下，依序进行两阶段的蚀刻制作工艺，形成连接垫的上表面与纳米线的一上表面齐平的一纳米线结构(未绘示)，最后再移除掩模层130。
值得注意的是，在进行该蚀刻制作工艺时，纳米线结构150因受到掩模层130的阻挡，是以，接近掩模层130的单晶硅层103蚀刻速率相对较慢，远离掩模层130的单晶硅层103则蚀刻速率相对较快。另一方面，因纳米线153相对于连接垫151具有较小的尺寸，当纳米线153的两侧同时被等向蚀刻时，远离掩模层130的单晶硅层103容易被蚀穿。也就是说，纳米线153紧邻下方绝缘层102的部分会被移除，仅有紧靠掩模层130的部分纳米线153可被保留，因而可形成悬跨于连接垫151之间的纳米线153，如图5及图6所示。
此外，在另一实施例中，也可选择性再蚀刻部分的绝缘层102，使纳米线153与绝缘层102间的距离更远，以确保后续形成的栅极结构可完全环绕纳米线153。
后续，如图7所示，形成一栅极结构170，使栅极结构170跨越纳米线153。具体来说，栅极结构170的形成方法例如是包含依序在硅覆绝缘基板100及纳米线结构150上形成全面覆盖的一栅极介电层(未绘示)，例如是氧化硅、氮化硅、氮氧化硅或合适的高介电常数材料等介电材质，以及一栅极层(未绘示)，例如是多晶硅、金属硅化物或是所需的功函数金属与金属等导电材质，再形成一图案化掩模层190，并据此图案化该栅极层及该栅极介电层，形成至少部分环绕纳米线153的栅极173，以及位于栅极173与纳米线153之间的栅极介电层171。在栅极173两侧则是源、漏极区域182，定义出一通道区域157。在源、漏极区域182内可以注入适当的掺质。
此外，如图8所示，还可进一步形成环绕栅极结构170的一间隙壁175。间隙壁175例如是包含氮化硅、氧化硅等单层或多层结构，而其形成方式则可与普遍应用的栅极制作工艺整合，应为本领域者所熟知，于此不再赘述。
如图9所示，接着进行一预非晶化注入(pre-amorphized implantation,PAI)制作工艺250，例如，利用锗离子或其它合适的离子对未被环绕栅极结构170覆盖的区域进行轰击。在上述PAI制作工艺250中，控制适当的能量与剂量可对硅的晶格结构产生破坏，以形成一非晶化层，此非晶化层的结构可降低硼穿隧效应(channeling)与瞬间扩散效应(transient enhanceddiffusion)。
随后，进行一应力记忆工艺(stress memorized technique,SMT)，包括在栅极结构170以及未被栅极结构170覆盖的区域利用化学气相沉积法沉积一应力层200，例如氮化硅或氧化硅，如图10所示。例如，对NMOS场效晶体管而言，应力层200可以是伸张(tensile)应力膜，对PMOS场效晶体管而言，应力层200可以是压缩(compressive)应力膜。根据本发明实施例，栅极全包覆式纳米线场效晶体管为一NMOS场效晶体管，应力层200为一伸张应力膜。
如图11所示，随后进行一退火制作工艺260，例如在400℃至1500℃的温度范围，将应力层200的应力转移记忆至栅极结构170内。因为栅极173内的多晶硅及源、漏极区域182内的硅原子的重新结晶，在通道所产生垂直压应力及延着元件长度方向的拉应力，能够增进电子在NMOS场效晶体管的迁移率。
如图12所示，经过退火制作工艺，使得源、漏极区域182内的硅原子的重新结晶，会在靠近通道区域157形成插排平面300。根据本发明实施例，插排面300可以是横跨纳米线153的整个厚度，其可以包含曲面或平面，并不设限。
最后，如图13所示，将应力层200完全去除。随后，可以选择在源、漏极区域182成长一外延应力诱发材料153a。上述外延应力诱发材料153a可以包含有碳化硅(SiC)、磷化硅(SiP)、掺杂磷碳化硅(SiCP)或以上组合。
举例来说，如图14所示，插排面300可以是三维的渐缩椎体形结构，环绕着纳米线153，从纳米线153的表面朝向纳米线153的内部及通道区域157渐缩并延伸一预定距离，例如，5至50纳米，但不限于此。插排面300可以对通道区域157诱发应力，进一步提升栅极全包覆式纳米线场效晶体管装置的效能。
结构上，从图13及图14可看出本发明栅极全包覆式纳米线场效晶体管装置包含有一半导体基板100；一纳米线153，位于半导体基板100上；一栅极结构170，环绕纳米线153的一中间部位；一源、漏极区域182，位于栅极结构170的一侧；以及至少一插排面300，设于源、漏极区域182内。其中插排面300为一渐缩椎体形插排面。栅极结构170包含一栅极介电层171以及一栅极173。栅极173可以包括金属栅极。
请参阅图15。图15为依据本发明另一实施例所绘示的栅极全包覆式纳米线场效晶体管装置的剖面示意图。虽然在图14中，栅极各侧的纳米线153中仅显示出一个插排面300，然而，依据本发明另一实施例，除了插排面300之外，在栅极各侧的纳米线153中还可以另外形成其它插排面，例如图15中的插排面302a～302c，其中插排面302a、插排面302b及插排面302c可以从纳米线153的表面朝向纳米线153的内部及通道区域157延伸一预定距离。
依据本发明另一实施例，如图15所示，插排面302a、插排面302b及插排面302c从纳米线153的表面朝向纳米线153的内部延伸的距离可以不相同，例如，插排面302a的延伸距离小于插排面302b的延伸距离，而插排面302b的延伸距离小于插排面302c的延伸距离，但不限于图中的排列顺序。如图15所示，例如，插排面302c可以横跨纳米线153的整个厚度，而插排面302a及插排面302b则未横跨纳米线153的整个厚度。
请参阅图16。图16为依据本发明另一实施例所绘示的栅极全包覆式纳米线场效晶体管装置的剖面示意图。依据本发明又另一实施例，除了插排面300之外，在栅极两侧的纳米线中还可以不同数量的其它插排面，例如，如图16所示，在栅极结构170左侧的纳米线153中还可以形成三个插排面402a～402c，在栅极结构170右侧的纳米线153中还可以形成四个插排面404a～404d，其中插排面402a～402c及插排面404a～404d从纳米线153的表面朝向纳米线153的内部以及连接垫151的方向延伸一预定距离。插排面402a～402c及插排面404a～404d从纳米线153的表面朝向纳米线153的内部延伸的距离可以不相同。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (11)

1.一种栅极全包覆式纳米线场效晶体管装置，包含有:
半导体基板；
纳米线，位于该半导体基板上；
栅极结构，环绕该纳米线的一中间部位；
源、漏极区域，位于该栅极结构的一侧的该纳米线上；以及
至少一插排面，设于该源、漏极区域内。
2.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该插排面为一渐缩椎体形插排面。
3.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该栅极结构包含栅极介电层以及金属栅极。
4.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中另包含间隙壁，位于该栅极结构上。
5.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该源、漏极区域另包含有外延应力诱发材料。
6.如权利要求5所述的栅极全包覆式纳米线场效晶体管装置，其中该外延应力诱发材料包含有碳化硅、磷化硅、掺杂磷碳化硅或以上组合。
7.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该纳米线为一硅纳米线。
8.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该栅极全包覆式纳米线场效晶体管装置为NMOS场效晶体管装置。
9.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该半导体基板包含硅覆绝缘基板。
10.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该纳米线位于两连接垫之间。
11.如权利要求1所述的栅极全包覆式纳米线场效晶体管装置，其中该半导体基板包含氧化层，且该纳米线悬于该氧化层上方。
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