CN106711211A - InP基MOSHEMT结构及其制备方法 - Google Patents
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Abstract
本发明公开一种InP基MOSHEMT结构及其制备方法,该结构自下而上依次包括:一单晶衬底(101);在该单晶衬底上表面形成的变In组分InxAl1‑xAs缓冲层(102);In0.52Al0.48As缓冲层(103);在缓冲层中形成的平面掺杂层(104);In0.7Ga0.3As沟道层(105);In0.6Ga0.4As沟道层(106);In0.5Ga0.5As沟道层(107);InP势垒层(108);在势垒层中形成的平面掺杂层(109)。本发明采用组分渐变缓冲层降低III‑V半导体之间晶格失配,减少位错引进的缺陷。同时该器件结构不仅降低MOS界面态密度,并且通过对外延材料采用高In组分In0.7Ga0.3As/In0.6Ga0.4As/In0.5Ga0.5As复合沟设计充分的提高了二维电子气的浓度与电子迁移率,降低了沟道的方块电阻。
Description
技术领域
本发明涉及半导体器件技术领域,尤其涉及一种InP基MOSHEMT结构及其制备方法。
背景技术
目前半导体工业的主流是硅技术,随着半导体技术最小尺寸发展到纳米尺度,硅集成电路技术日益逼近其理论和技术的双重极限。而III-V族半导体材料相比硅材料具有更高的电子迁移率(6-60倍)和在低电场和强场下具有更加优异的电子输运性能等特性,因此,III-V族半导体材料将是新一代超高频低功耗集成电子系统的必然选择。
然而,传统的InP基HEMT的沟道二维电子气浓度和电子迁移率,受材料结构的影响无法做到使得导电沟道电子迁移率与二维电子气浓度均很大,限制了InP基HEMT器件在微波通信中的发展。需要在III-V族半导体上采用新的器件结构,以充分发挥III-V族半导体材料的特性,增强沟道中二维电子气浓度与电子迁移率。
发明内容
(一)要解决的技术问题
有鉴于此,本发明的目的在于提供一种InP基MOSHEMT结构及其制备方法,以解决以上所述的至少一项技术问题。
(二)技术方案
根据本发明的一方面,提供一种InP基MOSHEMT结构,所述结构由下至上依次包括:InP单晶衬底;变In组分InxAl1-xAs缓冲层,0<x<1;In0.52Al0.48As缓冲层,该层中还形成有第一平面掺杂层;In0.7Ga0.3As沟道层;In0.6Ga0.4As沟道层;In0.5Ga0.5As沟道层;InP势垒层,该层中还形成有第二平面掺杂层。
进一步的,在所述InP势垒层之上,所述结构还包括:重掺杂的窄带隙欧姆接触层,掺杂浓度在1x1017~5x1019cm-3;源漏金属;刻蚀到InP势垒层截止后生长的栅介质;栅极金属,形成于栅介质上。
根据本发明的另一方面,提供一种InP基MOSHEMT结构的制备方法,包括步骤:
S1:在InP衬底片上外延形成变In组分InxAl1-xAs缓冲层,0<x<1;
S2:在变In组分InxAl1-xAs缓冲层上外延形成In0.52Al0.48As缓冲层(,该层中还形成第一平面掺杂层,形成在所述In0.52Al0.48As缓冲层中;
S3:在In0.52Al0.48As缓冲层上外延生长第一层In0.7Ga0.3As沟道层;
S4:在第一层In0.6Ga0.4As沟道层外延生长第二层In0.6Ga0.4As沟道层;
S5:在第二层In0.6Ga0.4As沟道层外延生长第三层In0.5Ga0.5As沟道层;
S6:在第三层In0.5Ga0.5As沟道层外延形成InP势垒层,其中包含第二平面掺杂层。
进一步的,步骤S6之后还具有步骤:
S7:在InP势垒层上外延形成重掺杂的窄带隙欧姆接触层;
S8:在以上外延结构上利用光刻和刻蚀工艺形成有源区;
S9:在重掺杂的窄带隙欧姆接触层上形成源漏金属,掺杂浓度在1x1017~5x1019cm-3;
S10:形成有源区后采用湿法腐蚀方法对栅槽进行腐蚀;
S11:在腐蚀完栅槽后形成栅介质;
S12:在栅介质上形成栅金属。
进一步的,在步骤S1到S7采用MOCVD的方法进行外延生长。
进一步的,步骤S8中的有源区得到的方法为干法刻蚀或湿法刻蚀。
进一步的,步骤S9中的源漏金属为Ni/Ge/Au/Ge/Ni/Au金属系统。
进一步的,步骤S10的栅槽腐蚀采用湿法腐蚀帽层的方法腐蚀。
进一步的,步骤S11的栅介质采用ALD沉积系统生长。
进一步的,步骤S12的栅金属采用PMMA/MMA/PMMA胶两次电子束曝光一次显影方法制备。
(三)有益效果
从上述技术方案可以看出,本发明具有以下有益效果:
(1)组分渐变缓冲层降低III-V半导体之间晶格失配,减少位错引进的缺陷;
(2)同时该器件结构不仅降低MOS界面态密度,并且通过对外延材料采用高In组分In0.7Ga0.3As/In0.6Ga0.4As/In0.5Ga0.5As复合沟道设计以及势垒层和缓冲层平面处的双掺杂设计充分的提高了二维电子气的浓度与电子迁移率,降低了沟道的方块电阻。
附图说明
图1是本发明实施例的InP基MOSHEMT器件的结构示意图。
图2是本发明实施例的InP基MOSHEMT的结构制备流程图。
具体实施方式
本发明中的“上”、“下”、“内”、“外”仅用于相对参照平面表示各个层之间的相对位置关系,不用于表示实际中的上下和内外关系,实际元器件可以根据具体需要正序安装或倒序安装。而且,“之上”及“之下”表示与目标层之间接触与非接触。
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明作进一步的详细说明。
需要说明的是,附图中未绘示或描述的实现方式,为所属技术领域中普通技术人员所知的形式。另外,虽然本文可提供包含特定值的参数的示范,但应了解,参数无需确切等于相应的值,而是可在可接受的误差容限或设计约束内近似于相应的值。此外,本发明中提到的方向用语,仅是参考附图的方向。因此,使用的方向用语是用来说明并非用来限制本发明。
图1是本发明实施例InP基MOSHEMT的器件的结构示意图,该III-V族半导体MOSHEMT的器件结构从下至上包括:
一单晶衬底(101);
在该单晶衬底上表面形成的变In组分InxAl1-xAs缓冲层(102),0<x<1;
In0.52Al0.48As缓冲层(103),以及在缓冲层中形成的第一平面掺杂层(104);
In0.7Ga0.3As沟道层(105);
In0.6Ga0.4As沟道层(106);
In0.5Ga0.5As沟道层(107);
InP势垒层(108),以及在势垒层中形成的第二平面掺杂层(109);
另外,上述结构还进一步包括:
在势垒层上形成的重掺杂的窄带隙欧姆接触层(110),掺杂浓度在1x1017~5x1019cm-3;
在欧姆接触层上形成的源漏金属(111);
刻蚀到势垒层截止后生长的栅介质(112);在栅介质上形成的栅极金属(113)。
图2是本发明实施例得InP基MOSHEMT结构制备流程图。如图2所示,该III-V族半导体MOSHEMT制备流程可包括以下步骤:
S1:在InP衬底片上外延形成变In组分InxAl1-xAs缓冲层(102),0<x<1;
S2:在变In组分InxAl1-xAs缓冲层(102)上外延形成In0.52Al0.48As缓冲层(103);该层中还形成有第一平面掺杂层(104),形成在所述In0.52Al0.48As缓冲层中;
S3:在In0.52Al0.48As缓冲层上外延生长第一层In0.7Ga0.3As沟道层(105),
S4:在第一层In0.7Ga0.3As沟道层(105)外延生长第二层In0.6Ga0.4As沟道层(106);
S5:在第二层In0.6Ga0.4As沟道层(106)外延生长第三层In0.5Ga0.5As沟道层(107)
S6:在第三层In0.5Ga0.5As沟道层(107)外延形成InP势垒层(108);其中包含第二平面掺杂层(109)。
S7:在InP势垒层(108)上外延形成重掺杂的窄带隙欧姆接触层(110);
S8:在以上外延结构上利用光刻和刻蚀工艺形成有源区;
S9:在重掺杂的窄带隙欧姆接触层上形成源漏金属;
S10:形成有源区后采用湿法腐蚀方法对栅槽进行腐蚀;
S11:在腐蚀完栅槽后形成高K栅介质;
S12:在高K栅介质上形成T形栅金属。
上述工艺中,其中,在步骤S1到S7中可采用MOCVD的方法进行外延生长。
进一步的,步骤S8中的有源区得到的方法可以为干法刻蚀,或者也可以采用湿法刻蚀。
进一步的,步骤S9中的源漏金属可以为Ni/Ge/Au/Ge/Ni/Au金属系统。
进一步的,步骤S10的栅槽腐蚀采用湿法腐蚀帽层的方法腐蚀。
进一步的,步骤S11的栅介质采用ALD沉积系统生长。
进一步的,步骤S12的栅金属采用PMMA/MMA/PMMA胶两次电子束曝光一次显影方法制备。
通过上述实施例,提供了一种III-V族半导体高电子迁移率晶体管制备方法,组分渐变缓冲层降低III-V半导体之间晶格失配,减少位错引进的缺陷。同时该器件结构不仅降低MOS界面态密度,并且通过对外延材料采用高In组分In0.7Ga0.3As/In0.6Ga0.4As/In0.5Ga0.5As复合沟道设计以及势垒层和缓冲层平面处的双掺杂设计充分的提高了二维电子气的浓度与电子迁移率,降低了沟道的方块电阻。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种InP基MOSHEMT结构,其特征在于,所述结构由下至上依次包括:
InP单晶衬底(101);
变In组分InxAl1-xAs缓冲层(102),0<x<1;
In0.52Al0.48As缓冲层(103),该层中还形成有第一平面掺杂层(104);
In0.7Ga0.3As沟道层(105);
In0.6Ga0.4As沟道层(106);
In0.5Ga0.5As沟道层(107);
InP势垒层(108),该层中还形成有第二平面掺杂层(109)。
2.根据权利要求1所述的结构,其特征在于,在所述InP势垒层(108)之上,所述结构还包括:
重掺杂的窄带隙欧姆接触层(110),掺杂浓度在1x1017~5x1019cm-3;
源漏金属(111);
刻蚀到InP势垒层截止后生长的栅介质(112);
栅极金属(113),形成于栅介质(112)上。
3.一种InP基MOSHEMT结构的制备方法,其特征在于,包括步骤:
S1:在InP衬底片上外延形成变In组分InxAl1-xAs缓冲层(102),0<x<1;
S2:在变In组分InxAl1-xAs缓冲层(102)上外延形成In0.52Al0.48As缓冲层(103),该层中还形成第一平面掺杂层(104),形成在所述In0.52Al0.48As缓冲层中;
S3:在In0.52Al0.48As缓冲层(103)上外延生长第一层In0.7Ga0.3As沟道层(105);
S4:在第一层In0.6Ga0.4As沟道层(105)外延生长第二层In0.6Ga0.4As沟道层(106);
S5:在第二层In0.6Ga0.4As沟道层(106)外延生长第三层In0.5Ga0.5As沟道层(107);
S6:在第三层In0.5Ga0.5As沟道层(107)外延形成InP势垒层(108),其中包含第二平面掺杂层(109)。
4.根据权利要求3所述的制备方法,其特征在于,步骤S6之后还具有步骤:
S7:在InP势垒层(108)上外延形成重掺杂的窄带隙欧姆接触层(110);
S8:在以上外延结构上利用光刻和刻蚀工艺形成有源区;
S9:在重掺杂的窄带隙欧姆接触层上形成源漏金属,掺杂浓度在1x1017~5x1019cm-3;
S10:形成有源区后采用湿法腐蚀方法对栅槽进行腐蚀;
S11:在腐蚀完栅槽后形成栅介质;
S12:在栅介质上形成栅金属。
5.根据权利要求4所述的制备方法,其特征在于,在步骤S1到S7采用MOCVD的方法进行外延生长。
6.根据权利要求4所述的制备方法,其特征在于,步骤S8中的有源区得到的方法为干法刻蚀或湿法刻蚀。
7.根据权利要求4所述的制备方法,其特征在于,步骤S9中的源漏金属为Ni/Ge/Au/Ge/Ni/Au金属系统。
8.根据权利要求4所述的制备方法,其特征在于,步骤S10的栅槽腐蚀采用湿法腐蚀帽层的方法腐蚀。
9.根据权利要求4所述的制备方法,其特征在于,步骤S11的栅介质采用ALD沉积系统生长。
10.根据权利要求4所述的制备方法,其特征在于,步骤S12的栅金属采用PMMA/MMA/PMMA胶两次电子束曝光一次显影方法制备。
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