CN106711116B - 电子电路供电电位的分布 - Google Patents

电子电路供电电位的分布 Download PDF

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CN106711116B
CN106711116B CN201610352065.1A CN201610352065A CN106711116B CN 106711116 B CN106711116 B CN 106711116B CN 201610352065 A CN201610352065 A CN 201610352065A CN 106711116 B CN106711116 B CN 106711116B
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chip
peripheral
welding disk
conducting wire
conductive welding
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CN106711116A (zh
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N·弗洛伊德瓦奥克斯
Y·巴彻
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STMicroelectronics Rousset SAS
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Abstract

一种集成电路，包括通过外围导电轨道互连的至少两个外围导电焊盘以及连接两个导电焊盘的至少一个电线。

Description

电子电路供电电位的分布
相关申请的交叉引用
本申请要求于2015年11月18日提交的第15/61095号法国专利申请的优先权，其全部内容在法律允许的最大范围内通过引用合并于此。
技术领域
本公开一般涉及电子电路，并且特别地涉及用于为集成电路供电的电位的分布。
背景技术
集成电路通常被组装在封装中并被连接到其它电路以及供电端子。供电电位的分布或者来自外部连接端子的集成电路中静态信号的分布是一个重复出现的问题。
最通常，将封装连接到另一封装或者电子板的端子分布在包含半导体材料芯片的封装的外围处。将这些焊盘中的一焊盘连接到用于提供静电位的端子一般不足以保持芯片内的电位的一致性。事实上，将该静电位从外部端子一直输送到使用它们的元件的轨道(track)具有产生电压降的寄生电阻。
因此，通常需要利用封装的多个均匀分布的端子，这些端子被连接到封装内部的集成电路的不同焊盘。因而建立一种环绕集成电路的环来分布静电位，尤其是供电电位。传递电位的端子数量越多，分布越好，即，集成电路的不同点(焊盘)之间的供电电压间隔越小。然而，端子数量越多，封装体积越大。
发明内容
希望在不影响封装中集成电路的这些电位分布的情况下，减少将封装连接到静电位的端子数量。
实施例克服了通常封装和相同静电位分布的所有或部分缺陷。
实施例提供了更尤其适于配置有外围电源线的集成电路的解决方案。
实施例提供了容易实施的解决方案。
因此，实施例提供一种集成电路，其包括：
通过外围导电轨道(conductive track)互连的至少两个外围导电焊盘；以及
连接该两个导电焊盘的至少一个电线。
根据实施例，该电路包括：
通过至少一个第一外围轨道互连的第一数量的第一外围导电焊盘；
通过至少一个第二导电轨道互连的、靠近芯片的中心布置的第二数量的第二导电焊盘；以及
将第一焊盘和第二焊盘两两连接的电线。
根据实施例，第一数量和第二数量是相等的。
根据实施例，第一导电轨道和第二导电轨道位于不同的导电层级(levels)。
根据实施例，该电路还包括：
通过至少一个第三外围轨道互连的第三数量的第一外围导电焊盘；
通过至少一个第四导电轨道互连的、靠近芯片的中心布置的第四数量的第二导电焊盘；以及
将第三焊盘和第四焊盘两两连接的电线。
根据实施例，第三数量和第四数量是相等的。
根据实施例，第三导电轨道和第四导电轨道位于不同的导电层级。
根据实施例，第一数量、第二数量、第三数量和第四数量是相等的。
根据实施例，所述电线由铜或金制成。
实施例还提供了一种电子电路，包括：
如上所述的集成电路；以及
封装，所述封装包含通过电线被连接到该电路的外围焊盘中的仅仅一个外围焊盘的第一端子。
根据实施例，第二端子通过电线被连接到集成电路的第三焊盘中的仅仅一个第三焊盘。
将联系附图在下面对特定实施例的非限制性描述中详细讨论前述和其它特征和优点。
附图说明
图1示意性示出了封装的端子连接到包含在封装中的集成电路的焊盘的常见实施例；
图2示意性示出了封装的端子连接到包含在封装中的集成电路的焊盘的实施例；
图3示意性示出了图2实施例中集成电路中心的连接；以及
图4示意性示出了封装的端子连接到包含在封装中的集成电路的焊盘的另一实施例。
具体实施方式
在不同的附图中同一元件标以相同的附图标记。具体来说，不同实施例所共有的结构和/或功能元件可以标以相同的附图标记，并且可以具有类似的结构、尺寸和材料特性。为清楚起见，只有有助于理解所述实施例的那些步骤和元件才被示出并被详细描述。具体来说，电路内部或外部的静电位的目的未被详细描述，所描述的实施例与当前所用的这种电位一致。此外，集成电路的结构和功能也未被详细描述，这里所描述的实施例也与普通集成电路的结构和功能一致。当提及术语“大约(about)”、“接近(approximately)”、或“大约(in the order of)”时，这意味着在10％，最好5％以内。为简单起见，由于所述实施例的实现没有对经集成电路处理的信号的其它连接进行修改，所以下面仅对静电供电电位的连接进行描述。
图1示意性示出了封装中常用集成电路的实例。
集成电路芯片2包括分布在芯片外围处并通过外围轨迹26和28互连的多个焊盘22和24。为了使供电电位在轨迹26和28上均匀分布，焊盘22和24单独连接到封装3的连接端子，连接端子在封装的外部连接到相应的供电电位。由于芯片2的层级处的外围轨迹26和28，实际上通常要提供多个外部连接以限制轨迹导体的寄生电阻的影响。然而，这大大增加了封装3的端子32和34的数量。
根据将要描述的实施例，提供一种对来自集成电路芯片的中心的供电电位的分布(尤其是，使用在集成电路多个区域中的静电位)。
图2是封装集成电路的实施例的简化图。
集成电路芯片4集成在封装5中，包括连接到外部的端子52和54。以与图1相同的方式，为简单起见，仅示出了供电电位的连接。
与常见实施方式相比，封装5的每个供电电位包括单个端子52或54。即便这没在按比例绘制的附图中出现，但其或能够减小封装尺寸并因此减小总体积，或能够使连接到外部的端子可用于集成其它功能。为了保证供电电位的均匀分布，芯片还包括多个焊盘42和44，焊盘优选是均匀分布的，连接到供电电位分布的外围轨迹46和48。
提供来自芯片4的中心而不是其外围的源自端子52和54的供电电位的分布。从下面的描述明显看出，电气路径长度的差距因此减小，这使得接入电阻(access resistance)一致，并因此使得芯片4层级的电位分布均匀。
在所示的实施例中，在芯片4的中心处，提供了与已有焊盘42和44一样多的焊盘62和64(在本实施例中为四个焊盘62和四个焊盘64)。像焊盘42和44一样，焊盘62和64位于芯片的上表面。每个焊盘42、44分别通过芯片4外部的电线66、68连接到焊盘62、64。因此，常规的趋势是形成与集成到芯片的导电轨道的所有连接，而发明人此处提供了从芯片外部形成静电位连接。
焊盘52和54分别通过导线56、58连接到芯片4外围的焊盘42、44中的一个(且仅一个)上。
为了允许多个静电位分布并避免可能产生短路危险的电线交叉，根据焊盘的性质，焊盘62和64通过集成到芯片的导电轨道相互连接。例如，轨道形成在与外围路径46和48相同的金属化层上。
图3是示出了形成焊盘62彼此之间的互连和焊盘64彼此之间的互连的简化图。在这个实例中，提供了在芯片4的两个不同导电层级上分别将焊盘62连接到一起和将焊盘64连接到一起的导电轨道65和67。
与集成的导电轨道相比，上述实施例的优点源于例如由金或铜制成的键合导线的更好导电性。从芯片的中心部位分布还能使分布电位一致。
焊盘42和44的数量越大，并且从而芯片的62和64的数量越大，供电电位的分布就越好。
一旦完成了导线键合，组件就被封装在形成封装的绝缘树脂中。从而将电线56、58、66和68全部集成在封装5中。
图4是相对于当前解决方案改进的另一实施例的顶视图，其未同图2和3的实施例那样优化分布。
在这个实例中，集成电路4’以与图2相同的方式配备外围供电电位分布轨迹(未示出)。电路4’包括两个大致直径上对置的外围焊盘42’以及两个大致直径上对置的外围焊盘44’(考虑内置有电路的圆形)。
以与图2相同的方式，封装的两个端子52和54通过电线连接到电路的两个外围焊盘42”和44”。焊盘42”和44”通过导电轨道连接到外围电源轨迹，未示出。
根据图4的实施例，提供将焊盘42’和焊盘44’两两连接的电线66’和68’。因此，即使供电电位具有单个输入点(焊盘42”和44”)，虽然封装的端子数量减少，但相对于简单外围轨迹来说，其电位分布也是一致的。
已经对各种实施例进行了描述。本领域技术人员可以对其进行各种变型、修改和改进。具体来说，焊盘42和44的数量可以根据实际应用进行改变。进一步，将被分布的电位数量也可以根据实际应用进行改变。进一步，基于上述给出的功能性说明，已经描述的实施例的具体实现在本领域技术人员的能力范围之内。
这种变型、修改和改进旨在构成本公开的一部分，而且在本发明的精神和范围之内。相应地，前述说明仅作为示例而非意在进行限制。本发明仅限于下面的权利要求及其等同替代的限定。

Claims (8)

1.一种集成电路，包括：
第一外围导电焊盘，位于集成电路芯片的第一边缘附近；
第二外围导电焊盘，位于集成电路芯片的第二边缘附近，所述第二边缘与所述第一边缘相对；其中所述第一外围导电焊盘和第二外围导电焊盘由所述集成电路芯片内的第一外围导电轨道互连；
所述集成电路芯片外部的第一导线，所述第一导线具有与所述第一外围导电焊盘直接接触的第一端并且具有与所述第二外围导电焊盘直接接触的第二端；
封装件，所述封装件封装所述集成电路芯片和所述第一导线，其中所述封装件包括外部端子；以及
另外的导线，所述另外的导线具有与所述外部端子直接接触的第一端并且具有与第三外围焊盘直接接触的第二端，所述第三外围焊盘被直接连接到所述第一外围导电轨道；以及
所述封装件还封装所述另外的导线。
2.一种集成电路，包括：
第一外围导电焊盘，位于集成电路芯片的第一边缘附近；
第二外围导电焊盘，位于集成电路芯片的第二边缘附近，所述第二边缘与所述第一边缘相对；
其中所述第一外围导电焊盘和第二外围导电焊盘由所述集成电路芯片内的第一外围导电轨道互连；
第一内部导电焊盘，位于所述集成电路芯片的中心区域；
第二内部导电焊盘，位于所述集成电路芯片的中心区域；
其中所述第一内部导电焊盘和第二内部导电焊盘由所述集成电路芯片内的第一内部导电轨道互连；
所述集成电路芯片外部的第一导线，所述第一导线具有与所述第一外围导电焊盘直接接触的第一端和与所述第一内部导电焊盘直接接触的第二端；以及
所述集成电路芯片外部的第二导线，所述第二导线具有与所述第二外围导电焊盘直接接触的第一端和与所述第二内部导电焊盘直接接触的第二端。
3.根据权利要求2所述的集成电路，还包括：
封装件，所述封装件封装所述集成电路芯片、所述第一导线和所述第二导线。
4.根据权利要求3所述的集成电路，其中所述封装件包括外部端子并且还包括另外的导线，所述另外的导线具有与所述外部端子直接接触的第一端并且具有与所述第一外围导电焊盘直接接触的第二端，所述封装件还封装所述另外的导线。
5.根据权利要求2所述的集成电路，其中所述第一外围导电轨道和所述第一内部导电轨道被形成在所述集成电路芯片的不同的导电层级中。
6.根据权利要求2所述的集成电路，还包括：
第三外围导电焊盘，位于集成电路芯片的所述第一边缘附近；
第四外围导电焊盘，位于集成电路芯片的所述第二边缘附近，所述第二边缘与所述第一边缘相对；
其中所述集成电路芯片的所述第三外围导电焊盘和所述第四外围导电焊盘由所述集成电路芯片内的第二外围导电轨道互连；
第三内部导电焊盘，位于所述集成电路芯片的所述中心区域；
第四内部导电焊盘，位于所述集成电路芯片的所述中心区域；
其中所述第三内部导电焊盘和所述第四内部导电焊盘由所述集成电路芯片内的第二内部导电轨道互连；
在所述集成电路芯片外部的第三导线，所述第三导线具有与所述第三外围导电焊盘直接接触的第一端并且具有与所述第三内部导电焊盘直接接触的第二端；以及
在所述集成电路芯片外部的第四导线，所述第四导线具有与所述第四外围导电焊盘直接接触的第一端并且具有与所述第四内部导电焊盘直接接触的第二端。
7.根据权利要求6所述的集成电路，其中所述第二外围导电轨道和所述第二内部导电轨道被形成在所述集成电路芯片的不同的导电层级中。
8.根据权利要求1所述的集成电路，其中所述第一导线是由铜或金制成的键合线。
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