CN106653763B - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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CN106653763B
CN106653763B CN201610855822.7A CN201610855822A CN106653763B CN 106653763 B CN106653763 B CN 106653763B CN 201610855822 A CN201610855822 A CN 201610855822A CN 106653763 B CN106653763 B CN 106653763B
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tft
film transistor
thin film
array substrate
data line
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CN106653763A (zh
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简守甫
孙丽娜
王一明
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Tianma Microelectronics Co Ltd
Shanghai AVIC Optoelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Shanghai AVIC Optoelectronics Co Ltd
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Abstract

本发明实施例公开了一种阵列基板、显示面板及显示装置。所述阵列基板包括：基板；形成在所述基板上的多条扫描线和多条数据线，所述多条扫描线和所述多条数据线绝缘交叉限定多个像素单元；所述像素单元包括薄膜晶体管，所述薄膜晶体管的栅极与所述扫描线电连接，源极与所述数据线电连接，漏极与所述像素单元的像素电极电连接；所述薄膜晶体管的沟道区的有效长度大于或者等于所述像素单元沿所述扫描线延伸方向长度的三分之一。本发明实施例降低了显示面板的漏电流，提升了显示面板在低频驱动时的显示效果。

Description

阵列基板、显示面板及显示装置
技术领域
本发明实施例涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
随着显示技术的发展，液晶显示产品的显示效果不断地得到改善，从而使液晶显示产品的应用越来越广泛。
显示产品的功耗与显示驱动频率成正比，为降低产品的功耗需要降低显示驱动频率。然而，目前的显示产品在降低驱动频率后，由于漏电流的存在，在保持阶段，像素电极电压不断减小，显示画面容易出现闪烁，影响显示效果。
发明内容
本发明提供了一种阵列基板、显示面板及显示装置，以降低显示面板的漏电流，实现显示面板的低频驱动，并提升低频驱动下的显示效果。
本发明实施例的一方面提供了一种阵列基板，所述阵列基板包括：
基板；
形成在所述基板上的多条扫描线和多条数据线，所述多条扫描线和所述多条数据线绝缘交叉限定多个像素单元；
所述像素单元包括薄膜晶体管，所述薄膜晶体管的栅极与所述扫描线电连接，源极与所述数据线电连接，漏极与所述像素单元的像素电极电连接；所述薄膜晶体管的沟道区的有效长度大于或者等于所述像素单元沿所述扫描线延伸方向长度的三分之一。
本发明实施例的另一方面还提供了一种显示面板，所述显示面板包括本发明任意实施例所述的阵列基板。
本发明实施例的又一方面还提供了一种显示装置，所述显示装置包括本发明任意实施例所述的显示面板。
本发明实施例通过设置薄膜晶体管的沟道区的有效长度大于或者等于像素单元沿扫描线延伸方向长度的三分之一，增大了薄膜晶体管的阻值，而薄膜晶体管两端的压差一定，从而降低了薄膜晶体管中的漏电流，使得像素电极电压变化减小，使得显示面板能够在低频率驱动的条件下避免漏电流过大引起的闪烁问题，从而实现了显示面板的低频驱动，节省了显示面板的功耗。
附图说明
图1是本发明实施例提供的一帧画面内像素电极电压变化示意图；
图2是本发明实施例提供的一种阵列基板的示意图；
图3是图2中阵列基板沿剖面线E-E的剖面图；
图4是本发明实施例提供的又一种阵列基板的示意图；
图5是本发明实施例提供的又一种阵列基板的示意图；
图6是本发明实施例提供的又一种阵列基板的示意图；
图7是图6中阵列基板沿剖面线F-F的剖面图；
图8是本发明实施例提供的一种显示面板的示意图；
图9是本发明实施例提供的一种显示面板的透视图；
图10是本发明实施例提供的一种显示装置的示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
图1是本发明实施例提供的一帧画面内像素电极电压变化示意图，参考图1，Vg为施加到扫描线的栅极驱动信号，Vp为像素电极电压，显示面板在显示时将每一帧画面分为画面充电阶段c和画面保持阶段e，在画面充电阶段c，栅极驱动信号Vg为高电平，与像素电极连接的薄膜晶体管导通，对像素电极充电，使像素电极电压Vp达到相应的灰阶电压，即将整个画面所要显示的信息完成写入；在画面保持阶段e，栅极线给定某一直流信号或不给信号，薄膜晶体管关闭，直到下一帧信号开始。由于漏电流的影响，在保持阶段e，像素电极会通过薄膜晶体管漏电，像素电极电压Vp随着时间不断减小。若降低显示面板的驱动频率，则保持阶段e的时间变长，像素电极电压Vp的减小量较大，在保持阶段像素电极电压Vp无法满足画面显示要求，容易出现闪烁，影响显示效果。
为解决上述问题，本发明提供了一种阵列基板，图2是本发明实施例提供的一种阵列基板的示意图，图3是图2中阵列基板沿剖面线E-E的剖面图，参考图2和图3，所述阵列基板包括：
基板10，形成在基板10上的多条扫描线110和多条数据线120，多条扫描线110和多条数据线120绝缘交叉限定多个像素单元130。
像素单元130包括薄膜晶体管131，薄膜晶体管131的栅极210与扫描线110电连接，源极220与数据线120电连接，漏极230与像素单元130的像素电极132电连接。薄膜晶体管131的沟道区的有效长度(L1+L2+L3)大于或者等于像素单元130沿扫描线110延伸方向长度A的三分之一。
其中，薄膜晶体管131的栅极210与扫描线110在同一工艺中形成，栅极210可以为属于扫描线110的一部分，图2中并未进行区分。薄膜晶体管131的沟道区即薄膜晶体管131的有源层240与扫描线110或栅极210的交叠部分，沟道区的有效长度即薄膜晶体管131的有源层240与扫描线110或栅极210的交叠部分的长度。参考图3，像素单元130还包括公共电极133(并未在图2中示出)。
具体的，薄膜晶体管131的沟道区有效长度与薄膜晶体管131的阻值具有一定的正比例关系，沟道区有效长度增大，薄膜晶体管131的阻值相应的增大。本实施例通过设置薄膜晶体管131的沟道区的有效长度大于或者等于像素单元130沿扫描线110延伸方向长度A的三分之一，增大了薄膜晶体管131的阻值，而薄膜晶体管131两端的电压一定，从而降低了薄膜晶体管131的漏电流，使得像素电极电压的变化减小，避免了像素电极电压减小量过大使显示画面出现闪烁，从而提升了低频驱动时的显示效果。
可选的，参考图2，与薄膜晶体管131的源极220电连接的数据线120和薄膜晶体管131的漏极230之间至少间隔一条数据线120。这样设置，使得薄膜晶体管131的漏极230与源极220沿扫描线110之间的距离增大，使得薄膜晶体管131的有源层240与扫描线110或栅极210对应的区域的长度可以更长，即沟道区的有效长度可以更长，进一步增大了薄膜晶体管131的阻值，从而进一步降低了漏电流，进一步提升了低频驱动时的显示效果。需要说明的是，图2中仅示出了与薄膜晶体管131的源极220电连接的数据线120和薄膜晶体管131的漏极230之间间隔一条数据线120的情况，并非对本发明的限定。
可选的，参考图2，与所述薄膜晶体管131的漏极230相邻的两条数据线120中，到与薄膜晶体管131的源极220电连接的数据线120距离较近的为第一数据线，另一条为第二数据线，薄膜晶体管131的漏极230到第一数据线的距离A1可以大于到第二数据线的距离A2。这样设置，进一步增大了薄膜晶体管131的漏极230与源极220沿扫描线110之间的距离，使得薄膜晶体管131的有源层240与扫描线110或栅极210对应的区域的长度可以更长，即沟道区的有效长度可以更长，进一步增大了薄膜晶体管131的阻值，从而进一步降低了漏电流，进一步提升了低频驱动时的显示效果。
图4是本发明实施例提供的又一种阵列基板的示意图，参考图4，薄膜晶体管131的源极220还可以和与薄膜晶体管131的漏极230相邻的数据线120之一电连接。这样设置，使得薄膜晶体管131无需跨越两个或多个像素单元130，使得扫描线110可以做的更窄，在增大薄膜晶体管131的沟道区有效长度的同时，保证了像素单元130具有较高的开口率。
可选的，参考图4，薄膜晶体管131的漏极230到与薄膜晶体管131的源极220电连接的数据线120的距离B1大于到另一条与薄膜晶体管131的漏极230相邻的数据线120的距离B2。通过设置B1大于B2使得薄膜晶体131的沟道区长度大于像素单元130沿扫描线110延伸方向长度A的二分之一，使得薄膜晶体管131具有较高的阻值，降低了薄膜晶体管131的漏电流，使得像素电极电压的变化减小，避免了像素电极电压减小量过大使显示画面出现闪烁，从而提升了低频驱动时的显示效果。
需要说明的是，上述实施例中主要通过增大薄膜晶体131的漏极230与源极220沿扫描线110之间的距离来增大沟道区沿扫描线110方向的尺寸达到增大沟道区有效长度的效果，并非对本发明的限定。在其他实施方式中还可以通过其他方式增大沟道区的有效长度。
可选的，还可以设置薄膜晶体管131的沟道区的有效长度大于薄膜晶体管131的源极220与漏极230沿扫描线110延伸方向的距离。
图5是本发明实施例提供的又一种阵列基板的示意图，参考图5，薄膜晶体管131的沟道区在基板10上的投影可以具有多个弯折部。具体的，可以设置多个图5所示的“n”型或“U”型弯折部，来增大薄膜晶体管131的沟道区沿数据线120方向的尺寸，从而增大沟道区的有效长度。需要说明的是，图5中仅示例性的示出了在沟道区设置一个“n”型和一个“U”型弯折部，使沟道区具有两段沿数据线120延伸方向平行的子沟道区240a、240b和240c的情况，并非对本非明的限定，在其他实施方式中，还可以设置多个弯折，使沟道区具有多段沿扫数据线120延伸方向平行的子沟道区。
图6是本发明实施例提供的又一种阵列基板的示意图，参考图6，可以通过在薄膜晶体管131的沟道区设置多个“C”型弯折部，来增大薄膜晶体管131的沟道区沿扫描线110延伸方向的尺寸，使得薄膜晶体管131的沟道区沿扫描线110延伸方向的尺寸远大于源极220与漏极230沿扫描线110延伸方向的距离，以提高薄膜晶体管131的阻值，进一步减小了漏电流。需要说明的是，图6中仅示例性的示出了在沟道区设置一个“C”型弯折部，使沟道区具有两段沿扫描线110延伸方向平行的子沟道区240d和240e的情况，并非对本非明的限定，在其他实施方式中，还可以设置多个弯折部，使沟道区具有多段沿扫描线110延伸方向平行的子沟道区。
具体的，图5和图6仅示例性的示出了设置三种形状的弯折部的情况，并非对本发明的限定，在其他实施方式中，还可以设置其他形状的弯折，还可以设置多种弯折形状的组合。另外，图5和图6所示的实施方式通过设置多个弯折部，使得薄膜晶体管131的沟道区的有效长度大于薄膜晶体管131的源极220与漏极230沿扫描线110延伸方向的距离，使得薄膜晶体管131无需跨越两个或多个像素单元130，使得将扫描线110可以做的较窄，在增大薄膜晶体管131的沟道区有效长度的同时，保证了像素单元130具有较高的开口率。
需要说明的是，上述实施方式中薄膜晶体管131的源极220与漏极230之间在沿数据线120延伸的方向上至少间隔一条扫描线110。这样设置，使得薄膜晶体管131的有源层240可以有更多的区域与扫描线110或栅极210交叠，即沟道区的有效长度可以更长，从而降低漏电流。但这样设置并非对本发明的限定，在其他实施方式中，源极220与漏极230之间在沿数据线120延伸的方向上是否间隔扫描线110，可以以及具体情况而定，只要使得薄膜晶体管131的有效长度可以设置的更长即可。
可选的，薄膜晶体管131可以为低温多晶硅薄膜晶体管。具体的，低温多晶硅薄膜晶体管具有较高的电子迁移速率，使得薄膜晶体管131的反应速度极快，保证了在薄膜晶体管131的沟道区长度变大之后不会影响像素单元130的充放电速度；另外使得薄膜晶体管131占用面积可以做的更小、更薄，一方面可以降低显示面板功耗，另一方面，保证了像素当有具有较高的开口率。
图7是图6中阵列基板沿剖面线F-F的剖面图，参考图6和图7，可选的，薄膜晶体管131为顶栅结构，薄膜晶体管131的沟道区位于栅极210朝向基板10的一侧。这样设置，栅极210可以遮挡薄膜晶体管131的沟道区，避免了光线从有源层240临近像素电极132的一侧照射时，由于光照射沟道区产生光生载流子而导致漏电流增大。另外，像素单元130还可以包括遮光层134，遮光层134位于薄膜晶体管131的沟道区朝向基板10的一侧，遮光层134在基板10上的垂直投影覆盖薄膜晶体管131的沟道区在基板10上的垂直投影。具体的，通过设置遮光层134来遮挡薄膜晶体管131的沟道区，避免了光从有源层240临近基板10的一侧照射时，由于光照射沟道区产生光生载流子而导致漏电流增大，，提升了薄膜晶体管131的特性，进一步减小了像素电极电压的变化，提升了低频驱动时的显示效果。
需要说明的是，上述实施方式仅以液晶显示面板的阵列基板为例对本发明进行了说明，并非对本发明的限定，本发明还适用于有机发光等自主发光的显示面板。
本发明实施例还提供了一种显示面板，图8是本发明实施例提供的一种显示面板的示意图，参考图8，所述显示面板包括本发明任意实施例所述的阵列基板100。
可选的，所述显示面板还包括与阵列基板100相对设置的彩膜基板300，以及设置于阵列基板100和彩膜基板300之间的液晶层200。图9是本发明实施例提供的一种显示面板的透视图，参考图9，彩膜基板300上设置有黑矩阵310，薄膜晶体管131在彩膜基板300的垂直投影位于黑矩阵310内。
可选的，所述显示面板的画面刷新频率范围为0.5Hz-45Hz，当画面刷新频率大于45Hz时，会带来较大的功耗，造成资源和能量的损耗，而本发明提供的显示面板，通过上述实施方式中的结构设计，可以有效地降低显示面板的画面刷新频率，同时使得显示面板在较低频率下仍具有稳定的显示画面，从而在保证具有较高的画面显示质量的同时，降低了显示面板的功耗。
本实施例提供的显示面板，通过设置阵列基板上的薄膜晶体管的沟道区的有效长度大于或者等于像素单元沿扫描线延伸方向长度的三分之一，增大了薄膜晶体管的阻值，而薄膜晶体管两端的电压一定，从而降低了薄膜晶体管的漏电流，使得像素电极电压的变化减小，避免了像素电极电压减小量过大使显示画面出现闪烁，提升了显示面板的低频驱动显示效果，使得显示面板可以采用更低的画面刷新频率，降低了显示面板的功耗。
本发明实施例还提供了一种显示装置，图10是本发明实施例提供的一种显示装置的示意图，参考图10，显示装置400包括显示面板500，显示面板500包括本发明任意实施例所述的阵列基板，其中，显示装置400可以为如图中所示的手机，也可以为电脑、电视机、智能穿戴显示装置等，本实施例对此不作特殊限定。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (14)

1.一种阵列基板，其特征在于，包括：
基板；
形成在所述基板上的多条扫描线和多条数据线，所述多条扫描线和所述多条数据线绝缘交叉限定多个像素单元；
所述像素单元包括薄膜晶体管，所述薄膜晶体管的栅极与所述扫描线电连接，源极与所述数据线电连接，漏极与所述像素单元的像素电极电连接；所述薄膜晶体管的沟道区的有效长度大于或者等于所述像素单元沿所述扫描线延伸方向长度的三分之一；与所述薄膜晶体管的源极电连接的数据线和所述薄膜晶体管的漏极之间至少间隔一条所述数据线。
2.根据权利要求1所述的阵列基板，其特征在于，与所述薄膜晶体管的漏极相邻的两条数据线中，到与所述薄膜晶体管的源极电连接的所述数据线距离较近的为第一数据线，另一条为第二数据线，所述薄膜晶体管的漏极到所述第一数据线的距离大于到所述第二数据线的距离。
3.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管的源极和与所述薄膜晶体管的漏极相邻的所述数据线之一电连接。
4.根据权利要求3所述的阵列基板，其特征在于，所述薄膜晶体管的漏极到与所述薄膜晶体管的源极电连接的所述数据线的距离大于到另一条与所述薄膜晶体管的漏极相邻的所述数据线的距离。
5.根据权利要求1-4任一项所述的阵列基板，其特征在于，所述薄膜晶体管的沟道区的有效长度大于所述薄膜晶体管的源极与漏极沿所述扫描线延伸方向的距离。
6.根据权利要求1-4任一项所述的阵列基板，其特征在于，所述薄膜晶体管的沟道区在所述基板上的投影具有多个弯折部。
7.根据权利要求1-4任一项所述的阵列基板，其特征在于，所述薄膜晶体管的源极与漏极之间在沿所述数据线延伸的方向上至少间隔一条所述扫描线。
8.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管为低温多晶硅薄膜晶体管。
9.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管为顶栅结构，所述薄膜晶体管的沟道区位于所述栅极朝向所述基板的一侧。
10.根据权利要求1所述的阵列基板，其特征在于，所述像素单元还包括遮光层，所述遮光层位于所述薄膜晶体管的沟道区朝向所述基板的一侧，所述遮光层在所述基板上的垂直投影覆盖所述薄膜晶体管的沟道区在所述基板上的垂直投影。
11.一种显示面板，其特征在于，包括权利要求1-10任一项所述的阵列基板。
12.根据权利要求11所述的显示面板，其特征在于，还包括：
与所述阵列基板相对设置的彩膜基板；
所述彩膜基板上设置有黑矩阵，所述薄膜晶体管在所述彩膜基板的垂直投影位于所述黑矩阵内。
13.根据权利要求11所述的显示面板，其特征在于，所述显示面板的画面刷新频率范围为0.5Hz-45Hz。
14.一种显示装置，其特征在于，包括权利要求11-13任一项所述的显示面板。
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