CN106571384A - 凹入式数组器件 - Google Patents

凹入式数组器件 Download PDF

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CN106571384A
CN106571384A CN201610494377.6A CN201610494377A CN106571384A CN 106571384 A CN106571384 A CN 106571384A CN 201610494377 A CN201610494377 A CN 201610494377A CN 106571384 A CN106571384 A CN 106571384A
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吴铁将
施信益
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Micron Technology Inc
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Abstract

本发明公开了一种凹入式数组器件，包含一栅极沟槽，穿过有源区，栅极沟槽包括一第一侧墙、一第二侧墙以及一底表面。一突起部，位在栅极沟槽底部。突起部具有两相对侧墙以及一顶端部分，所述底表面包括所述顶端部分的表面与所述两相对侧墙的表面。一栅极氧化层，位于第一侧墙、第二侧墙，及底表面上。栅极氧化层于第一侧墙、第二侧墙具有第一厚度，在突起部的两相对侧墙上具有第二厚度，在突起部的顶端部分具有第三厚度，其中第一厚度大于第二厚度，第二厚度大于第三厚度。

Description

凹入式数组器件
技术领域
本发明涉及一种半导体装置，特别是涉及一种凹入式数组器件及其制作方法。
背景技术
多年来在存储器及半导体工业的趋势是持续缩减存储单元尺寸，以增加集成度及DRAM芯片的存储容量。随着存储器装置中存储单元密度的增加，制作在半导体衬底凹部的凹入式数组器件也越来越受到青睐。
在一般情况下，形成在衬底上的凹部(或栅极沟槽)具有相对的侧墙以及在侧墙之间延伸的底表面。栅极氧化物层先形成在凹部内，栅极结构接着沉积到凹部内，然后，将掺杂区域形成在衬底的主表面，构成源极和漏极。
现有技术的凹入式数组器件仍具有一些缺点。例如，现有技术的凹入式数组器件在栅极与漏极区域之间的重叠区域附近会有较高的栅极感应漏极漏电(GIDL)电流。在上述重叠区域，GIDL电流可能由带对带隧道(band to bandtunneling)效应导致，并且对薄氧化物存储单元器件造成操作上的限制以及保存时间(retention time)性能损失。虽然在上述重叠区域的GIDL电流可以通过增加栅极氧化层的厚度来减轻，但是另一方面回写性能将受到影响。
因此，有必要在本技术领域提供一种改良的凹入式数组器件，其能够克服上述缺点。
发明内容
本发明提供一种改良的凹入式数组器件，包含有一半导体衬底；至少一有源区，位在半导体衬底的一主表面；一沟槽隔离，在半导体衬底的主表面上并围绕有源区；至少一栅极沟槽，穿过有源区，其中栅极沟槽包括一第一侧墙、一第二侧墙，面对第一侧墙，以及一在第一侧墙和第二侧墙的之间延伸的底表面；一突起部，位于栅极沟槽的底部，其中突起部具有两相对侧墙以及一位于两相对侧墙之间的顶端部分，其中底表面包括顶端部分的表面与两相对侧墙的表面；一栅极氧化层，位在第一侧墙、第二侧墙，以及底表面上，其中栅极氧化层于第一侧墙、第二侧墙具有一第一厚度，在突起部的两相对侧墙上具有一第二厚度，在突起部的顶端部分具有一第三厚度，其中第一厚度大于第二厚度，第二厚度大于第三厚度；以及一凹入式栅极，位在栅极沟槽内。
无庸置疑的，本领域的技术人员读完接下来本发明较佳实施例的详细描述与图式后，均可了解本发明的目的。
附图说明
图1是依据本发明一实施例绘示的存储器单元数组的部分平面示意图。
图2A及图2B分别是沿图1中切线I-I’和II-II’所视的剖面示意视图。
图3A及图3B分别是沿图1中切线I-I’和II-II’所视的剖面示意视图，显示栅极氧化物生长增强/抑制植入步骤。
图4A及图4B分别是沿图1中切线I-I’和II-II’所视的剖面示意视图，显示栅极氧化层生长成不同厚度。
图5是依据本发明一实施例绘示的凹部的鞍形表面轮廓的三维立体图。
其中，附图标记说明如下：
10 有源区
12 沟槽隔离
12a 表面
20 氧化物生长增强植入
30 氧化物生长抑制植入
100 半导体衬底
102 栅极沟槽
102a 第一侧墙
102b第二侧墙
102c 底表面
110 硬掩膜
120 突起部
120a 侧墙
120b 侧墙
120c 顶端部分
130 栅极氧化层
141 共享源极区
142 漏极区域
160 凹入式栅极
210 位线
t1、t2、t3 厚度
具体实施方式
虽然本发明以实施例揭露如下，然而其并非用以限定本发明，任何熟习本领域之技术人员，在不脱离本发明之精神和范围内，当可作些许之更动与润饰，因此本发明的保护范围当依据附的申请专利范围界定的为准，且为了不使本发明的精神晦涩难懂，部分习知结构与工艺步骤的细节将不在此揭露。
关于晶体管和集成电路的制造中，术语“主表面”指的是其中制造有多个晶体管的半导体层的表面，例如，在一个平面工艺。如本文所用，术语“垂直”是指大致垂直相对于所述主表面。通常情况下，主表面是沿其单晶硅层的<100>平面，其上制造有场效应晶体管。
请参考图1、图2A、图2B，及图5。图1是依据本发明一实施绘示的存储器单元数组的部分平面示意图。图2A及图2B分别是沿图1中切线I-I’和II-II’所视的剖面示意视图。图5是依据本发明一实施例绘示的凹部的鞍形表面轮廓的三维立体图。以下将配合图式例示说明本发明实施例制造凹入式数组器件的方法。
首先，如图1所示，有源区10以矩阵形式设置在的半导体衬底上。每个有源区10被沟槽隔离12包围而彼此分离。根据所示的实施例，每个有源区10被两个栅极沟槽102穿过，使得每一个有源区10被分成三个区域，包括布置在每个有源区10的两端的两个漏极区域142以及两个栅极沟槽102之间的共享源极区域141。
两个栅极沟槽102沿第一方向(参考y轴)或字线(WL)方向延伸。覆盖在衬底的主表面的位线(DL)210仅用以说明目的。这些位线210沿第二方向(参考x轴)或位线(DL)方向延伸。
形成栅极沟槽102的做法，可以进行光刻工艺及干蚀刻工艺，以蚀刻通过硬掩膜110并进入半导体衬底100到预定的沟槽深度。
如图2A所示，每个栅极沟槽102包括第一侧墙102a、第二侧墙102b，面对第一侧墙102a，以及在第一侧墙102a和第二侧墙102b的之间延伸的底表面102c。如图2B和图5，一个突起部120形成在每个栅极沟槽102的底部，从而在每个栅极沟槽102提供一个鞍形表面轮廓。突起部120从沟槽隔离12的一个表面12a突出，并具有两个相对的，稍微弯曲的侧墙120a和120b。突起部120还具有两个侧墙120a和120b之间延伸的顶端部分120c。前述的底表面102c包括顶端部分120c的表面与所述两个侧墙120a和120b的表面。
如图3A和图3B所示，在形成栅极沟槽102后，可进行一氧化物生长增强植入(oxide growth enhancement implant)20沿所述DL方向及一指定角度对第一侧墙102a和第二侧墙102b植入卤素杂质。通过调整氧化物生长增强植入20的倾斜角，卤素杂质，如氟(F)可以被植入到只有第一侧墙102a和第二侧墙102b的上部。卤素杂质，如氟(F)加速氧化硅层的生长。
另一替代方式是，进行一氧化物生长抑制植入(oxide growth suppressionimplant)30沿WL方向将杂质如氮原子植入顶端部分120c和突起部120的侧墙120a及120b中。氮原子推迟氧化硅层的生长。在一些实施例中，氧化物生长增强植入20和氧化物生长抑制植入30两者均可被执行。
在完成的氧化物生长增强植入20或氧化物生长抑制植入30之后，进行一氧化工艺，在各栅极沟槽102内生长栅极氧化层130。栅极氧化层130具有至少三个不同厚度：在侧墙102a和102b为厚度t1，在侧墙120a和120b为厚度t2，以及在突起部120顶端部分120c为厚度t3。由于卤素杂质加速氧化硅层的生长，栅极氧化层130在侧墙102a和102b的厚度t1大于在侧墙120a和120b的厚度t2，并且在侧墙上120a和120b的厚度t2大于在凸起部120顶端部分120c的厚度t3(t1>t2>t3)。形成栅极氧化层130后，可在各栅极沟槽102内形成一个凹入式栅极160。
由于栅极氧化层130在突起部120的顶端部分120c具有较薄厚度t3，回写性能可以得到改进。栅极氧化物层130在侧墙102a和102b较厚，可以减轻栅极160和汲区142之间的重叠区域的GIDL电流。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种凹入式数组器件，其特征在于，包含有:
一半导体衬底；
至少一有源区，位在所述半导体衬底的一主表面；
一沟槽隔离，在所述半导体衬底的所述主表面上并围绕所述有源区；
至少一栅极沟槽，穿过所述有源区，其中所述栅极沟槽包括一第一侧墙、一第二侧墙，面对所述第一侧墙，以及一在所述第一侧墙和所述第二侧墙的之间延伸的底表面；
一突起部，位于所述栅极沟槽的底部，其中所述突起部具有两相对侧墙以及一位于所述两相对侧墙之间的顶端部分，其中所述底表面包括所述顶端部分的表面与所述两相对侧墙的表面；
一栅极氧化层，位在所述第一侧墙、所述第二侧墙，以及所述底表面上，其中所述栅极氧化层于所述第一侧墙、所述第二侧墙具有一第一厚度，在所述突起部的所述两相对侧墙上具有一第二厚度，在所述突起部的顶端部分具有一第三厚度，其中所述第一厚度大于所述第二厚度，所述第二厚度大于所述第三厚度；以及
一凹入式栅极，位在所述栅极沟槽内。
2.根据权利要求1所述的凹入式数组器件，其特征在于，另包含一源极区域，位在所述栅极沟槽一侧的所述有源区内，以及一漏极区域，位在所述栅极沟槽另一侧的所述有源区内。
3.根据权利要求1所述的凹入式数组器件，其特征在于，所述第一侧墙、所述第二侧墙以及所述表面在所述栅极沟槽内构成一鞍形表面轮廓。
4.根据权利要求1所述的凹入式数组器件，其特征在于，所述栅极沟槽沿着一字线方向延伸。
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