CN106409916A - 薄膜晶体管结构 - Google Patents
薄膜晶体管结构 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 94
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims description 29
- 230000003139 buffering effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 238000000034 method Methods 0.000 description 1
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- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
本发明公开了一种薄膜晶体管结构,其包含一基板、一第一金属层、一第一缓冲层、一半导体层、一第二金属层、一第二缓冲层以及一第三金属层,该第二金属层包含一间隔区,该半导体层包含一通道区,本发明通过该第一金属层以及第三金属层产生双闸极,通过双闸极结构夹合信道区,进而提升薄膜晶体管的开电流,达到元件驱动效率提升的目的。
Description
技术领域
本发明涉及一种薄膜晶体管结构,尤指具有双闸极的薄膜晶体管结构。
背景技术
平面显示器产业中,薄膜晶体管液晶显示器(TFTL-LCD)为当今炙手可热的产品,而在平面显示器产品中由于会大量应用薄膜晶体管,因此薄膜晶体管的质量优劣(如电流导通性等)对液晶显示器整体质量具有密不可分的关系。
当薄膜晶体管导通时电子会从源极扩散至汲极。在薄膜晶体管中,根据半导体层材料的不同可再细分为多晶硅薄膜晶体管以及非晶硅薄膜晶体管,多晶硅薄膜晶体管具有较高的载子迁移率的优点,但同时也伴随着具有较大漏电流的缺点,而非晶硅薄膜晶体管的载子迁移率比多晶硅薄膜晶体管低,此因素造成非晶硅半导体层具有较高的电阻率,进而限制了元件电流的导通性,故非晶硅薄膜晶体管的开电流也会间接造成驱动效率较不理想。
有鉴于此,对于现今薄膜晶体管的改进上,如何研发一种新颖的高驱动效率的薄膜晶体管,以改善上述所带来的不便,实为相关产业与企业公司当下不容忽视的一重要课题。
发明内容
本发明的一主要目的在于提供一种薄膜晶体管结构,其通过设置一第三金属层达到提升薄膜晶体管的驱动特性的目的。
本发明的一次要目的在于提供一种薄膜晶体管结构,通过设置一第三金属层达到优化电路布局的目的。
为了达到上述目的,本发明提出一种薄膜晶体管结构,其包含一基板、一第一金属层、一第一缓冲层、一半导体层、一第二金属层、一第二缓冲层以及一第三金属层,第一金属层设于基板上,第一缓冲层覆盖基板及第一金属层,半导体层设于第一缓冲层上,第二金属层设于半导体层的并具有一间隔区,第二缓冲层覆盖第二金属层,第三金属层设于第二缓冲层上,通过半导体层上下方的该第一金属层与该第三金属层产生双闸极,进而使开电流提升,以达到薄膜晶体管的驱动效率提升及电路布局优化等目的。
在本发明的一实施例中,该第一金属层的宽度大于该间隔区的宽度。
在本发明的一实施例中,该第二缓冲层上方具有至少一凹槽,该第三金属层设于该凹槽内。
在本发明的一实施例中,该第三金属层的宽度大于该间隔区的宽度。
在本发明的一实施例中,该第三金属层的宽度等于该间隔区的宽度。
在本发明的一实施例中,该第三金属层的宽度小于该间隔区的宽度。
在本发明的一实施例中,该半导体层中具有一通道区。
在本发明的一实施例中,该信道区的宽度小于该第三金属层的宽度。
在本发明的一实施例中,该信道区的宽度等于该第三金属层的宽度。
在本发明的一实施例中,该信道区的宽度大于该第三金属层的宽度。
附图说明
图1A为本发明第一实施例的结构示意图;
图1B为本发明第一实施例的俯视图;
图2A~图2F为本发明第一实施例的制作流程示意图;
图3A为本发明第二实施例的结构示意图;
图3B为本发明第二实施例的俯视图;
图4A为本发明第三实施例的结构示意图;
图4B为本发明第三实施例的俯视图。
附图标记说明:1-薄膜晶体管结构;11-基板;12-第一金属层;13-第一缓冲层;14-半导体层;141-通道区;15-第二金属层;151-间隔区;16-第二缓冲层;17-第三金属层;171-凹槽。
具体实施方式
为使审查员对本发明的特征及所达成的功效有更进一步的了解与认识,谨佐以实施例及配合图式,说明如后:
本发明的特色之一在于:鉴于薄膜晶体管的结构对晶体管的驱动效能以及电路布局小型化等需求日益增加,故,本发明提出一种薄膜晶体管结构,以增加开电流进而达到提升驱动效能以及优化电路布局面积等目的。
如图1A所示为本发明第一实施例的结构示意图。如图所示,其说明本实施例的元件及其连接关系,本实施例为一种薄膜晶体管结构1,其包含一基板11、一第一金属层12、一第一缓冲层13、一半导体层14、一第二金属层15、一第二缓冲层16与一第三金属层17,除此之外,于本实施例中该半导体层14具有一通道区141,于该第二金属层15具有一间隔区151以及于该第二缓冲层16的上方具有至少一凹槽171。
如图1B所示为本发明第一实施例的俯视图;其说明本实施例第二金属层15以及第三金属层17的相对关系,以俯视图视角来看,该第二金属层15具有多个部分,其分别作为薄膜晶体管的源极及汲极,图中虚框所涵盖的范围为该第三金属层17对应该第二金属层15的该间隔区151所设置的位置,由图可知,本实施例中该第三金属层17完全覆盖该间隔区151。
如图2A至图2F所示为本发明第一实施例的制作流程示意图,其说明本实施例的薄膜晶体管中各元件之间的连接关系;如图2A所示,该第一金属层12设于该基板11上,该第一金属层12作为薄膜晶体管的一闸极;如图2B所示,该第一缓冲层13覆盖该基板11及该第一金属层12;如图2C所示,该半导体层14设于该第一缓冲层13上,该半导体层14可为非晶硅半导体材料,但实际应用上并不限于此,亦可采用其他半导体材料,如多晶硅等;如图2D所示,该第二金属层15设于该半导体层14上,并具有一间隔区151,并通过该间隔区151将该第二金属层15区隔为两部分,以分别作为薄膜晶体管的源极及汲极,当施加适当电压于薄膜晶体管时该半导体层14会有电子在进行传递,进而电性连接该间隔区151相异两端的该第二金属层15;如图2E所示,该第二缓冲层16覆盖该第二金属层15以及该半导体层14;以及,如图2F所示,该第三金属层17设于该第二缓冲层16上,且该第三金属层17的宽度大于该间隔区151的宽度,该第三金属层17的材料可为金属元素、金属化合物或者金属氧化物,可作为薄膜晶体管的另一闸极。
承上所述,于本实施例中该第一金属层12的宽度与该间隔区151的宽度近似,此近似包含该第一金属层12的宽度大于、等于以及小于该间隔区151的宽度,最佳实施态样为该第一金属层12的宽度大于该间隔区151的宽度,如此可具有较佳的结构特性。此外,如图2F所示,于本实施例中亦可根据设计需求使该通道区141的宽度大于、等于或小于该第三金属层17的宽度,以调整薄膜晶体管的结构特性。
承上,本实施例为一薄膜晶体管结构1,其利用了该三金属层17,从而有别于该第一金属层12的另一闸极,该半导体层14与每一上、下方作为闸极所用的第一金属层12以及第二金属层15互相感应,从而通过该第一金属层12以及第三金属层17产生双闸极结构,并通过此双闸极结构夹合信道区141,以有效提升元件的开关速度与开电流(open-current),达到提升开电流并改善整体薄膜晶体管结构1的放电速度的目的,以提升驱动效能。
如图3A所示为本发明第二实施例的结构示意图。如图所示,其说明本实施例的元件及其连接关系,本实施例与前一实施例的差异在于,该第三金属层17的宽度等于该间隔区151的宽度,但本实施例中的细部元件及其连接关系与前一实施例相同,故不再赘述。
如图3B所示为本发明第二实施例的俯视图;其说明本实施例第二金属层15以及第三金属层17的相对关系,以俯视图视角来看,该第二金属层15具有多个部分,其分别作为薄膜晶体管的源极及汲极,图中虚框所涵盖的范围为该第三金属层17对应该第二金属层15的该间隔区151所设置的位置,由图可知,本实施例中该第三金属层17的宽度大于该间隔区151的宽度。如图3A所示,本发明中所述的该通道区141的宽度进一步而言指电子离子由该第二金属层15的任一端流向相对的另一端时的距离,换言之,由于该通道区141必须与该第二金属层15的两端直接连接,故可推知该通道区141的宽度将为该间隔区151的宽度再加上该第二金属层15的两端部分宽度,故该通道区141会稍大于该间隔区151的宽度。基于上述,由图3B可知,本实施例与前一实施例的另一差异在于,该第三金属层17对应该通道区141覆盖于该第二缓冲层16上。
如图4A所示为本发明第三实施例的结构示意图。如图所示,其说明本实施例的元件及其连接关系,本实施例与前述多个实施例的差异在于,该第三金属层17的宽度小于该间隔区151的宽度,但本实施例中的细部元件及其连接关与前述多个实施例相同,故不再赘述。
如图4B所示为本发明第三实施例的俯视图;其说明本实施例第二金属层15以及第三金属层17的相对关系,以俯视图视角来看,该第二金属层15具有多个部分,其分别作为薄膜晶体管的源极及汲极,图中虚框所涵盖的范围为该第三金属层17对应该第二金属层15的该间隔区151所设置的位置,由图可知,本实施例与前几个实施例的另一差异在于,该第三金属层17对应设置于该通道区141或该间隔区151的宽度范围内。
综上所述,本发明为一薄膜晶体管结构,其包含一基板、一第一金属层、一第一缓冲层、一半导体层、一第二金属层、一第二缓冲层以及一第三金属层,该第一金属层设于该基板上,该第一缓冲层覆盖该基板及该第一金属层,该半导体层设于该第一缓冲层上,该第二金属层设于该半导体层上,并具有一间隔区,该第二缓冲层覆盖该第二金属层及该半导体层,该第三金属层设于该第二缓冲层上,本发明通过所设置的第一金属层与第三金属层可各自对该半导体层产生感应形成双闸极,进而改善薄膜晶体管元件的驱动能力并同时优化电路布局。
以上所述仅为本发明的实施例而已,并非用来限定本发明实施的范围,故举凡依本发明权利要求范围所述的形状、构造、特征及精神所为的均等变化与修饰,均应包括于本发明的保护范围内。
Claims (10)
1.一种薄膜晶体管结构,其特征在于,包含:
一基板,
一第一金属层,设于该基板上;
一第一缓冲层,覆盖该基板及该第一金属层;
一半导体层,设于该第一缓冲层上;
一第二金属层,设于该半导体层上,并具有一间隔区;
一第二缓冲层,覆盖该第二金属层;以及
一第三金属层,设于该第二缓冲层上。
2.根据权利要求1所述的薄膜晶体管结构,其特征在于,该第一金属层的宽度大于该间隔区的宽度。
3.根据权利要求1所述的薄膜晶体管结构,其特征在于,该第二缓冲层上方具有至少一凹槽,该第三金属层设于该凹槽内。
4.根据权利要求1所述的薄膜晶体管结构,其特征在于,该第三金属层的宽度大于该间隔区的宽度。
5.根据权利要求1所述的薄膜晶体管结构,其特征在于,该第三金属层的宽度等于该间隔区的宽度。
6.根据权利要求1所述的薄膜晶体管结构,其特征在于,该第三金属层的宽度小于该间隔区的宽度。
7.根据权利要求1所述的薄膜晶体管结构,其特征在于,该半导体层中具有一通道区。
8.根据权利要求1所述的薄膜晶体管结构,其特征在于,该信道区的宽度小于该第三金属层的宽度。
9.根据权利要求1所述的薄膜晶体管结构,其特征在于,该信道区的宽度等于该第三金属层的宽度。
10.根据权利要求1所述的薄膜晶体管结构,其特征在于,该信道区的宽度大于该第三金属层的宽度。
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TW104124874A TW201704831A (zh) | 2015-07-31 | 2015-07-31 | 薄膜電晶體結構 |
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CN107946189A (zh) * | 2017-11-22 | 2018-04-20 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及其制备方法 |
CN108163840A (zh) * | 2017-12-27 | 2018-06-15 | 深圳市华星光电半导体显示技术有限公司 | 碳纳米管提纯方法、薄膜晶体管及制备方法 |
WO2020119249A1 (en) * | 2018-12-13 | 2020-06-18 | Boe Technology Group Co., Ltd. | Thin-film transistor for use with light-emitting apparatus and manufacturing method thereof |
US10777662B2 (en) | 2017-11-22 | 2020-09-15 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin film transistor and manufacturing method thereof |
Families Citing this family (1)
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US20170207642A1 (en) * | 2016-01-15 | 2017-07-20 | Renesas Electronics America Inc. | E-fuse/switch by back end of line (beol) process |
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CN107946189A (zh) * | 2017-11-22 | 2018-04-20 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及其制备方法 |
CN107946189B (zh) * | 2017-11-22 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及其制备方法 |
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WO2019127680A1 (zh) * | 2017-12-27 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | 碳纳米管提纯方法、薄膜晶体管及制备方法 |
CN108163840B (zh) * | 2017-12-27 | 2020-02-07 | 深圳市华星光电半导体显示技术有限公司 | 碳纳米管提纯方法、薄膜晶体管及制备方法 |
WO2020119249A1 (en) * | 2018-12-13 | 2020-06-18 | Boe Technology Group Co., Ltd. | Thin-film transistor for use with light-emitting apparatus and manufacturing method thereof |
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US20170033236A1 (en) | 2017-02-02 |
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